ev.c 5.8 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/slab.h>
  33. #include <linux/mman.h>
  34. #include <net/sock.h>
  35. #include "iw_cxgb4.h"
  36. static void post_qp_event(struct c4iw_dev *dev, struct c4iw_cq *chp,
  37. struct c4iw_qp *qhp,
  38. struct t4_cqe *err_cqe,
  39. enum ib_event_type ib_event)
  40. {
  41. struct ib_event event;
  42. struct c4iw_qp_attributes attrs;
  43. unsigned long flag;
  44. if ((qhp->attr.state == C4IW_QP_STATE_ERROR) ||
  45. (qhp->attr.state == C4IW_QP_STATE_TERMINATE)) {
  46. pr_err("%s AE after RTS - qpid 0x%x opcode %d status 0x%x "\
  47. "type %d wrid.hi 0x%x wrid.lo 0x%x\n",
  48. __func__, CQE_QPID(err_cqe), CQE_OPCODE(err_cqe),
  49. CQE_STATUS(err_cqe), CQE_TYPE(err_cqe),
  50. CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe));
  51. return;
  52. }
  53. printk(KERN_ERR MOD "AE qpid 0x%x opcode %d status 0x%x "
  54. "type %d wrid.hi 0x%x wrid.lo 0x%x\n",
  55. CQE_QPID(err_cqe), CQE_OPCODE(err_cqe),
  56. CQE_STATUS(err_cqe), CQE_TYPE(err_cqe),
  57. CQE_WRID_HI(err_cqe), CQE_WRID_LOW(err_cqe));
  58. if (qhp->attr.state == C4IW_QP_STATE_RTS) {
  59. attrs.next_state = C4IW_QP_STATE_TERMINATE;
  60. c4iw_modify_qp(qhp->rhp, qhp, C4IW_QP_ATTR_NEXT_STATE,
  61. &attrs, 0);
  62. }
  63. event.event = ib_event;
  64. event.device = chp->ibcq.device;
  65. if (ib_event == IB_EVENT_CQ_ERR)
  66. event.element.cq = &chp->ibcq;
  67. else
  68. event.element.qp = &qhp->ibqp;
  69. if (qhp->ibqp.event_handler)
  70. (*qhp->ibqp.event_handler)(&event, qhp->ibqp.qp_context);
  71. spin_lock_irqsave(&chp->comp_handler_lock, flag);
  72. (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
  73. spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
  74. }
  75. void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe)
  76. {
  77. struct c4iw_cq *chp;
  78. struct c4iw_qp *qhp;
  79. u32 cqid;
  80. spin_lock_irq(&dev->lock);
  81. qhp = get_qhp(dev, CQE_QPID(err_cqe));
  82. if (!qhp) {
  83. printk(KERN_ERR MOD "BAD AE qpid 0x%x opcode %d "
  84. "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
  85. CQE_QPID(err_cqe),
  86. CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
  87. CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
  88. CQE_WRID_LOW(err_cqe));
  89. spin_unlock_irq(&dev->lock);
  90. goto out;
  91. }
  92. if (SQ_TYPE(err_cqe))
  93. cqid = qhp->attr.scq;
  94. else
  95. cqid = qhp->attr.rcq;
  96. chp = get_chp(dev, cqid);
  97. if (!chp) {
  98. printk(KERN_ERR MOD "BAD AE cqid 0x%x qpid 0x%x opcode %d "
  99. "status 0x%x type %d wrid.hi 0x%x wrid.lo 0x%x\n",
  100. cqid, CQE_QPID(err_cqe),
  101. CQE_OPCODE(err_cqe), CQE_STATUS(err_cqe),
  102. CQE_TYPE(err_cqe), CQE_WRID_HI(err_cqe),
  103. CQE_WRID_LOW(err_cqe));
  104. spin_unlock_irq(&dev->lock);
  105. goto out;
  106. }
  107. c4iw_qp_add_ref(&qhp->ibqp);
  108. atomic_inc(&chp->refcnt);
  109. spin_unlock_irq(&dev->lock);
  110. /* Bad incoming write */
  111. if (RQ_TYPE(err_cqe) &&
  112. (CQE_OPCODE(err_cqe) == FW_RI_RDMA_WRITE)) {
  113. post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_REQ_ERR);
  114. goto done;
  115. }
  116. switch (CQE_STATUS(err_cqe)) {
  117. /* Completion Events */
  118. case T4_ERR_SUCCESS:
  119. printk(KERN_ERR MOD "AE with status 0!\n");
  120. break;
  121. case T4_ERR_STAG:
  122. case T4_ERR_PDID:
  123. case T4_ERR_QPID:
  124. case T4_ERR_ACCESS:
  125. case T4_ERR_WRAP:
  126. case T4_ERR_BOUND:
  127. case T4_ERR_INVALIDATE_SHARED_MR:
  128. case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
  129. post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_ACCESS_ERR);
  130. break;
  131. /* Device Fatal Errors */
  132. case T4_ERR_ECC:
  133. case T4_ERR_ECC_PSTAG:
  134. case T4_ERR_INTERNAL_ERR:
  135. post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_DEVICE_FATAL);
  136. break;
  137. /* QP Fatal Errors */
  138. case T4_ERR_OUT_OF_RQE:
  139. case T4_ERR_PBL_ADDR_BOUND:
  140. case T4_ERR_CRC:
  141. case T4_ERR_MARKER:
  142. case T4_ERR_PDU_LEN_ERR:
  143. case T4_ERR_DDP_VERSION:
  144. case T4_ERR_RDMA_VERSION:
  145. case T4_ERR_OPCODE:
  146. case T4_ERR_DDP_QUEUE_NUM:
  147. case T4_ERR_MSN:
  148. case T4_ERR_TBIT:
  149. case T4_ERR_MO:
  150. case T4_ERR_MSN_GAP:
  151. case T4_ERR_MSN_RANGE:
  152. case T4_ERR_RQE_ADDR_BOUND:
  153. case T4_ERR_IRD_OVERFLOW:
  154. post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
  155. break;
  156. default:
  157. printk(KERN_ERR MOD "Unknown T4 status 0x%x QPID 0x%x\n",
  158. CQE_STATUS(err_cqe), qhp->wq.sq.qid);
  159. post_qp_event(dev, chp, qhp, err_cqe, IB_EVENT_QP_FATAL);
  160. break;
  161. }
  162. done:
  163. if (atomic_dec_and_test(&chp->refcnt))
  164. wake_up(&chp->wait);
  165. c4iw_qp_rem_ref(&qhp->ibqp);
  166. out:
  167. return;
  168. }
  169. int c4iw_ev_handler(struct c4iw_dev *dev, u32 qid)
  170. {
  171. struct c4iw_cq *chp;
  172. unsigned long flag;
  173. chp = get_chp(dev, qid);
  174. if (chp) {
  175. spin_lock_irqsave(&chp->comp_handler_lock, flag);
  176. (*chp->ibcq.comp_handler)(&chp->ibcq, chp->ibcq.cq_context);
  177. spin_unlock_irqrestore(&chp->comp_handler_lock, flag);
  178. } else
  179. PDBG("%s unknown cqid 0x%x\n", __func__, qid);
  180. return 0;
  181. }