radeon_test.c 13 KB

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  1. /*
  2. * Copyright 2009 VMware, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Michel Dänzer
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/radeon_drm.h>
  26. #include "radeon_reg.h"
  27. #include "radeon.h"
  28. #define RADEON_TEST_COPY_BLIT 1
  29. #define RADEON_TEST_COPY_DMA 0
  30. /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
  31. static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
  32. {
  33. struct radeon_bo *vram_obj = NULL;
  34. struct radeon_bo **gtt_obj = NULL;
  35. struct radeon_fence *fence = NULL;
  36. uint64_t gtt_addr, vram_addr;
  37. unsigned i, n, size;
  38. int r, ring;
  39. switch (flag) {
  40. case RADEON_TEST_COPY_DMA:
  41. ring = radeon_copy_dma_ring_index(rdev);
  42. break;
  43. case RADEON_TEST_COPY_BLIT:
  44. ring = radeon_copy_blit_ring_index(rdev);
  45. break;
  46. default:
  47. DRM_ERROR("Unknown copy method\n");
  48. return;
  49. }
  50. size = 1024 * 1024;
  51. /* Number of tests =
  52. * (Total GTT - IB pool - writeback page - ring buffers) / test size
  53. */
  54. n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
  55. for (i = 0; i < RADEON_NUM_RINGS; ++i)
  56. n -= rdev->ring[i].ring_size;
  57. if (rdev->wb.wb_obj)
  58. n -= RADEON_GPU_PAGE_SIZE;
  59. if (rdev->ih.ring_obj)
  60. n -= rdev->ih.ring_size;
  61. n /= size;
  62. gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
  63. if (!gtt_obj) {
  64. DRM_ERROR("Failed to allocate %d pointers\n", n);
  65. r = 1;
  66. goto out_cleanup;
  67. }
  68. r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  69. NULL, &vram_obj);
  70. if (r) {
  71. DRM_ERROR("Failed to create VRAM object\n");
  72. goto out_cleanup;
  73. }
  74. r = radeon_bo_reserve(vram_obj, false);
  75. if (unlikely(r != 0))
  76. goto out_cleanup;
  77. r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
  78. if (r) {
  79. DRM_ERROR("Failed to pin VRAM object\n");
  80. goto out_cleanup;
  81. }
  82. for (i = 0; i < n; i++) {
  83. void *gtt_map, *vram_map;
  84. void **gtt_start, **gtt_end;
  85. void **vram_start, **vram_end;
  86. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  87. RADEON_GEM_DOMAIN_GTT, NULL, gtt_obj + i);
  88. if (r) {
  89. DRM_ERROR("Failed to create GTT object %d\n", i);
  90. goto out_cleanup;
  91. }
  92. r = radeon_bo_reserve(gtt_obj[i], false);
  93. if (unlikely(r != 0))
  94. goto out_cleanup;
  95. r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
  96. if (r) {
  97. DRM_ERROR("Failed to pin GTT object %d\n", i);
  98. goto out_cleanup;
  99. }
  100. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  101. if (r) {
  102. DRM_ERROR("Failed to map GTT object %d\n", i);
  103. goto out_cleanup;
  104. }
  105. for (gtt_start = gtt_map, gtt_end = gtt_map + size;
  106. gtt_start < gtt_end;
  107. gtt_start++)
  108. *gtt_start = gtt_start;
  109. radeon_bo_kunmap(gtt_obj[i]);
  110. if (ring == R600_RING_TYPE_DMA_INDEX)
  111. r = radeon_copy_dma(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  112. else
  113. r = radeon_copy_blit(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  114. if (r) {
  115. DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
  116. goto out_cleanup;
  117. }
  118. r = radeon_fence_wait(fence, false);
  119. if (r) {
  120. DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
  121. goto out_cleanup;
  122. }
  123. radeon_fence_unref(&fence);
  124. r = radeon_bo_kmap(vram_obj, &vram_map);
  125. if (r) {
  126. DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
  127. goto out_cleanup;
  128. }
  129. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  130. vram_start = vram_map, vram_end = vram_map + size;
  131. vram_start < vram_end;
  132. gtt_start++, vram_start++) {
  133. if (*vram_start != gtt_start) {
  134. DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
  135. "expected 0x%p (GTT/VRAM offset "
  136. "0x%16llx/0x%16llx)\n",
  137. i, *vram_start, gtt_start,
  138. (unsigned long long)
  139. (gtt_addr - rdev->mc.gtt_start +
  140. (void*)gtt_start - gtt_map),
  141. (unsigned long long)
  142. (vram_addr - rdev->mc.vram_start +
  143. (void*)gtt_start - gtt_map));
  144. radeon_bo_kunmap(vram_obj);
  145. goto out_cleanup;
  146. }
  147. *vram_start = vram_start;
  148. }
  149. radeon_bo_kunmap(vram_obj);
  150. if (ring == R600_RING_TYPE_DMA_INDEX)
  151. r = radeon_copy_dma(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  152. else
  153. r = radeon_copy_blit(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, &fence);
  154. if (r) {
  155. DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
  156. goto out_cleanup;
  157. }
  158. r = radeon_fence_wait(fence, false);
  159. if (r) {
  160. DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
  161. goto out_cleanup;
  162. }
  163. radeon_fence_unref(&fence);
  164. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  165. if (r) {
  166. DRM_ERROR("Failed to map GTT object after copy %d\n", i);
  167. goto out_cleanup;
  168. }
  169. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  170. vram_start = vram_map, vram_end = vram_map + size;
  171. gtt_start < gtt_end;
  172. gtt_start++, vram_start++) {
  173. if (*gtt_start != vram_start) {
  174. DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
  175. "expected 0x%p (VRAM/GTT offset "
  176. "0x%16llx/0x%16llx)\n",
  177. i, *gtt_start, vram_start,
  178. (unsigned long long)
  179. (vram_addr - rdev->mc.vram_start +
  180. (void*)vram_start - vram_map),
  181. (unsigned long long)
  182. (gtt_addr - rdev->mc.gtt_start +
  183. (void*)vram_start - vram_map));
  184. radeon_bo_kunmap(gtt_obj[i]);
  185. goto out_cleanup;
  186. }
  187. }
  188. radeon_bo_kunmap(gtt_obj[i]);
  189. DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
  190. gtt_addr - rdev->mc.gtt_start);
  191. }
  192. out_cleanup:
  193. if (vram_obj) {
  194. if (radeon_bo_is_reserved(vram_obj)) {
  195. radeon_bo_unpin(vram_obj);
  196. radeon_bo_unreserve(vram_obj);
  197. }
  198. radeon_bo_unref(&vram_obj);
  199. }
  200. if (gtt_obj) {
  201. for (i = 0; i < n; i++) {
  202. if (gtt_obj[i]) {
  203. if (radeon_bo_is_reserved(gtt_obj[i])) {
  204. radeon_bo_unpin(gtt_obj[i]);
  205. radeon_bo_unreserve(gtt_obj[i]);
  206. }
  207. radeon_bo_unref(&gtt_obj[i]);
  208. }
  209. }
  210. kfree(gtt_obj);
  211. }
  212. if (fence) {
  213. radeon_fence_unref(&fence);
  214. }
  215. if (r) {
  216. printk(KERN_WARNING "Error while testing BO move.\n");
  217. }
  218. }
  219. void radeon_test_moves(struct radeon_device *rdev)
  220. {
  221. if (rdev->asic->copy.dma)
  222. radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
  223. if (rdev->asic->copy.blit)
  224. radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
  225. }
  226. void radeon_test_ring_sync(struct radeon_device *rdev,
  227. struct radeon_ring *ringA,
  228. struct radeon_ring *ringB)
  229. {
  230. struct radeon_fence *fence1 = NULL, *fence2 = NULL;
  231. struct radeon_semaphore *semaphore = NULL;
  232. int r;
  233. r = radeon_semaphore_create(rdev, &semaphore);
  234. if (r) {
  235. DRM_ERROR("Failed to create semaphore\n");
  236. goto out_cleanup;
  237. }
  238. r = radeon_ring_lock(rdev, ringA, 64);
  239. if (r) {
  240. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  241. goto out_cleanup;
  242. }
  243. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  244. r = radeon_fence_emit(rdev, &fence1, ringA->idx);
  245. if (r) {
  246. DRM_ERROR("Failed to emit fence 1\n");
  247. radeon_ring_unlock_undo(rdev, ringA);
  248. goto out_cleanup;
  249. }
  250. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  251. r = radeon_fence_emit(rdev, &fence2, ringA->idx);
  252. if (r) {
  253. DRM_ERROR("Failed to emit fence 2\n");
  254. radeon_ring_unlock_undo(rdev, ringA);
  255. goto out_cleanup;
  256. }
  257. radeon_ring_unlock_commit(rdev, ringA);
  258. mdelay(1000);
  259. if (radeon_fence_signaled(fence1)) {
  260. DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
  261. goto out_cleanup;
  262. }
  263. r = radeon_ring_lock(rdev, ringB, 64);
  264. if (r) {
  265. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  266. goto out_cleanup;
  267. }
  268. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  269. radeon_ring_unlock_commit(rdev, ringB);
  270. r = radeon_fence_wait(fence1, false);
  271. if (r) {
  272. DRM_ERROR("Failed to wait for sync fence 1\n");
  273. goto out_cleanup;
  274. }
  275. mdelay(1000);
  276. if (radeon_fence_signaled(fence2)) {
  277. DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
  278. goto out_cleanup;
  279. }
  280. r = radeon_ring_lock(rdev, ringB, 64);
  281. if (r) {
  282. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  283. goto out_cleanup;
  284. }
  285. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  286. radeon_ring_unlock_commit(rdev, ringB);
  287. r = radeon_fence_wait(fence2, false);
  288. if (r) {
  289. DRM_ERROR("Failed to wait for sync fence 1\n");
  290. goto out_cleanup;
  291. }
  292. out_cleanup:
  293. radeon_semaphore_free(rdev, &semaphore, NULL);
  294. if (fence1)
  295. radeon_fence_unref(&fence1);
  296. if (fence2)
  297. radeon_fence_unref(&fence2);
  298. if (r)
  299. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  300. }
  301. static void radeon_test_ring_sync2(struct radeon_device *rdev,
  302. struct radeon_ring *ringA,
  303. struct radeon_ring *ringB,
  304. struct radeon_ring *ringC)
  305. {
  306. struct radeon_fence *fenceA = NULL, *fenceB = NULL;
  307. struct radeon_semaphore *semaphore = NULL;
  308. bool sigA, sigB;
  309. int i, r;
  310. r = radeon_semaphore_create(rdev, &semaphore);
  311. if (r) {
  312. DRM_ERROR("Failed to create semaphore\n");
  313. goto out_cleanup;
  314. }
  315. r = radeon_ring_lock(rdev, ringA, 64);
  316. if (r) {
  317. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  318. goto out_cleanup;
  319. }
  320. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  321. r = radeon_fence_emit(rdev, &fenceA, ringA->idx);
  322. if (r) {
  323. DRM_ERROR("Failed to emit sync fence 1\n");
  324. radeon_ring_unlock_undo(rdev, ringA);
  325. goto out_cleanup;
  326. }
  327. radeon_ring_unlock_commit(rdev, ringA);
  328. r = radeon_ring_lock(rdev, ringB, 64);
  329. if (r) {
  330. DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
  331. goto out_cleanup;
  332. }
  333. radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
  334. r = radeon_fence_emit(rdev, &fenceB, ringB->idx);
  335. if (r) {
  336. DRM_ERROR("Failed to create sync fence 2\n");
  337. radeon_ring_unlock_undo(rdev, ringB);
  338. goto out_cleanup;
  339. }
  340. radeon_ring_unlock_commit(rdev, ringB);
  341. mdelay(1000);
  342. if (radeon_fence_signaled(fenceA)) {
  343. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  344. goto out_cleanup;
  345. }
  346. if (radeon_fence_signaled(fenceB)) {
  347. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  348. goto out_cleanup;
  349. }
  350. r = radeon_ring_lock(rdev, ringC, 64);
  351. if (r) {
  352. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  353. goto out_cleanup;
  354. }
  355. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  356. radeon_ring_unlock_commit(rdev, ringC);
  357. for (i = 0; i < 30; ++i) {
  358. mdelay(100);
  359. sigA = radeon_fence_signaled(fenceA);
  360. sigB = radeon_fence_signaled(fenceB);
  361. if (sigA || sigB)
  362. break;
  363. }
  364. if (!sigA && !sigB) {
  365. DRM_ERROR("Neither fence A nor B has been signaled\n");
  366. goto out_cleanup;
  367. } else if (sigA && sigB) {
  368. DRM_ERROR("Both fence A and B has been signaled\n");
  369. goto out_cleanup;
  370. }
  371. DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
  372. r = radeon_ring_lock(rdev, ringC, 64);
  373. if (r) {
  374. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  375. goto out_cleanup;
  376. }
  377. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  378. radeon_ring_unlock_commit(rdev, ringC);
  379. mdelay(1000);
  380. r = radeon_fence_wait(fenceA, false);
  381. if (r) {
  382. DRM_ERROR("Failed to wait for sync fence A\n");
  383. goto out_cleanup;
  384. }
  385. r = radeon_fence_wait(fenceB, false);
  386. if (r) {
  387. DRM_ERROR("Failed to wait for sync fence B\n");
  388. goto out_cleanup;
  389. }
  390. out_cleanup:
  391. radeon_semaphore_free(rdev, &semaphore, NULL);
  392. if (fenceA)
  393. radeon_fence_unref(&fenceA);
  394. if (fenceB)
  395. radeon_fence_unref(&fenceB);
  396. if (r)
  397. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  398. }
  399. void radeon_test_syncing(struct radeon_device *rdev)
  400. {
  401. int i, j, k;
  402. for (i = 1; i < RADEON_NUM_RINGS; ++i) {
  403. struct radeon_ring *ringA = &rdev->ring[i];
  404. if (!ringA->ready)
  405. continue;
  406. for (j = 0; j < i; ++j) {
  407. struct radeon_ring *ringB = &rdev->ring[j];
  408. if (!ringB->ready)
  409. continue;
  410. DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
  411. radeon_test_ring_sync(rdev, ringA, ringB);
  412. DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
  413. radeon_test_ring_sync(rdev, ringB, ringA);
  414. for (k = 0; k < j; ++k) {
  415. struct radeon_ring *ringC = &rdev->ring[k];
  416. if (!ringC->ready)
  417. continue;
  418. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
  419. radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
  420. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
  421. radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
  422. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
  423. radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
  424. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
  425. radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
  426. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
  427. radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
  428. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
  429. radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
  430. }
  431. }
  432. }
  433. }