omap_irq.c 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322
  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_irq.c
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. * Author: Rob Clark <rob.clark@linaro.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "omap_drv.h"
  20. static DEFINE_SPINLOCK(list_lock);
  21. static void omap_irq_error_handler(struct omap_drm_irq *irq,
  22. uint32_t irqstatus)
  23. {
  24. DRM_ERROR("errors: %08x\n", irqstatus);
  25. }
  26. /* call with list_lock and dispc runtime held */
  27. static void omap_irq_update(struct drm_device *dev)
  28. {
  29. struct omap_drm_private *priv = dev->dev_private;
  30. struct omap_drm_irq *irq;
  31. uint32_t irqmask = priv->vblank_mask;
  32. BUG_ON(!spin_is_locked(&list_lock));
  33. list_for_each_entry(irq, &priv->irq_list, node)
  34. irqmask |= irq->irqmask;
  35. DBG("irqmask=%08x", irqmask);
  36. dispc_write_irqenable(irqmask);
  37. dispc_read_irqenable(); /* flush posted write */
  38. }
  39. void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq)
  40. {
  41. struct omap_drm_private *priv = dev->dev_private;
  42. unsigned long flags;
  43. dispc_runtime_get();
  44. spin_lock_irqsave(&list_lock, flags);
  45. if (!WARN_ON(irq->registered)) {
  46. irq->registered = true;
  47. list_add(&irq->node, &priv->irq_list);
  48. omap_irq_update(dev);
  49. }
  50. spin_unlock_irqrestore(&list_lock, flags);
  51. dispc_runtime_put();
  52. }
  53. void omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq)
  54. {
  55. unsigned long flags;
  56. dispc_runtime_get();
  57. spin_lock_irqsave(&list_lock, flags);
  58. if (!WARN_ON(!irq->registered)) {
  59. irq->registered = false;
  60. list_del(&irq->node);
  61. omap_irq_update(dev);
  62. }
  63. spin_unlock_irqrestore(&list_lock, flags);
  64. dispc_runtime_put();
  65. }
  66. struct omap_irq_wait {
  67. struct omap_drm_irq irq;
  68. int count;
  69. };
  70. static DECLARE_WAIT_QUEUE_HEAD(wait_event);
  71. static void wait_irq(struct omap_drm_irq *irq, uint32_t irqstatus)
  72. {
  73. struct omap_irq_wait *wait =
  74. container_of(irq, struct omap_irq_wait, irq);
  75. wait->count--;
  76. wake_up_all(&wait_event);
  77. }
  78. struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
  79. uint32_t irqmask, int count)
  80. {
  81. struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
  82. wait->irq.irq = wait_irq;
  83. wait->irq.irqmask = irqmask;
  84. wait->count = count;
  85. omap_irq_register(dev, &wait->irq);
  86. return wait;
  87. }
  88. int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
  89. unsigned long timeout)
  90. {
  91. int ret = wait_event_timeout(wait_event, (wait->count <= 0), timeout);
  92. omap_irq_unregister(dev, &wait->irq);
  93. kfree(wait);
  94. if (ret == 0)
  95. return -1;
  96. return 0;
  97. }
  98. /**
  99. * enable_vblank - enable vblank interrupt events
  100. * @dev: DRM device
  101. * @crtc: which irq to enable
  102. *
  103. * Enable vblank interrupts for @crtc. If the device doesn't have
  104. * a hardware vblank counter, this routine should be a no-op, since
  105. * interrupts will have to stay on to keep the count accurate.
  106. *
  107. * RETURNS
  108. * Zero on success, appropriate errno if the given @crtc's vblank
  109. * interrupt cannot be enabled.
  110. */
  111. int omap_irq_enable_vblank(struct drm_device *dev, int crtc)
  112. {
  113. struct omap_drm_private *priv = dev->dev_private;
  114. unsigned long flags;
  115. DBG("dev=%p, crtc=%d", dev, crtc);
  116. dispc_runtime_get();
  117. spin_lock_irqsave(&list_lock, flags);
  118. priv->vblank_mask |= pipe2vbl(crtc);
  119. omap_irq_update(dev);
  120. spin_unlock_irqrestore(&list_lock, flags);
  121. dispc_runtime_put();
  122. return 0;
  123. }
  124. /**
  125. * disable_vblank - disable vblank interrupt events
  126. * @dev: DRM device
  127. * @crtc: which irq to enable
  128. *
  129. * Disable vblank interrupts for @crtc. If the device doesn't have
  130. * a hardware vblank counter, this routine should be a no-op, since
  131. * interrupts will have to stay on to keep the count accurate.
  132. */
  133. void omap_irq_disable_vblank(struct drm_device *dev, int crtc)
  134. {
  135. struct omap_drm_private *priv = dev->dev_private;
  136. unsigned long flags;
  137. DBG("dev=%p, crtc=%d", dev, crtc);
  138. dispc_runtime_get();
  139. spin_lock_irqsave(&list_lock, flags);
  140. priv->vblank_mask &= ~pipe2vbl(crtc);
  141. omap_irq_update(dev);
  142. spin_unlock_irqrestore(&list_lock, flags);
  143. dispc_runtime_put();
  144. }
  145. irqreturn_t omap_irq_handler(DRM_IRQ_ARGS)
  146. {
  147. struct drm_device *dev = (struct drm_device *) arg;
  148. struct omap_drm_private *priv = dev->dev_private;
  149. struct omap_drm_irq *handler, *n;
  150. unsigned long flags;
  151. unsigned int id;
  152. u32 irqstatus;
  153. irqstatus = dispc_read_irqstatus();
  154. dispc_clear_irqstatus(irqstatus);
  155. dispc_read_irqstatus(); /* flush posted write */
  156. VERB("irqs: %08x", irqstatus);
  157. for (id = 0; id < priv->num_crtcs; id++)
  158. if (irqstatus & pipe2vbl(id))
  159. drm_handle_vblank(dev, id);
  160. spin_lock_irqsave(&list_lock, flags);
  161. list_for_each_entry_safe(handler, n, &priv->irq_list, node) {
  162. if (handler->irqmask & irqstatus) {
  163. spin_unlock_irqrestore(&list_lock, flags);
  164. handler->irq(handler, handler->irqmask & irqstatus);
  165. spin_lock_irqsave(&list_lock, flags);
  166. }
  167. }
  168. spin_unlock_irqrestore(&list_lock, flags);
  169. return IRQ_HANDLED;
  170. }
  171. void omap_irq_preinstall(struct drm_device *dev)
  172. {
  173. DBG("dev=%p", dev);
  174. dispc_runtime_get();
  175. dispc_clear_irqstatus(0xffffffff);
  176. dispc_runtime_put();
  177. }
  178. int omap_irq_postinstall(struct drm_device *dev)
  179. {
  180. struct omap_drm_private *priv = dev->dev_private;
  181. struct omap_drm_irq *error_handler = &priv->error_handler;
  182. DBG("dev=%p", dev);
  183. INIT_LIST_HEAD(&priv->irq_list);
  184. error_handler->irq = omap_irq_error_handler;
  185. error_handler->irqmask = DISPC_IRQ_OCP_ERR;
  186. /* for now ignore DISPC_IRQ_SYNC_LOST_DIGIT.. really I think
  187. * we just need to ignore it while enabling tv-out
  188. */
  189. error_handler->irqmask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
  190. omap_irq_register(dev, error_handler);
  191. return 0;
  192. }
  193. void omap_irq_uninstall(struct drm_device *dev)
  194. {
  195. DBG("dev=%p", dev);
  196. // TODO prolly need to call drm_irq_uninstall() somewhere too
  197. }
  198. /*
  199. * We need a special version, instead of just using drm_irq_install(),
  200. * because we need to register the irq via omapdss. Once omapdss and
  201. * omapdrm are merged together we can assign the dispc hwmod data to
  202. * ourselves and drop these and just use drm_irq_{install,uninstall}()
  203. */
  204. int omap_drm_irq_install(struct drm_device *dev)
  205. {
  206. int ret;
  207. mutex_lock(&dev->struct_mutex);
  208. if (dev->irq_enabled) {
  209. mutex_unlock(&dev->struct_mutex);
  210. return -EBUSY;
  211. }
  212. dev->irq_enabled = 1;
  213. mutex_unlock(&dev->struct_mutex);
  214. /* Before installing handler */
  215. if (dev->driver->irq_preinstall)
  216. dev->driver->irq_preinstall(dev);
  217. ret = dispc_request_irq(dev->driver->irq_handler, dev);
  218. if (ret < 0) {
  219. mutex_lock(&dev->struct_mutex);
  220. dev->irq_enabled = 0;
  221. mutex_unlock(&dev->struct_mutex);
  222. return ret;
  223. }
  224. /* After installing handler */
  225. if (dev->driver->irq_postinstall)
  226. ret = dev->driver->irq_postinstall(dev);
  227. if (ret < 0) {
  228. mutex_lock(&dev->struct_mutex);
  229. dev->irq_enabled = 0;
  230. mutex_unlock(&dev->struct_mutex);
  231. dispc_free_irq(dev);
  232. }
  233. return ret;
  234. }
  235. int omap_drm_irq_uninstall(struct drm_device *dev)
  236. {
  237. unsigned long irqflags;
  238. int irq_enabled, i;
  239. mutex_lock(&dev->struct_mutex);
  240. irq_enabled = dev->irq_enabled;
  241. dev->irq_enabled = 0;
  242. mutex_unlock(&dev->struct_mutex);
  243. /*
  244. * Wake up any waiters so they don't hang.
  245. */
  246. if (dev->num_crtcs) {
  247. spin_lock_irqsave(&dev->vbl_lock, irqflags);
  248. for (i = 0; i < dev->num_crtcs; i++) {
  249. DRM_WAKEUP(&dev->vbl_queue[i]);
  250. dev->vblank_enabled[i] = 0;
  251. dev->last_vblank[i] =
  252. dev->driver->get_vblank_counter(dev, i);
  253. }
  254. spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
  255. }
  256. if (!irq_enabled)
  257. return -EINVAL;
  258. if (dev->driver->irq_uninstall)
  259. dev->driver->irq_uninstall(dev);
  260. dispc_free_irq(dev);
  261. return 0;
  262. }