nouveau_perf.c 10 KB

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  1. /*
  2. * Copyright 2010 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <drm/drmP.h>
  25. #include "nouveau_drm.h"
  26. #include "nouveau_reg.h"
  27. #include "nouveau_pm.h"
  28. static u8 *
  29. nouveau_perf_table(struct drm_device *dev, u8 *ver)
  30. {
  31. struct nouveau_drm *drm = nouveau_drm(dev);
  32. struct nvbios *bios = &drm->vbios;
  33. struct bit_entry P;
  34. if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) {
  35. u8 *perf = ROMPTR(dev, P.data[0]);
  36. if (perf) {
  37. *ver = perf[0];
  38. return perf;
  39. }
  40. }
  41. if (bios->type == NVBIOS_BMP) {
  42. if (bios->data[bios->offset + 6] >= 0x25) {
  43. u8 *perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
  44. if (perf) {
  45. *ver = perf[1];
  46. return perf;
  47. }
  48. }
  49. }
  50. return NULL;
  51. }
  52. static u8 *
  53. nouveau_perf_entry(struct drm_device *dev, int idx,
  54. u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  55. {
  56. u8 *perf = nouveau_perf_table(dev, ver);
  57. if (perf) {
  58. if (*ver >= 0x12 && *ver < 0x20 && idx < perf[2]) {
  59. *hdr = perf[3];
  60. *cnt = 0;
  61. *len = 0;
  62. return perf + perf[0] + idx * perf[3];
  63. } else
  64. if (*ver >= 0x20 && *ver < 0x40 && idx < perf[2]) {
  65. *hdr = perf[3];
  66. *cnt = perf[4];
  67. *len = perf[5];
  68. return perf + perf[1] + idx * (*hdr + (*cnt * *len));
  69. } else
  70. if (*ver >= 0x40 && *ver < 0x41 && idx < perf[5]) {
  71. *hdr = perf[2];
  72. *cnt = perf[4];
  73. *len = perf[3];
  74. return perf + perf[1] + idx * (*hdr + (*cnt * *len));
  75. }
  76. }
  77. return NULL;
  78. }
  79. u8 *
  80. nouveau_perf_rammap(struct drm_device *dev, u32 freq,
  81. u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
  82. {
  83. struct nouveau_drm *drm = nouveau_drm(dev);
  84. struct bit_entry P;
  85. u8 *perf, i = 0;
  86. if (!bit_table(dev, 'P', &P) && P.version == 2) {
  87. u8 *rammap = ROMPTR(dev, P.data[4]);
  88. if (rammap) {
  89. u8 *ramcfg = rammap + rammap[1];
  90. *ver = rammap[0];
  91. *hdr = rammap[2];
  92. *cnt = rammap[4];
  93. *len = rammap[3];
  94. freq /= 1000;
  95. for (i = 0; i < rammap[5]; i++) {
  96. if (freq >= ROM16(ramcfg[0]) &&
  97. freq <= ROM16(ramcfg[2]))
  98. return ramcfg;
  99. ramcfg += *hdr + (*cnt * *len);
  100. }
  101. }
  102. return NULL;
  103. }
  104. if (nv_device(drm->device)->chipset == 0x49 ||
  105. nv_device(drm->device)->chipset == 0x4b)
  106. freq /= 2;
  107. while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) {
  108. if (*ver >= 0x20 && *ver < 0x25) {
  109. if (perf[0] != 0xff && freq <= ROM16(perf[11]) * 1000)
  110. break;
  111. } else
  112. if (*ver >= 0x25 && *ver < 0x40) {
  113. if (perf[0] != 0xff && freq <= ROM16(perf[12]) * 1000)
  114. break;
  115. }
  116. }
  117. if (perf) {
  118. u8 *ramcfg = perf + *hdr;
  119. *ver = 0x00;
  120. *hdr = 0;
  121. return ramcfg;
  122. }
  123. return NULL;
  124. }
  125. u8 *
  126. nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
  127. {
  128. struct nouveau_device *device = nouveau_dev(dev);
  129. struct nouveau_drm *drm = nouveau_drm(dev);
  130. struct nvbios *bios = &drm->vbios;
  131. u8 strap, hdr, cnt;
  132. u8 *rammap;
  133. strap = (nv_rd32(device, 0x101000) & 0x0000003c) >> 2;
  134. if (bios->ram_restrict_tbl_ptr)
  135. strap = bios->data[bios->ram_restrict_tbl_ptr + strap];
  136. rammap = nouveau_perf_rammap(dev, freq, ver, &hdr, &cnt, len);
  137. if (rammap && strap < cnt)
  138. return rammap + hdr + (strap * *len);
  139. return NULL;
  140. }
  141. u8 *
  142. nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
  143. {
  144. struct nouveau_drm *drm = nouveau_drm(dev);
  145. struct nvbios *bios = &drm->vbios;
  146. struct bit_entry P;
  147. u8 *perf, *timing = NULL;
  148. u8 i = 0, hdr, cnt;
  149. if (bios->type == NVBIOS_BMP) {
  150. while ((perf = nouveau_perf_entry(dev, i++, ver, &hdr, &cnt,
  151. len)) && *ver == 0x15) {
  152. if (freq <= ROM32(perf[5]) * 20) {
  153. *ver = 0x00;
  154. *len = 14;
  155. return perf + 41;
  156. }
  157. }
  158. return NULL;
  159. }
  160. if (!bit_table(dev, 'P', &P)) {
  161. if (P.version == 1)
  162. timing = ROMPTR(dev, P.data[4]);
  163. else
  164. if (P.version == 2)
  165. timing = ROMPTR(dev, P.data[8]);
  166. }
  167. if (timing && timing[0] == 0x10) {
  168. u8 *ramcfg = nouveau_perf_ramcfg(dev, freq, ver, len);
  169. if (ramcfg && ramcfg[1] < timing[2]) {
  170. *ver = timing[0];
  171. *len = timing[3];
  172. return timing + timing[1] + (ramcfg[1] * timing[3]);
  173. }
  174. }
  175. return NULL;
  176. }
  177. static void
  178. legacy_perf_init(struct drm_device *dev)
  179. {
  180. struct nouveau_device *device = nouveau_dev(dev);
  181. struct nouveau_drm *drm = nouveau_drm(dev);
  182. struct nvbios *bios = &drm->vbios;
  183. struct nouveau_pm *pm = nouveau_pm(dev);
  184. char *perf, *entry, *bmp = &bios->data[bios->offset];
  185. int headerlen, use_straps;
  186. if (bmp[5] < 0x5 || bmp[6] < 0x14) {
  187. NV_DEBUG(drm, "BMP version too old for perf\n");
  188. return;
  189. }
  190. perf = ROMPTR(dev, bmp[0x73]);
  191. if (!perf) {
  192. NV_DEBUG(drm, "No memclock table pointer found.\n");
  193. return;
  194. }
  195. switch (perf[0]) {
  196. case 0x12:
  197. case 0x14:
  198. case 0x18:
  199. use_straps = 0;
  200. headerlen = 1;
  201. break;
  202. case 0x01:
  203. use_straps = perf[1] & 1;
  204. headerlen = (use_straps ? 8 : 2);
  205. break;
  206. default:
  207. NV_WARN(drm, "Unknown memclock table version %x.\n", perf[0]);
  208. return;
  209. }
  210. entry = perf + headerlen;
  211. if (use_straps)
  212. entry += (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
  213. sprintf(pm->perflvl[0].name, "performance_level_0");
  214. pm->perflvl[0].memory = ROM16(entry[0]) * 20;
  215. pm->nr_perflvl = 1;
  216. }
  217. static void
  218. nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
  219. {
  220. struct nouveau_drm *drm = nouveau_drm(dev);
  221. struct bit_entry P;
  222. u8 *vmap;
  223. int id;
  224. id = perflvl->volt_min;
  225. perflvl->volt_min = 0;
  226. /* boards using voltage table version <0x40 store the voltage
  227. * level directly in the perflvl entry as a multiple of 10mV
  228. */
  229. if (drm->pm->voltage.version < 0x40) {
  230. perflvl->volt_min = id * 10000;
  231. perflvl->volt_max = perflvl->volt_min;
  232. return;
  233. }
  234. /* on newer ones, the perflvl stores an index into yet another
  235. * vbios table containing a min/max voltage value for the perflvl
  236. */
  237. if (bit_table(dev, 'P', &P) || P.version != 2 || P.length < 34) {
  238. NV_DEBUG(drm, "where's our volt map table ptr? %d %d\n",
  239. P.version, P.length);
  240. return;
  241. }
  242. vmap = ROMPTR(dev, P.data[32]);
  243. if (!vmap) {
  244. NV_DEBUG(drm, "volt map table pointer invalid\n");
  245. return;
  246. }
  247. if (id < vmap[3]) {
  248. vmap += vmap[1] + (vmap[2] * id);
  249. perflvl->volt_min = ROM32(vmap[0]);
  250. perflvl->volt_max = ROM32(vmap[4]);
  251. }
  252. }
  253. void
  254. nouveau_perf_init(struct drm_device *dev)
  255. {
  256. struct nouveau_drm *drm = nouveau_drm(dev);
  257. struct nouveau_pm *pm = nouveau_pm(dev);
  258. struct nvbios *bios = &drm->vbios;
  259. u8 *perf, ver, hdr, cnt, len;
  260. int ret, vid, i = -1;
  261. if (bios->type == NVBIOS_BMP && bios->data[bios->offset + 6] < 0x25) {
  262. legacy_perf_init(dev);
  263. return;
  264. }
  265. perf = nouveau_perf_table(dev, &ver);
  266. while ((perf = nouveau_perf_entry(dev, ++i, &ver, &hdr, &cnt, &len))) {
  267. struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
  268. if (perf[0] == 0xff)
  269. continue;
  270. switch (ver) {
  271. case 0x12:
  272. case 0x13:
  273. case 0x15:
  274. perflvl->fanspeed = perf[55];
  275. if (hdr > 56)
  276. perflvl->volt_min = perf[56];
  277. perflvl->core = ROM32(perf[1]) * 10;
  278. perflvl->memory = ROM32(perf[5]) * 20;
  279. break;
  280. case 0x21:
  281. case 0x23:
  282. case 0x24:
  283. perflvl->fanspeed = perf[4];
  284. perflvl->volt_min = perf[5];
  285. perflvl->shader = ROM16(perf[6]) * 1000;
  286. perflvl->core = perflvl->shader;
  287. perflvl->core += (signed char)perf[8] * 1000;
  288. if (nv_device(drm->device)->chipset == 0x49 ||
  289. nv_device(drm->device)->chipset == 0x4b)
  290. perflvl->memory = ROM16(perf[11]) * 1000;
  291. else
  292. perflvl->memory = ROM16(perf[11]) * 2000;
  293. break;
  294. case 0x25:
  295. perflvl->fanspeed = perf[4];
  296. perflvl->volt_min = perf[5];
  297. perflvl->core = ROM16(perf[6]) * 1000;
  298. perflvl->shader = ROM16(perf[10]) * 1000;
  299. perflvl->memory = ROM16(perf[12]) * 1000;
  300. break;
  301. case 0x30:
  302. perflvl->memscript = ROM16(perf[2]);
  303. case 0x35:
  304. perflvl->fanspeed = perf[6];
  305. perflvl->volt_min = perf[7];
  306. perflvl->core = ROM16(perf[8]) * 1000;
  307. perflvl->shader = ROM16(perf[10]) * 1000;
  308. perflvl->memory = ROM16(perf[12]) * 1000;
  309. perflvl->vdec = ROM16(perf[16]) * 1000;
  310. perflvl->dom6 = ROM16(perf[20]) * 1000;
  311. break;
  312. case 0x40:
  313. #define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000)
  314. perflvl->fanspeed = 0; /*XXX*/
  315. perflvl->volt_min = perf[2];
  316. if (nv_device(drm->device)->card_type == NV_50) {
  317. perflvl->core = subent(0);
  318. perflvl->shader = subent(1);
  319. perflvl->memory = subent(2);
  320. perflvl->vdec = subent(3);
  321. perflvl->unka0 = subent(4);
  322. } else {
  323. perflvl->hub06 = subent(0);
  324. perflvl->hub01 = subent(1);
  325. perflvl->copy = subent(2);
  326. perflvl->shader = subent(3);
  327. perflvl->rop = subent(4);
  328. perflvl->memory = subent(5);
  329. perflvl->vdec = subent(6);
  330. perflvl->daemon = subent(10);
  331. perflvl->hub07 = subent(11);
  332. perflvl->core = perflvl->shader / 2;
  333. }
  334. break;
  335. }
  336. /* make sure vid is valid */
  337. nouveau_perf_voltage(dev, perflvl);
  338. if (pm->voltage.supported && perflvl->volt_min) {
  339. vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
  340. if (vid < 0) {
  341. NV_DEBUG(drm, "perflvl %d, bad vid\n", i);
  342. continue;
  343. }
  344. }
  345. /* get the corresponding memory timings */
  346. ret = nouveau_mem_timing_calc(dev, perflvl->memory,
  347. &perflvl->timing);
  348. if (ret) {
  349. NV_DEBUG(drm, "perflvl %d, bad timing: %d\n", i, ret);
  350. continue;
  351. }
  352. snprintf(perflvl->name, sizeof(perflvl->name),
  353. "performance_level_%d", i);
  354. perflvl->id = i;
  355. snprintf(perflvl->profile.name, sizeof(perflvl->profile.name),
  356. "%d", perflvl->id);
  357. perflvl->profile.func = &nouveau_pm_static_profile_func;
  358. list_add_tail(&perflvl->profile.head, &pm->profiles);
  359. pm->nr_perflvl++;
  360. }
  361. }
  362. void
  363. nouveau_perf_fini(struct drm_device *dev)
  364. {
  365. }