intel_sdvo.c 86 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856
  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base.base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return container_of(intel_attached_encoder(connector),
  179. struct intel_sdvo, base);
  180. }
  181. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  182. {
  183. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  184. }
  185. static bool
  186. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  187. static bool
  188. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  189. struct intel_sdvo_connector *intel_sdvo_connector,
  190. int type);
  191. static bool
  192. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  193. struct intel_sdvo_connector *intel_sdvo_connector);
  194. /**
  195. * Writes the SDVOB or SDVOC with the given value, but always writes both
  196. * SDVOB and SDVOC to work around apparent hardware issues (according to
  197. * comments in the BIOS).
  198. */
  199. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  200. {
  201. struct drm_device *dev = intel_sdvo->base.base.dev;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 bval = val, cval = val;
  204. int i;
  205. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  206. I915_WRITE(intel_sdvo->sdvo_reg, val);
  207. I915_READ(intel_sdvo->sdvo_reg);
  208. return;
  209. }
  210. if (intel_sdvo->sdvo_reg == SDVOB) {
  211. cval = I915_READ(SDVOC);
  212. } else {
  213. bval = I915_READ(SDVOB);
  214. }
  215. /*
  216. * Write the registers twice for luck. Sometimes,
  217. * writing them only once doesn't appear to 'stick'.
  218. * The BIOS does this too. Yay, magic
  219. */
  220. for (i = 0; i < 2; i++)
  221. {
  222. I915_WRITE(SDVOB, bval);
  223. I915_READ(SDVOB);
  224. I915_WRITE(SDVOC, cval);
  225. I915_READ(SDVOC);
  226. }
  227. }
  228. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  229. {
  230. struct i2c_msg msgs[] = {
  231. {
  232. .addr = intel_sdvo->slave_addr,
  233. .flags = 0,
  234. .len = 1,
  235. .buf = &addr,
  236. },
  237. {
  238. .addr = intel_sdvo->slave_addr,
  239. .flags = I2C_M_RD,
  240. .len = 1,
  241. .buf = ch,
  242. }
  243. };
  244. int ret;
  245. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  246. return true;
  247. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  248. return false;
  249. }
  250. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  251. /** Mapping of command numbers to names, for debug output */
  252. static const struct _sdvo_cmd_name {
  253. u8 cmd;
  254. const char *name;
  255. } sdvo_cmd_names[] = {
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  299. /* Add the op code for SDVO enhancements */
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  344. /* HDMI op code */
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  364. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  365. };
  366. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  367. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  368. const void *args, int args_len)
  369. {
  370. int i;
  371. DRM_DEBUG_KMS("%s: W: %02X ",
  372. SDVO_NAME(intel_sdvo), cmd);
  373. for (i = 0; i < args_len; i++)
  374. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  375. for (; i < 8; i++)
  376. DRM_LOG_KMS(" ");
  377. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  378. if (cmd == sdvo_cmd_names[i].cmd) {
  379. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  380. break;
  381. }
  382. }
  383. if (i == ARRAY_SIZE(sdvo_cmd_names))
  384. DRM_LOG_KMS("(%02X)", cmd);
  385. DRM_LOG_KMS("\n");
  386. }
  387. static const char *cmd_status_names[] = {
  388. "Power on",
  389. "Success",
  390. "Not supported",
  391. "Invalid arg",
  392. "Pending",
  393. "Target not specified",
  394. "Scaling not supported"
  395. };
  396. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  397. const void *args, int args_len)
  398. {
  399. u8 *buf, status;
  400. struct i2c_msg *msgs;
  401. int i, ret = true;
  402. /* Would be simpler to allocate both in one go ? */
  403. buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
  404. if (!buf)
  405. return false;
  406. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  407. if (!msgs) {
  408. kfree(buf);
  409. return false;
  410. }
  411. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  412. for (i = 0; i < args_len; i++) {
  413. msgs[i].addr = intel_sdvo->slave_addr;
  414. msgs[i].flags = 0;
  415. msgs[i].len = 2;
  416. msgs[i].buf = buf + 2 *i;
  417. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  418. buf[2*i + 1] = ((u8*)args)[i];
  419. }
  420. msgs[i].addr = intel_sdvo->slave_addr;
  421. msgs[i].flags = 0;
  422. msgs[i].len = 2;
  423. msgs[i].buf = buf + 2*i;
  424. buf[2*i + 0] = SDVO_I2C_OPCODE;
  425. buf[2*i + 1] = cmd;
  426. /* the following two are to read the response */
  427. status = SDVO_I2C_CMD_STATUS;
  428. msgs[i+1].addr = intel_sdvo->slave_addr;
  429. msgs[i+1].flags = 0;
  430. msgs[i+1].len = 1;
  431. msgs[i+1].buf = &status;
  432. msgs[i+2].addr = intel_sdvo->slave_addr;
  433. msgs[i+2].flags = I2C_M_RD;
  434. msgs[i+2].len = 1;
  435. msgs[i+2].buf = &status;
  436. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  437. if (ret < 0) {
  438. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  439. ret = false;
  440. goto out;
  441. }
  442. if (ret != i+3) {
  443. /* failure in I2C transfer */
  444. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  445. ret = false;
  446. }
  447. out:
  448. kfree(msgs);
  449. kfree(buf);
  450. return ret;
  451. }
  452. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  453. void *response, int response_len)
  454. {
  455. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  456. u8 status;
  457. int i;
  458. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  459. /*
  460. * The documentation states that all commands will be
  461. * processed within 15µs, and that we need only poll
  462. * the status byte a maximum of 3 times in order for the
  463. * command to be complete.
  464. *
  465. * Check 5 times in case the hardware failed to read the docs.
  466. *
  467. * Also beware that the first response by many devices is to
  468. * reply PENDING and stall for time. TVs are notorious for
  469. * requiring longer than specified to complete their replies.
  470. * Originally (in the DDX long ago), the delay was only ever 15ms
  471. * with an additional delay of 30ms applied for TVs added later after
  472. * many experiments. To accommodate both sets of delays, we do a
  473. * sequence of slow checks if the device is falling behind and fails
  474. * to reply within 5*15µs.
  475. */
  476. if (!intel_sdvo_read_byte(intel_sdvo,
  477. SDVO_I2C_CMD_STATUS,
  478. &status))
  479. goto log_fail;
  480. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  481. if (retry < 10)
  482. msleep(15);
  483. else
  484. udelay(15);
  485. if (!intel_sdvo_read_byte(intel_sdvo,
  486. SDVO_I2C_CMD_STATUS,
  487. &status))
  488. goto log_fail;
  489. }
  490. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  491. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  492. else
  493. DRM_LOG_KMS("(??? %d)", status);
  494. if (status != SDVO_CMD_STATUS_SUCCESS)
  495. goto log_fail;
  496. /* Read the command response */
  497. for (i = 0; i < response_len; i++) {
  498. if (!intel_sdvo_read_byte(intel_sdvo,
  499. SDVO_I2C_RETURN_0 + i,
  500. &((u8 *)response)[i]))
  501. goto log_fail;
  502. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  503. }
  504. DRM_LOG_KMS("\n");
  505. return true;
  506. log_fail:
  507. DRM_LOG_KMS("... failed\n");
  508. return false;
  509. }
  510. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  511. {
  512. if (mode->clock >= 100000)
  513. return 1;
  514. else if (mode->clock >= 50000)
  515. return 2;
  516. else
  517. return 4;
  518. }
  519. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  520. u8 ddc_bus)
  521. {
  522. /* This must be the immediately preceding write before the i2c xfer */
  523. return intel_sdvo_write_cmd(intel_sdvo,
  524. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  525. &ddc_bus, 1);
  526. }
  527. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  528. {
  529. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  530. return false;
  531. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  532. }
  533. static bool
  534. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  535. {
  536. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  537. return false;
  538. return intel_sdvo_read_response(intel_sdvo, value, len);
  539. }
  540. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  541. {
  542. struct intel_sdvo_set_target_input_args targets = {0};
  543. return intel_sdvo_set_value(intel_sdvo,
  544. SDVO_CMD_SET_TARGET_INPUT,
  545. &targets, sizeof(targets));
  546. }
  547. /**
  548. * Return whether each input is trained.
  549. *
  550. * This function is making an assumption about the layout of the response,
  551. * which should be checked against the docs.
  552. */
  553. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  554. {
  555. struct intel_sdvo_get_trained_inputs_response response;
  556. BUILD_BUG_ON(sizeof(response) != 1);
  557. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  558. &response, sizeof(response)))
  559. return false;
  560. *input_1 = response.input0_trained;
  561. *input_2 = response.input1_trained;
  562. return true;
  563. }
  564. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  565. u16 outputs)
  566. {
  567. return intel_sdvo_set_value(intel_sdvo,
  568. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  569. &outputs, sizeof(outputs));
  570. }
  571. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  572. u16 *outputs)
  573. {
  574. return intel_sdvo_get_value(intel_sdvo,
  575. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  576. outputs, sizeof(*outputs));
  577. }
  578. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  579. int mode)
  580. {
  581. u8 state = SDVO_ENCODER_STATE_ON;
  582. switch (mode) {
  583. case DRM_MODE_DPMS_ON:
  584. state = SDVO_ENCODER_STATE_ON;
  585. break;
  586. case DRM_MODE_DPMS_STANDBY:
  587. state = SDVO_ENCODER_STATE_STANDBY;
  588. break;
  589. case DRM_MODE_DPMS_SUSPEND:
  590. state = SDVO_ENCODER_STATE_SUSPEND;
  591. break;
  592. case DRM_MODE_DPMS_OFF:
  593. state = SDVO_ENCODER_STATE_OFF;
  594. break;
  595. }
  596. return intel_sdvo_set_value(intel_sdvo,
  597. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  598. }
  599. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  600. int *clock_min,
  601. int *clock_max)
  602. {
  603. struct intel_sdvo_pixel_clock_range clocks;
  604. BUILD_BUG_ON(sizeof(clocks) != 4);
  605. if (!intel_sdvo_get_value(intel_sdvo,
  606. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  607. &clocks, sizeof(clocks)))
  608. return false;
  609. /* Convert the values from units of 10 kHz to kHz. */
  610. *clock_min = clocks.min * 10;
  611. *clock_max = clocks.max * 10;
  612. return true;
  613. }
  614. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  615. u16 outputs)
  616. {
  617. return intel_sdvo_set_value(intel_sdvo,
  618. SDVO_CMD_SET_TARGET_OUTPUT,
  619. &outputs, sizeof(outputs));
  620. }
  621. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  622. struct intel_sdvo_dtd *dtd)
  623. {
  624. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  625. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  626. }
  627. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  628. struct intel_sdvo_dtd *dtd)
  629. {
  630. return intel_sdvo_set_timing(intel_sdvo,
  631. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  632. }
  633. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  634. struct intel_sdvo_dtd *dtd)
  635. {
  636. return intel_sdvo_set_timing(intel_sdvo,
  637. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  638. }
  639. static bool
  640. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  641. uint16_t clock,
  642. uint16_t width,
  643. uint16_t height)
  644. {
  645. struct intel_sdvo_preferred_input_timing_args args;
  646. memset(&args, 0, sizeof(args));
  647. args.clock = clock;
  648. args.width = width;
  649. args.height = height;
  650. args.interlace = 0;
  651. if (intel_sdvo->is_lvds &&
  652. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  653. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  654. args.scaled = 1;
  655. return intel_sdvo_set_value(intel_sdvo,
  656. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  657. &args, sizeof(args));
  658. }
  659. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  660. struct intel_sdvo_dtd *dtd)
  661. {
  662. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  663. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  664. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  665. &dtd->part1, sizeof(dtd->part1)) &&
  666. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  667. &dtd->part2, sizeof(dtd->part2));
  668. }
  669. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  670. {
  671. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  672. }
  673. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  674. const struct drm_display_mode *mode)
  675. {
  676. uint16_t width, height;
  677. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  678. uint16_t h_sync_offset, v_sync_offset;
  679. int mode_clock;
  680. width = mode->hdisplay;
  681. height = mode->vdisplay;
  682. /* do some mode translations */
  683. h_blank_len = mode->htotal - mode->hdisplay;
  684. h_sync_len = mode->hsync_end - mode->hsync_start;
  685. v_blank_len = mode->vtotal - mode->vdisplay;
  686. v_sync_len = mode->vsync_end - mode->vsync_start;
  687. h_sync_offset = mode->hsync_start - mode->hdisplay;
  688. v_sync_offset = mode->vsync_start - mode->vdisplay;
  689. mode_clock = mode->clock;
  690. mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
  691. mode_clock /= 10;
  692. dtd->part1.clock = mode_clock;
  693. dtd->part1.h_active = width & 0xff;
  694. dtd->part1.h_blank = h_blank_len & 0xff;
  695. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  696. ((h_blank_len >> 8) & 0xf);
  697. dtd->part1.v_active = height & 0xff;
  698. dtd->part1.v_blank = v_blank_len & 0xff;
  699. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  700. ((v_blank_len >> 8) & 0xf);
  701. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  702. dtd->part2.h_sync_width = h_sync_len & 0xff;
  703. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  704. (v_sync_len & 0xf);
  705. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  706. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  707. ((v_sync_len & 0x30) >> 4);
  708. dtd->part2.dtd_flags = 0x18;
  709. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  710. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  711. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  712. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  713. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  714. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  715. dtd->part2.sdvo_flags = 0;
  716. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  717. dtd->part2.reserved = 0;
  718. }
  719. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  720. const struct intel_sdvo_dtd *dtd)
  721. {
  722. mode->hdisplay = dtd->part1.h_active;
  723. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  724. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  725. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  726. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  727. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  728. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  729. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  730. mode->vdisplay = dtd->part1.v_active;
  731. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  732. mode->vsync_start = mode->vdisplay;
  733. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  734. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  735. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  736. mode->vsync_end = mode->vsync_start +
  737. (dtd->part2.v_sync_off_width & 0xf);
  738. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  739. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  740. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  741. mode->clock = dtd->part1.clock * 10;
  742. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  743. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  744. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  745. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  746. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  747. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  748. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  749. }
  750. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  751. {
  752. struct intel_sdvo_encode encode;
  753. BUILD_BUG_ON(sizeof(encode) != 2);
  754. return intel_sdvo_get_value(intel_sdvo,
  755. SDVO_CMD_GET_SUPP_ENCODE,
  756. &encode, sizeof(encode));
  757. }
  758. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  759. uint8_t mode)
  760. {
  761. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  762. }
  763. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  764. uint8_t mode)
  765. {
  766. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  767. }
  768. #if 0
  769. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  770. {
  771. int i, j;
  772. uint8_t set_buf_index[2];
  773. uint8_t av_split;
  774. uint8_t buf_size;
  775. uint8_t buf[48];
  776. uint8_t *pos;
  777. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  778. for (i = 0; i <= av_split; i++) {
  779. set_buf_index[0] = i; set_buf_index[1] = 0;
  780. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  781. set_buf_index, 2);
  782. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  783. intel_sdvo_read_response(encoder, &buf_size, 1);
  784. pos = buf;
  785. for (j = 0; j <= buf_size; j += 8) {
  786. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  787. NULL, 0);
  788. intel_sdvo_read_response(encoder, pos, 8);
  789. pos += 8;
  790. }
  791. }
  792. }
  793. #endif
  794. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  795. unsigned if_index, uint8_t tx_rate,
  796. uint8_t *data, unsigned length)
  797. {
  798. uint8_t set_buf_index[2] = { if_index, 0 };
  799. uint8_t hbuf_size, tmp[8];
  800. int i;
  801. if (!intel_sdvo_set_value(intel_sdvo,
  802. SDVO_CMD_SET_HBUF_INDEX,
  803. set_buf_index, 2))
  804. return false;
  805. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  806. &hbuf_size, 1))
  807. return false;
  808. /* Buffer size is 0 based, hooray! */
  809. hbuf_size++;
  810. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  811. if_index, length, hbuf_size);
  812. for (i = 0; i < hbuf_size; i += 8) {
  813. memset(tmp, 0, 8);
  814. if (i < length)
  815. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  816. if (!intel_sdvo_set_value(intel_sdvo,
  817. SDVO_CMD_SET_HBUF_DATA,
  818. tmp, 8))
  819. return false;
  820. }
  821. return intel_sdvo_set_value(intel_sdvo,
  822. SDVO_CMD_SET_HBUF_TXRATE,
  823. &tx_rate, 1);
  824. }
  825. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  826. const struct drm_display_mode *adjusted_mode)
  827. {
  828. struct dip_infoframe avi_if = {
  829. .type = DIP_TYPE_AVI,
  830. .ver = DIP_VERSION_AVI,
  831. .len = DIP_LEN_AVI,
  832. };
  833. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  834. if (intel_sdvo->rgb_quant_range_selectable) {
  835. if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
  836. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  837. else
  838. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  839. }
  840. intel_dip_infoframe_csum(&avi_if);
  841. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  842. * we must not send the ecc field, either. */
  843. memcpy(sdvo_data, &avi_if, 3);
  844. sdvo_data[3] = avi_if.checksum;
  845. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  846. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  847. SDVO_HBUF_TX_VSYNC,
  848. sdvo_data, sizeof(sdvo_data));
  849. }
  850. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  851. {
  852. struct intel_sdvo_tv_format format;
  853. uint32_t format_map;
  854. format_map = 1 << intel_sdvo->tv_format_index;
  855. memset(&format, 0, sizeof(format));
  856. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  857. BUILD_BUG_ON(sizeof(format) != 6);
  858. return intel_sdvo_set_value(intel_sdvo,
  859. SDVO_CMD_SET_TV_FORMAT,
  860. &format, sizeof(format));
  861. }
  862. static bool
  863. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  864. const struct drm_display_mode *mode)
  865. {
  866. struct intel_sdvo_dtd output_dtd;
  867. if (!intel_sdvo_set_target_output(intel_sdvo,
  868. intel_sdvo->attached_output))
  869. return false;
  870. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  871. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  872. return false;
  873. return true;
  874. }
  875. /* Asks the sdvo controller for the preferred input mode given the output mode.
  876. * Unfortunately we have to set up the full output mode to do that. */
  877. static bool
  878. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  879. const struct drm_display_mode *mode,
  880. struct drm_display_mode *adjusted_mode)
  881. {
  882. struct intel_sdvo_dtd input_dtd;
  883. /* Reset the input timing to the screen. Assume always input 0. */
  884. if (!intel_sdvo_set_target_input(intel_sdvo))
  885. return false;
  886. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  887. mode->clock / 10,
  888. mode->hdisplay,
  889. mode->vdisplay))
  890. return false;
  891. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  892. &input_dtd))
  893. return false;
  894. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  895. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  896. return true;
  897. }
  898. static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  899. const struct drm_display_mode *mode,
  900. struct drm_display_mode *adjusted_mode)
  901. {
  902. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  903. int multiplier;
  904. /* We need to construct preferred input timings based on our
  905. * output timings. To do that, we have to set the output
  906. * timings, even though this isn't really the right place in
  907. * the sequence to do it. Oh well.
  908. */
  909. if (intel_sdvo->is_tv) {
  910. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  911. return false;
  912. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  913. mode,
  914. adjusted_mode);
  915. } else if (intel_sdvo->is_lvds) {
  916. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  917. intel_sdvo->sdvo_lvds_fixed_mode))
  918. return false;
  919. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  920. mode,
  921. adjusted_mode);
  922. }
  923. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  924. * SDVO device will factor out the multiplier during mode_set.
  925. */
  926. multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
  927. intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  928. if (intel_sdvo->color_range_auto) {
  929. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  930. if (intel_sdvo->has_hdmi_monitor &&
  931. drm_match_cea_mode(adjusted_mode) > 1)
  932. intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  933. else
  934. intel_sdvo->color_range = 0;
  935. }
  936. if (intel_sdvo->color_range)
  937. adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
  938. return true;
  939. }
  940. static void intel_sdvo_mode_set(struct drm_encoder *encoder,
  941. struct drm_display_mode *mode,
  942. struct drm_display_mode *adjusted_mode)
  943. {
  944. struct drm_device *dev = encoder->dev;
  945. struct drm_i915_private *dev_priv = dev->dev_private;
  946. struct drm_crtc *crtc = encoder->crtc;
  947. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  948. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  949. u32 sdvox;
  950. struct intel_sdvo_in_out_map in_out;
  951. struct intel_sdvo_dtd input_dtd, output_dtd;
  952. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  953. int rate;
  954. if (!mode)
  955. return;
  956. /* First, set the input mapping for the first input to our controlled
  957. * output. This is only correct if we're a single-input device, in
  958. * which case the first input is the output from the appropriate SDVO
  959. * channel on the motherboard. In a two-input device, the first input
  960. * will be SDVOB and the second SDVOC.
  961. */
  962. in_out.in0 = intel_sdvo->attached_output;
  963. in_out.in1 = 0;
  964. intel_sdvo_set_value(intel_sdvo,
  965. SDVO_CMD_SET_IN_OUT_MAP,
  966. &in_out, sizeof(in_out));
  967. /* Set the output timings to the screen */
  968. if (!intel_sdvo_set_target_output(intel_sdvo,
  969. intel_sdvo->attached_output))
  970. return;
  971. /* lvds has a special fixed output timing. */
  972. if (intel_sdvo->is_lvds)
  973. intel_sdvo_get_dtd_from_mode(&output_dtd,
  974. intel_sdvo->sdvo_lvds_fixed_mode);
  975. else
  976. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  977. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  978. DRM_INFO("Setting output timings on %s failed\n",
  979. SDVO_NAME(intel_sdvo));
  980. /* Set the input timing to the screen. Assume always input 0. */
  981. if (!intel_sdvo_set_target_input(intel_sdvo))
  982. return;
  983. if (intel_sdvo->has_hdmi_monitor) {
  984. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  985. intel_sdvo_set_colorimetry(intel_sdvo,
  986. SDVO_COLORIMETRY_RGB256);
  987. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  988. } else
  989. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  990. if (intel_sdvo->is_tv &&
  991. !intel_sdvo_set_tv_format(intel_sdvo))
  992. return;
  993. /* We have tried to get input timing in mode_fixup, and filled into
  994. * adjusted_mode.
  995. */
  996. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  997. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  998. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  999. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1000. DRM_INFO("Setting input timings on %s failed\n",
  1001. SDVO_NAME(intel_sdvo));
  1002. switch (pixel_multiplier) {
  1003. default:
  1004. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1005. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1006. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1007. }
  1008. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1009. return;
  1010. /* Set the SDVO control regs. */
  1011. if (INTEL_INFO(dev)->gen >= 4) {
  1012. /* The real mode polarity is set by the SDVO commands, using
  1013. * struct intel_sdvo_dtd. */
  1014. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1015. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1016. sdvox |= intel_sdvo->color_range;
  1017. if (INTEL_INFO(dev)->gen < 5)
  1018. sdvox |= SDVO_BORDER_ENABLE;
  1019. } else {
  1020. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1021. switch (intel_sdvo->sdvo_reg) {
  1022. case SDVOB:
  1023. sdvox &= SDVOB_PRESERVE_MASK;
  1024. break;
  1025. case SDVOC:
  1026. sdvox &= SDVOC_PRESERVE_MASK;
  1027. break;
  1028. }
  1029. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1030. }
  1031. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1032. sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
  1033. else
  1034. sdvox |= TRANSCODER(intel_crtc->pipe);
  1035. if (intel_sdvo->has_hdmi_audio)
  1036. sdvox |= SDVO_AUDIO_ENABLE;
  1037. if (INTEL_INFO(dev)->gen >= 4) {
  1038. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1039. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1040. /* done in crtc_mode_set as it lives inside the dpll register */
  1041. } else {
  1042. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  1043. }
  1044. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1045. INTEL_INFO(dev)->gen < 5)
  1046. sdvox |= SDVO_STALL_SELECT;
  1047. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1048. }
  1049. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1050. {
  1051. struct intel_sdvo_connector *intel_sdvo_connector =
  1052. to_intel_sdvo_connector(&connector->base);
  1053. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1054. u16 active_outputs;
  1055. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1056. if (active_outputs & intel_sdvo_connector->output_flag)
  1057. return true;
  1058. else
  1059. return false;
  1060. }
  1061. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1062. enum pipe *pipe)
  1063. {
  1064. struct drm_device *dev = encoder->base.dev;
  1065. struct drm_i915_private *dev_priv = dev->dev_private;
  1066. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1067. u32 tmp;
  1068. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1069. if (!(tmp & SDVO_ENABLE))
  1070. return false;
  1071. if (HAS_PCH_CPT(dev))
  1072. *pipe = PORT_TO_PIPE_CPT(tmp);
  1073. else
  1074. *pipe = PORT_TO_PIPE(tmp);
  1075. return true;
  1076. }
  1077. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1078. {
  1079. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1080. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1081. u32 temp;
  1082. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1083. if (0)
  1084. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1085. DRM_MODE_DPMS_OFF);
  1086. temp = I915_READ(intel_sdvo->sdvo_reg);
  1087. if ((temp & SDVO_ENABLE) != 0) {
  1088. /* HW workaround for IBX, we need to move the port to
  1089. * transcoder A before disabling it. */
  1090. if (HAS_PCH_IBX(encoder->base.dev)) {
  1091. struct drm_crtc *crtc = encoder->base.crtc;
  1092. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1093. if (temp & SDVO_PIPE_B_SELECT) {
  1094. temp &= ~SDVO_PIPE_B_SELECT;
  1095. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1096. POSTING_READ(intel_sdvo->sdvo_reg);
  1097. /* Again we need to write this twice. */
  1098. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1099. POSTING_READ(intel_sdvo->sdvo_reg);
  1100. /* Transcoder selection bits only update
  1101. * effectively on vblank. */
  1102. if (crtc)
  1103. intel_wait_for_vblank(encoder->base.dev, pipe);
  1104. else
  1105. msleep(50);
  1106. }
  1107. }
  1108. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1109. }
  1110. }
  1111. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1112. {
  1113. struct drm_device *dev = encoder->base.dev;
  1114. struct drm_i915_private *dev_priv = dev->dev_private;
  1115. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1116. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1117. u32 temp;
  1118. bool input1, input2;
  1119. int i;
  1120. u8 status;
  1121. temp = I915_READ(intel_sdvo->sdvo_reg);
  1122. if ((temp & SDVO_ENABLE) == 0) {
  1123. /* HW workaround for IBX, we need to move the port
  1124. * to transcoder A before disabling it. */
  1125. if (HAS_PCH_IBX(dev)) {
  1126. struct drm_crtc *crtc = encoder->base.crtc;
  1127. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1128. /* Restore the transcoder select bit. */
  1129. if (pipe == PIPE_B)
  1130. temp |= SDVO_PIPE_B_SELECT;
  1131. }
  1132. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1133. }
  1134. for (i = 0; i < 2; i++)
  1135. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1136. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1137. /* Warn if the device reported failure to sync.
  1138. * A lot of SDVO devices fail to notify of sync, but it's
  1139. * a given it the status is a success, we succeeded.
  1140. */
  1141. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1142. DRM_DEBUG_KMS("First %s output reported failure to "
  1143. "sync\n", SDVO_NAME(intel_sdvo));
  1144. }
  1145. if (0)
  1146. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1147. DRM_MODE_DPMS_ON);
  1148. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1149. }
  1150. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1151. {
  1152. struct drm_crtc *crtc;
  1153. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1154. /* dvo supports only 2 dpms states. */
  1155. if (mode != DRM_MODE_DPMS_ON)
  1156. mode = DRM_MODE_DPMS_OFF;
  1157. if (mode == connector->dpms)
  1158. return;
  1159. connector->dpms = mode;
  1160. /* Only need to change hw state when actually enabled */
  1161. crtc = intel_sdvo->base.base.crtc;
  1162. if (!crtc) {
  1163. intel_sdvo->base.connectors_active = false;
  1164. return;
  1165. }
  1166. if (mode != DRM_MODE_DPMS_ON) {
  1167. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1168. if (0)
  1169. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1170. intel_sdvo->base.connectors_active = false;
  1171. intel_crtc_update_dpms(crtc);
  1172. } else {
  1173. intel_sdvo->base.connectors_active = true;
  1174. intel_crtc_update_dpms(crtc);
  1175. if (0)
  1176. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1177. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1178. }
  1179. intel_modeset_check_state(connector->dev);
  1180. }
  1181. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1182. struct drm_display_mode *mode)
  1183. {
  1184. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1185. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1186. return MODE_NO_DBLESCAN;
  1187. if (intel_sdvo->pixel_clock_min > mode->clock)
  1188. return MODE_CLOCK_LOW;
  1189. if (intel_sdvo->pixel_clock_max < mode->clock)
  1190. return MODE_CLOCK_HIGH;
  1191. if (intel_sdvo->is_lvds) {
  1192. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1193. return MODE_PANEL;
  1194. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1195. return MODE_PANEL;
  1196. }
  1197. return MODE_OK;
  1198. }
  1199. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1200. {
  1201. BUILD_BUG_ON(sizeof(*caps) != 8);
  1202. if (!intel_sdvo_get_value(intel_sdvo,
  1203. SDVO_CMD_GET_DEVICE_CAPS,
  1204. caps, sizeof(*caps)))
  1205. return false;
  1206. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1207. " vendor_id: %d\n"
  1208. " device_id: %d\n"
  1209. " device_rev_id: %d\n"
  1210. " sdvo_version_major: %d\n"
  1211. " sdvo_version_minor: %d\n"
  1212. " sdvo_inputs_mask: %d\n"
  1213. " smooth_scaling: %d\n"
  1214. " sharp_scaling: %d\n"
  1215. " up_scaling: %d\n"
  1216. " down_scaling: %d\n"
  1217. " stall_support: %d\n"
  1218. " output_flags: %d\n",
  1219. caps->vendor_id,
  1220. caps->device_id,
  1221. caps->device_rev_id,
  1222. caps->sdvo_version_major,
  1223. caps->sdvo_version_minor,
  1224. caps->sdvo_inputs_mask,
  1225. caps->smooth_scaling,
  1226. caps->sharp_scaling,
  1227. caps->up_scaling,
  1228. caps->down_scaling,
  1229. caps->stall_support,
  1230. caps->output_flags);
  1231. return true;
  1232. }
  1233. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1234. {
  1235. struct drm_device *dev = intel_sdvo->base.base.dev;
  1236. uint16_t hotplug;
  1237. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1238. * on the line. */
  1239. if (IS_I945G(dev) || IS_I945GM(dev))
  1240. return 0;
  1241. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1242. &hotplug, sizeof(hotplug)))
  1243. return 0;
  1244. return hotplug;
  1245. }
  1246. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1247. {
  1248. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1249. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1250. &intel_sdvo->hotplug_active, 2);
  1251. }
  1252. static bool
  1253. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1254. {
  1255. /* Is there more than one type of output? */
  1256. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1257. }
  1258. static struct edid *
  1259. intel_sdvo_get_edid(struct drm_connector *connector)
  1260. {
  1261. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1262. return drm_get_edid(connector, &sdvo->ddc);
  1263. }
  1264. /* Mac mini hack -- use the same DDC as the analog connector */
  1265. static struct edid *
  1266. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1267. {
  1268. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1269. return drm_get_edid(connector,
  1270. intel_gmbus_get_adapter(dev_priv,
  1271. dev_priv->crt_ddc_pin));
  1272. }
  1273. static enum drm_connector_status
  1274. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1275. {
  1276. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1277. enum drm_connector_status status;
  1278. struct edid *edid;
  1279. edid = intel_sdvo_get_edid(connector);
  1280. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1281. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1282. /*
  1283. * Don't use the 1 as the argument of DDC bus switch to get
  1284. * the EDID. It is used for SDVO SPD ROM.
  1285. */
  1286. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1287. intel_sdvo->ddc_bus = ddc;
  1288. edid = intel_sdvo_get_edid(connector);
  1289. if (edid)
  1290. break;
  1291. }
  1292. /*
  1293. * If we found the EDID on the other bus,
  1294. * assume that is the correct DDC bus.
  1295. */
  1296. if (edid == NULL)
  1297. intel_sdvo->ddc_bus = saved_ddc;
  1298. }
  1299. /*
  1300. * When there is no edid and no monitor is connected with VGA
  1301. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1302. */
  1303. if (edid == NULL)
  1304. edid = intel_sdvo_get_analog_edid(connector);
  1305. status = connector_status_unknown;
  1306. if (edid != NULL) {
  1307. /* DDC bus is shared, match EDID to connector type */
  1308. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1309. status = connector_status_connected;
  1310. if (intel_sdvo->is_hdmi) {
  1311. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1312. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1313. intel_sdvo->rgb_quant_range_selectable =
  1314. drm_rgb_quant_range_selectable(edid);
  1315. }
  1316. } else
  1317. status = connector_status_disconnected;
  1318. kfree(edid);
  1319. }
  1320. if (status == connector_status_connected) {
  1321. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1322. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1323. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1324. }
  1325. return status;
  1326. }
  1327. static bool
  1328. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1329. struct edid *edid)
  1330. {
  1331. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1332. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1333. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1334. connector_is_digital, monitor_is_digital);
  1335. return connector_is_digital == monitor_is_digital;
  1336. }
  1337. static enum drm_connector_status
  1338. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1339. {
  1340. uint16_t response;
  1341. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1342. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1343. enum drm_connector_status ret;
  1344. if (!intel_sdvo_get_value(intel_sdvo,
  1345. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1346. &response, 2))
  1347. return connector_status_unknown;
  1348. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1349. response & 0xff, response >> 8,
  1350. intel_sdvo_connector->output_flag);
  1351. if (response == 0)
  1352. return connector_status_disconnected;
  1353. intel_sdvo->attached_output = response;
  1354. intel_sdvo->has_hdmi_monitor = false;
  1355. intel_sdvo->has_hdmi_audio = false;
  1356. intel_sdvo->rgb_quant_range_selectable = false;
  1357. if ((intel_sdvo_connector->output_flag & response) == 0)
  1358. ret = connector_status_disconnected;
  1359. else if (IS_TMDS(intel_sdvo_connector))
  1360. ret = intel_sdvo_tmds_sink_detect(connector);
  1361. else {
  1362. struct edid *edid;
  1363. /* if we have an edid check it matches the connection */
  1364. edid = intel_sdvo_get_edid(connector);
  1365. if (edid == NULL)
  1366. edid = intel_sdvo_get_analog_edid(connector);
  1367. if (edid != NULL) {
  1368. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1369. edid))
  1370. ret = connector_status_connected;
  1371. else
  1372. ret = connector_status_disconnected;
  1373. kfree(edid);
  1374. } else
  1375. ret = connector_status_connected;
  1376. }
  1377. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1378. if (ret == connector_status_connected) {
  1379. intel_sdvo->is_tv = false;
  1380. intel_sdvo->is_lvds = false;
  1381. intel_sdvo->base.needs_tv_clock = false;
  1382. if (response & SDVO_TV_MASK) {
  1383. intel_sdvo->is_tv = true;
  1384. intel_sdvo->base.needs_tv_clock = true;
  1385. }
  1386. if (response & SDVO_LVDS_MASK)
  1387. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1388. }
  1389. return ret;
  1390. }
  1391. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1392. {
  1393. struct edid *edid;
  1394. /* set the bus switch and get the modes */
  1395. edid = intel_sdvo_get_edid(connector);
  1396. /*
  1397. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1398. * link between analog and digital outputs. So, if the regular SDVO
  1399. * DDC fails, check to see if the analog output is disconnected, in
  1400. * which case we'll look there for the digital DDC data.
  1401. */
  1402. if (edid == NULL)
  1403. edid = intel_sdvo_get_analog_edid(connector);
  1404. if (edid != NULL) {
  1405. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1406. edid)) {
  1407. drm_mode_connector_update_edid_property(connector, edid);
  1408. drm_add_edid_modes(connector, edid);
  1409. }
  1410. kfree(edid);
  1411. }
  1412. }
  1413. /*
  1414. * Set of SDVO TV modes.
  1415. * Note! This is in reply order (see loop in get_tv_modes).
  1416. * XXX: all 60Hz refresh?
  1417. */
  1418. static const struct drm_display_mode sdvo_tv_modes[] = {
  1419. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1420. 416, 0, 200, 201, 232, 233, 0,
  1421. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1422. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1423. 416, 0, 240, 241, 272, 273, 0,
  1424. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1425. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1426. 496, 0, 300, 301, 332, 333, 0,
  1427. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1428. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1429. 736, 0, 350, 351, 382, 383, 0,
  1430. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1431. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1432. 736, 0, 400, 401, 432, 433, 0,
  1433. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1434. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1435. 736, 0, 480, 481, 512, 513, 0,
  1436. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1437. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1438. 800, 0, 480, 481, 512, 513, 0,
  1439. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1440. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1441. 800, 0, 576, 577, 608, 609, 0,
  1442. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1443. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1444. 816, 0, 350, 351, 382, 383, 0,
  1445. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1446. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1447. 816, 0, 400, 401, 432, 433, 0,
  1448. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1449. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1450. 816, 0, 480, 481, 512, 513, 0,
  1451. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1452. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1453. 816, 0, 540, 541, 572, 573, 0,
  1454. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1455. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1456. 816, 0, 576, 577, 608, 609, 0,
  1457. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1458. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1459. 864, 0, 576, 577, 608, 609, 0,
  1460. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1461. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1462. 896, 0, 600, 601, 632, 633, 0,
  1463. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1464. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1465. 928, 0, 624, 625, 656, 657, 0,
  1466. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1467. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1468. 1016, 0, 766, 767, 798, 799, 0,
  1469. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1470. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1471. 1120, 0, 768, 769, 800, 801, 0,
  1472. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1473. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1474. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1475. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1476. };
  1477. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1478. {
  1479. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1480. struct intel_sdvo_sdtv_resolution_request tv_res;
  1481. uint32_t reply = 0, format_map = 0;
  1482. int i;
  1483. /* Read the list of supported input resolutions for the selected TV
  1484. * format.
  1485. */
  1486. format_map = 1 << intel_sdvo->tv_format_index;
  1487. memcpy(&tv_res, &format_map,
  1488. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1489. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1490. return;
  1491. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1492. if (!intel_sdvo_write_cmd(intel_sdvo,
  1493. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1494. &tv_res, sizeof(tv_res)))
  1495. return;
  1496. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1497. return;
  1498. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1499. if (reply & (1 << i)) {
  1500. struct drm_display_mode *nmode;
  1501. nmode = drm_mode_duplicate(connector->dev,
  1502. &sdvo_tv_modes[i]);
  1503. if (nmode)
  1504. drm_mode_probed_add(connector, nmode);
  1505. }
  1506. }
  1507. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1508. {
  1509. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1510. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1511. struct drm_display_mode *newmode;
  1512. /*
  1513. * Attempt to get the mode list from DDC.
  1514. * Assume that the preferred modes are
  1515. * arranged in priority order.
  1516. */
  1517. intel_ddc_get_modes(connector, intel_sdvo->i2c);
  1518. if (list_empty(&connector->probed_modes) == false)
  1519. goto end;
  1520. /* Fetch modes from VBT */
  1521. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1522. newmode = drm_mode_duplicate(connector->dev,
  1523. dev_priv->sdvo_lvds_vbt_mode);
  1524. if (newmode != NULL) {
  1525. /* Guarantee the mode is preferred */
  1526. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1527. DRM_MODE_TYPE_DRIVER);
  1528. drm_mode_probed_add(connector, newmode);
  1529. }
  1530. }
  1531. end:
  1532. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1533. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1534. intel_sdvo->sdvo_lvds_fixed_mode =
  1535. drm_mode_duplicate(connector->dev, newmode);
  1536. intel_sdvo->is_lvds = true;
  1537. break;
  1538. }
  1539. }
  1540. }
  1541. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1542. {
  1543. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1544. if (IS_TV(intel_sdvo_connector))
  1545. intel_sdvo_get_tv_modes(connector);
  1546. else if (IS_LVDS(intel_sdvo_connector))
  1547. intel_sdvo_get_lvds_modes(connector);
  1548. else
  1549. intel_sdvo_get_ddc_modes(connector);
  1550. return !list_empty(&connector->probed_modes);
  1551. }
  1552. static void
  1553. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1554. {
  1555. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1556. struct drm_device *dev = connector->dev;
  1557. if (intel_sdvo_connector->left)
  1558. drm_property_destroy(dev, intel_sdvo_connector->left);
  1559. if (intel_sdvo_connector->right)
  1560. drm_property_destroy(dev, intel_sdvo_connector->right);
  1561. if (intel_sdvo_connector->top)
  1562. drm_property_destroy(dev, intel_sdvo_connector->top);
  1563. if (intel_sdvo_connector->bottom)
  1564. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1565. if (intel_sdvo_connector->hpos)
  1566. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1567. if (intel_sdvo_connector->vpos)
  1568. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1569. if (intel_sdvo_connector->saturation)
  1570. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1571. if (intel_sdvo_connector->contrast)
  1572. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1573. if (intel_sdvo_connector->hue)
  1574. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1575. if (intel_sdvo_connector->sharpness)
  1576. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1577. if (intel_sdvo_connector->flicker_filter)
  1578. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1579. if (intel_sdvo_connector->flicker_filter_2d)
  1580. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1581. if (intel_sdvo_connector->flicker_filter_adaptive)
  1582. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1583. if (intel_sdvo_connector->tv_luma_filter)
  1584. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1585. if (intel_sdvo_connector->tv_chroma_filter)
  1586. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1587. if (intel_sdvo_connector->dot_crawl)
  1588. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1589. if (intel_sdvo_connector->brightness)
  1590. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1591. }
  1592. static void intel_sdvo_destroy(struct drm_connector *connector)
  1593. {
  1594. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1595. if (intel_sdvo_connector->tv_format)
  1596. drm_property_destroy(connector->dev,
  1597. intel_sdvo_connector->tv_format);
  1598. intel_sdvo_destroy_enhance_property(connector);
  1599. drm_sysfs_connector_remove(connector);
  1600. drm_connector_cleanup(connector);
  1601. kfree(intel_sdvo_connector);
  1602. }
  1603. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1604. {
  1605. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1606. struct edid *edid;
  1607. bool has_audio = false;
  1608. if (!intel_sdvo->is_hdmi)
  1609. return false;
  1610. edid = intel_sdvo_get_edid(connector);
  1611. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1612. has_audio = drm_detect_monitor_audio(edid);
  1613. kfree(edid);
  1614. return has_audio;
  1615. }
  1616. static int
  1617. intel_sdvo_set_property(struct drm_connector *connector,
  1618. struct drm_property *property,
  1619. uint64_t val)
  1620. {
  1621. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1622. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1623. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1624. uint16_t temp_value;
  1625. uint8_t cmd;
  1626. int ret;
  1627. ret = drm_object_property_set_value(&connector->base, property, val);
  1628. if (ret)
  1629. return ret;
  1630. if (property == dev_priv->force_audio_property) {
  1631. int i = val;
  1632. bool has_audio;
  1633. if (i == intel_sdvo_connector->force_audio)
  1634. return 0;
  1635. intel_sdvo_connector->force_audio = i;
  1636. if (i == HDMI_AUDIO_AUTO)
  1637. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1638. else
  1639. has_audio = (i == HDMI_AUDIO_ON);
  1640. if (has_audio == intel_sdvo->has_hdmi_audio)
  1641. return 0;
  1642. intel_sdvo->has_hdmi_audio = has_audio;
  1643. goto done;
  1644. }
  1645. if (property == dev_priv->broadcast_rgb_property) {
  1646. switch (val) {
  1647. case INTEL_BROADCAST_RGB_AUTO:
  1648. intel_sdvo->color_range_auto = true;
  1649. break;
  1650. case INTEL_BROADCAST_RGB_FULL:
  1651. intel_sdvo->color_range_auto = false;
  1652. intel_sdvo->color_range = 0;
  1653. break;
  1654. case INTEL_BROADCAST_RGB_LIMITED:
  1655. intel_sdvo->color_range_auto = false;
  1656. intel_sdvo->color_range = SDVO_COLOR_RANGE_16_235;
  1657. break;
  1658. default:
  1659. return -EINVAL;
  1660. }
  1661. goto done;
  1662. }
  1663. #define CHECK_PROPERTY(name, NAME) \
  1664. if (intel_sdvo_connector->name == property) { \
  1665. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1666. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1667. cmd = SDVO_CMD_SET_##NAME; \
  1668. intel_sdvo_connector->cur_##name = temp_value; \
  1669. goto set_value; \
  1670. }
  1671. if (property == intel_sdvo_connector->tv_format) {
  1672. if (val >= TV_FORMAT_NUM)
  1673. return -EINVAL;
  1674. if (intel_sdvo->tv_format_index ==
  1675. intel_sdvo_connector->tv_format_supported[val])
  1676. return 0;
  1677. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1678. goto done;
  1679. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1680. temp_value = val;
  1681. if (intel_sdvo_connector->left == property) {
  1682. drm_object_property_set_value(&connector->base,
  1683. intel_sdvo_connector->right, val);
  1684. if (intel_sdvo_connector->left_margin == temp_value)
  1685. return 0;
  1686. intel_sdvo_connector->left_margin = temp_value;
  1687. intel_sdvo_connector->right_margin = temp_value;
  1688. temp_value = intel_sdvo_connector->max_hscan -
  1689. intel_sdvo_connector->left_margin;
  1690. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1691. goto set_value;
  1692. } else if (intel_sdvo_connector->right == property) {
  1693. drm_object_property_set_value(&connector->base,
  1694. intel_sdvo_connector->left, val);
  1695. if (intel_sdvo_connector->right_margin == temp_value)
  1696. return 0;
  1697. intel_sdvo_connector->left_margin = temp_value;
  1698. intel_sdvo_connector->right_margin = temp_value;
  1699. temp_value = intel_sdvo_connector->max_hscan -
  1700. intel_sdvo_connector->left_margin;
  1701. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1702. goto set_value;
  1703. } else if (intel_sdvo_connector->top == property) {
  1704. drm_object_property_set_value(&connector->base,
  1705. intel_sdvo_connector->bottom, val);
  1706. if (intel_sdvo_connector->top_margin == temp_value)
  1707. return 0;
  1708. intel_sdvo_connector->top_margin = temp_value;
  1709. intel_sdvo_connector->bottom_margin = temp_value;
  1710. temp_value = intel_sdvo_connector->max_vscan -
  1711. intel_sdvo_connector->top_margin;
  1712. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1713. goto set_value;
  1714. } else if (intel_sdvo_connector->bottom == property) {
  1715. drm_object_property_set_value(&connector->base,
  1716. intel_sdvo_connector->top, val);
  1717. if (intel_sdvo_connector->bottom_margin == temp_value)
  1718. return 0;
  1719. intel_sdvo_connector->top_margin = temp_value;
  1720. intel_sdvo_connector->bottom_margin = temp_value;
  1721. temp_value = intel_sdvo_connector->max_vscan -
  1722. intel_sdvo_connector->top_margin;
  1723. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1724. goto set_value;
  1725. }
  1726. CHECK_PROPERTY(hpos, HPOS)
  1727. CHECK_PROPERTY(vpos, VPOS)
  1728. CHECK_PROPERTY(saturation, SATURATION)
  1729. CHECK_PROPERTY(contrast, CONTRAST)
  1730. CHECK_PROPERTY(hue, HUE)
  1731. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1732. CHECK_PROPERTY(sharpness, SHARPNESS)
  1733. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1734. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1735. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1736. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1737. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1738. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1739. }
  1740. return -EINVAL; /* unknown property */
  1741. set_value:
  1742. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1743. return -EIO;
  1744. done:
  1745. if (intel_sdvo->base.base.crtc)
  1746. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1747. return 0;
  1748. #undef CHECK_PROPERTY
  1749. }
  1750. static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
  1751. .mode_fixup = intel_sdvo_mode_fixup,
  1752. .mode_set = intel_sdvo_mode_set,
  1753. };
  1754. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1755. .dpms = intel_sdvo_dpms,
  1756. .detect = intel_sdvo_detect,
  1757. .fill_modes = drm_helper_probe_single_connector_modes,
  1758. .set_property = intel_sdvo_set_property,
  1759. .destroy = intel_sdvo_destroy,
  1760. };
  1761. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1762. .get_modes = intel_sdvo_get_modes,
  1763. .mode_valid = intel_sdvo_mode_valid,
  1764. .best_encoder = intel_best_encoder,
  1765. };
  1766. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1767. {
  1768. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1769. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1770. drm_mode_destroy(encoder->dev,
  1771. intel_sdvo->sdvo_lvds_fixed_mode);
  1772. i2c_del_adapter(&intel_sdvo->ddc);
  1773. intel_encoder_destroy(encoder);
  1774. }
  1775. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1776. .destroy = intel_sdvo_enc_destroy,
  1777. };
  1778. static void
  1779. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1780. {
  1781. uint16_t mask = 0;
  1782. unsigned int num_bits;
  1783. /* Make a mask of outputs less than or equal to our own priority in the
  1784. * list.
  1785. */
  1786. switch (sdvo->controlled_output) {
  1787. case SDVO_OUTPUT_LVDS1:
  1788. mask |= SDVO_OUTPUT_LVDS1;
  1789. case SDVO_OUTPUT_LVDS0:
  1790. mask |= SDVO_OUTPUT_LVDS0;
  1791. case SDVO_OUTPUT_TMDS1:
  1792. mask |= SDVO_OUTPUT_TMDS1;
  1793. case SDVO_OUTPUT_TMDS0:
  1794. mask |= SDVO_OUTPUT_TMDS0;
  1795. case SDVO_OUTPUT_RGB1:
  1796. mask |= SDVO_OUTPUT_RGB1;
  1797. case SDVO_OUTPUT_RGB0:
  1798. mask |= SDVO_OUTPUT_RGB0;
  1799. break;
  1800. }
  1801. /* Count bits to find what number we are in the priority list. */
  1802. mask &= sdvo->caps.output_flags;
  1803. num_bits = hweight16(mask);
  1804. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1805. if (num_bits > 3)
  1806. num_bits = 3;
  1807. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1808. sdvo->ddc_bus = 1 << num_bits;
  1809. }
  1810. /**
  1811. * Choose the appropriate DDC bus for control bus switch command for this
  1812. * SDVO output based on the controlled output.
  1813. *
  1814. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1815. * outputs, then LVDS outputs.
  1816. */
  1817. static void
  1818. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1819. struct intel_sdvo *sdvo, u32 reg)
  1820. {
  1821. struct sdvo_device_mapping *mapping;
  1822. if (sdvo->is_sdvob)
  1823. mapping = &(dev_priv->sdvo_mappings[0]);
  1824. else
  1825. mapping = &(dev_priv->sdvo_mappings[1]);
  1826. if (mapping->initialized)
  1827. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1828. else
  1829. intel_sdvo_guess_ddc_bus(sdvo);
  1830. }
  1831. static void
  1832. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1833. struct intel_sdvo *sdvo, u32 reg)
  1834. {
  1835. struct sdvo_device_mapping *mapping;
  1836. u8 pin;
  1837. if (sdvo->is_sdvob)
  1838. mapping = &dev_priv->sdvo_mappings[0];
  1839. else
  1840. mapping = &dev_priv->sdvo_mappings[1];
  1841. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1842. pin = mapping->i2c_pin;
  1843. else
  1844. pin = GMBUS_PORT_DPB;
  1845. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1846. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1847. * our code totally fails once we start using gmbus. Hence fall back to
  1848. * bit banging for now. */
  1849. intel_gmbus_force_bit(sdvo->i2c, true);
  1850. }
  1851. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1852. static void
  1853. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1854. {
  1855. intel_gmbus_force_bit(sdvo->i2c, false);
  1856. }
  1857. static bool
  1858. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1859. {
  1860. return intel_sdvo_check_supp_encode(intel_sdvo);
  1861. }
  1862. static u8
  1863. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1864. {
  1865. struct drm_i915_private *dev_priv = dev->dev_private;
  1866. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1867. if (sdvo->is_sdvob) {
  1868. my_mapping = &dev_priv->sdvo_mappings[0];
  1869. other_mapping = &dev_priv->sdvo_mappings[1];
  1870. } else {
  1871. my_mapping = &dev_priv->sdvo_mappings[1];
  1872. other_mapping = &dev_priv->sdvo_mappings[0];
  1873. }
  1874. /* If the BIOS described our SDVO device, take advantage of it. */
  1875. if (my_mapping->slave_addr)
  1876. return my_mapping->slave_addr;
  1877. /* If the BIOS only described a different SDVO device, use the
  1878. * address that it isn't using.
  1879. */
  1880. if (other_mapping->slave_addr) {
  1881. if (other_mapping->slave_addr == 0x70)
  1882. return 0x72;
  1883. else
  1884. return 0x70;
  1885. }
  1886. /* No SDVO device info is found for another DVO port,
  1887. * so use mapping assumption we had before BIOS parsing.
  1888. */
  1889. if (sdvo->is_sdvob)
  1890. return 0x70;
  1891. else
  1892. return 0x72;
  1893. }
  1894. static void
  1895. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1896. struct intel_sdvo *encoder)
  1897. {
  1898. drm_connector_init(encoder->base.base.dev,
  1899. &connector->base.base,
  1900. &intel_sdvo_connector_funcs,
  1901. connector->base.base.connector_type);
  1902. drm_connector_helper_add(&connector->base.base,
  1903. &intel_sdvo_connector_helper_funcs);
  1904. connector->base.base.interlace_allowed = 1;
  1905. connector->base.base.doublescan_allowed = 0;
  1906. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1907. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  1908. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1909. drm_sysfs_connector_add(&connector->base.base);
  1910. }
  1911. static void
  1912. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  1913. struct intel_sdvo_connector *connector)
  1914. {
  1915. struct drm_device *dev = connector->base.base.dev;
  1916. intel_attach_force_audio_property(&connector->base.base);
  1917. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  1918. intel_attach_broadcast_rgb_property(&connector->base.base);
  1919. intel_sdvo->color_range_auto = true;
  1920. }
  1921. }
  1922. static bool
  1923. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1924. {
  1925. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1926. struct drm_connector *connector;
  1927. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1928. struct intel_connector *intel_connector;
  1929. struct intel_sdvo_connector *intel_sdvo_connector;
  1930. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1931. if (!intel_sdvo_connector)
  1932. return false;
  1933. if (device == 0) {
  1934. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1935. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1936. } else if (device == 1) {
  1937. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1938. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1939. }
  1940. intel_connector = &intel_sdvo_connector->base;
  1941. connector = &intel_connector->base;
  1942. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  1943. intel_sdvo_connector->output_flag) {
  1944. connector->polled = DRM_CONNECTOR_POLL_HPD;
  1945. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  1946. /* Some SDVO devices have one-shot hotplug interrupts.
  1947. * Ensure that they get re-enabled when an interrupt happens.
  1948. */
  1949. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1950. intel_sdvo_enable_hotplug(intel_encoder);
  1951. } else {
  1952. connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1953. }
  1954. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1955. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1956. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1957. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1958. intel_sdvo->is_hdmi = true;
  1959. }
  1960. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1961. if (intel_sdvo->is_hdmi)
  1962. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  1963. return true;
  1964. }
  1965. static bool
  1966. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1967. {
  1968. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1969. struct drm_connector *connector;
  1970. struct intel_connector *intel_connector;
  1971. struct intel_sdvo_connector *intel_sdvo_connector;
  1972. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1973. if (!intel_sdvo_connector)
  1974. return false;
  1975. intel_connector = &intel_sdvo_connector->base;
  1976. connector = &intel_connector->base;
  1977. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1978. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1979. intel_sdvo->controlled_output |= type;
  1980. intel_sdvo_connector->output_flag = type;
  1981. intel_sdvo->is_tv = true;
  1982. intel_sdvo->base.needs_tv_clock = true;
  1983. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1984. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1985. goto err;
  1986. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1987. goto err;
  1988. return true;
  1989. err:
  1990. intel_sdvo_destroy(connector);
  1991. return false;
  1992. }
  1993. static bool
  1994. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  1995. {
  1996. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1997. struct drm_connector *connector;
  1998. struct intel_connector *intel_connector;
  1999. struct intel_sdvo_connector *intel_sdvo_connector;
  2000. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2001. if (!intel_sdvo_connector)
  2002. return false;
  2003. intel_connector = &intel_sdvo_connector->base;
  2004. connector = &intel_connector->base;
  2005. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2006. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2007. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2008. if (device == 0) {
  2009. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2010. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2011. } else if (device == 1) {
  2012. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2013. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2014. }
  2015. intel_sdvo_connector_init(intel_sdvo_connector,
  2016. intel_sdvo);
  2017. return true;
  2018. }
  2019. static bool
  2020. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2021. {
  2022. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2023. struct drm_connector *connector;
  2024. struct intel_connector *intel_connector;
  2025. struct intel_sdvo_connector *intel_sdvo_connector;
  2026. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2027. if (!intel_sdvo_connector)
  2028. return false;
  2029. intel_connector = &intel_sdvo_connector->base;
  2030. connector = &intel_connector->base;
  2031. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2032. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2033. if (device == 0) {
  2034. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2035. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2036. } else if (device == 1) {
  2037. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2038. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2039. }
  2040. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2041. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2042. goto err;
  2043. return true;
  2044. err:
  2045. intel_sdvo_destroy(connector);
  2046. return false;
  2047. }
  2048. static bool
  2049. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2050. {
  2051. intel_sdvo->is_tv = false;
  2052. intel_sdvo->base.needs_tv_clock = false;
  2053. intel_sdvo->is_lvds = false;
  2054. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2055. if (flags & SDVO_OUTPUT_TMDS0)
  2056. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2057. return false;
  2058. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2059. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2060. return false;
  2061. /* TV has no XXX1 function block */
  2062. if (flags & SDVO_OUTPUT_SVID0)
  2063. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2064. return false;
  2065. if (flags & SDVO_OUTPUT_CVBS0)
  2066. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2067. return false;
  2068. if (flags & SDVO_OUTPUT_YPRPB0)
  2069. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2070. return false;
  2071. if (flags & SDVO_OUTPUT_RGB0)
  2072. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2073. return false;
  2074. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2075. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2076. return false;
  2077. if (flags & SDVO_OUTPUT_LVDS0)
  2078. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2079. return false;
  2080. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2081. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2082. return false;
  2083. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2084. unsigned char bytes[2];
  2085. intel_sdvo->controlled_output = 0;
  2086. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2087. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2088. SDVO_NAME(intel_sdvo),
  2089. bytes[0], bytes[1]);
  2090. return false;
  2091. }
  2092. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2093. return true;
  2094. }
  2095. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2096. {
  2097. struct drm_device *dev = intel_sdvo->base.base.dev;
  2098. struct drm_connector *connector, *tmp;
  2099. list_for_each_entry_safe(connector, tmp,
  2100. &dev->mode_config.connector_list, head) {
  2101. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2102. intel_sdvo_destroy(connector);
  2103. }
  2104. }
  2105. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2106. struct intel_sdvo_connector *intel_sdvo_connector,
  2107. int type)
  2108. {
  2109. struct drm_device *dev = intel_sdvo->base.base.dev;
  2110. struct intel_sdvo_tv_format format;
  2111. uint32_t format_map, i;
  2112. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2113. return false;
  2114. BUILD_BUG_ON(sizeof(format) != 6);
  2115. if (!intel_sdvo_get_value(intel_sdvo,
  2116. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2117. &format, sizeof(format)))
  2118. return false;
  2119. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2120. if (format_map == 0)
  2121. return false;
  2122. intel_sdvo_connector->format_supported_num = 0;
  2123. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2124. if (format_map & (1 << i))
  2125. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2126. intel_sdvo_connector->tv_format =
  2127. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2128. "mode", intel_sdvo_connector->format_supported_num);
  2129. if (!intel_sdvo_connector->tv_format)
  2130. return false;
  2131. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2132. drm_property_add_enum(
  2133. intel_sdvo_connector->tv_format, i,
  2134. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2135. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2136. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2137. intel_sdvo_connector->tv_format, 0);
  2138. return true;
  2139. }
  2140. #define ENHANCEMENT(name, NAME) do { \
  2141. if (enhancements.name) { \
  2142. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2143. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2144. return false; \
  2145. intel_sdvo_connector->max_##name = data_value[0]; \
  2146. intel_sdvo_connector->cur_##name = response; \
  2147. intel_sdvo_connector->name = \
  2148. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2149. if (!intel_sdvo_connector->name) return false; \
  2150. drm_object_attach_property(&connector->base, \
  2151. intel_sdvo_connector->name, \
  2152. intel_sdvo_connector->cur_##name); \
  2153. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2154. data_value[0], data_value[1], response); \
  2155. } \
  2156. } while (0)
  2157. static bool
  2158. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2159. struct intel_sdvo_connector *intel_sdvo_connector,
  2160. struct intel_sdvo_enhancements_reply enhancements)
  2161. {
  2162. struct drm_device *dev = intel_sdvo->base.base.dev;
  2163. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2164. uint16_t response, data_value[2];
  2165. /* when horizontal overscan is supported, Add the left/right property */
  2166. if (enhancements.overscan_h) {
  2167. if (!intel_sdvo_get_value(intel_sdvo,
  2168. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2169. &data_value, 4))
  2170. return false;
  2171. if (!intel_sdvo_get_value(intel_sdvo,
  2172. SDVO_CMD_GET_OVERSCAN_H,
  2173. &response, 2))
  2174. return false;
  2175. intel_sdvo_connector->max_hscan = data_value[0];
  2176. intel_sdvo_connector->left_margin = data_value[0] - response;
  2177. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2178. intel_sdvo_connector->left =
  2179. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2180. if (!intel_sdvo_connector->left)
  2181. return false;
  2182. drm_object_attach_property(&connector->base,
  2183. intel_sdvo_connector->left,
  2184. intel_sdvo_connector->left_margin);
  2185. intel_sdvo_connector->right =
  2186. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2187. if (!intel_sdvo_connector->right)
  2188. return false;
  2189. drm_object_attach_property(&connector->base,
  2190. intel_sdvo_connector->right,
  2191. intel_sdvo_connector->right_margin);
  2192. DRM_DEBUG_KMS("h_overscan: max %d, "
  2193. "default %d, current %d\n",
  2194. data_value[0], data_value[1], response);
  2195. }
  2196. if (enhancements.overscan_v) {
  2197. if (!intel_sdvo_get_value(intel_sdvo,
  2198. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2199. &data_value, 4))
  2200. return false;
  2201. if (!intel_sdvo_get_value(intel_sdvo,
  2202. SDVO_CMD_GET_OVERSCAN_V,
  2203. &response, 2))
  2204. return false;
  2205. intel_sdvo_connector->max_vscan = data_value[0];
  2206. intel_sdvo_connector->top_margin = data_value[0] - response;
  2207. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2208. intel_sdvo_connector->top =
  2209. drm_property_create_range(dev, 0,
  2210. "top_margin", 0, data_value[0]);
  2211. if (!intel_sdvo_connector->top)
  2212. return false;
  2213. drm_object_attach_property(&connector->base,
  2214. intel_sdvo_connector->top,
  2215. intel_sdvo_connector->top_margin);
  2216. intel_sdvo_connector->bottom =
  2217. drm_property_create_range(dev, 0,
  2218. "bottom_margin", 0, data_value[0]);
  2219. if (!intel_sdvo_connector->bottom)
  2220. return false;
  2221. drm_object_attach_property(&connector->base,
  2222. intel_sdvo_connector->bottom,
  2223. intel_sdvo_connector->bottom_margin);
  2224. DRM_DEBUG_KMS("v_overscan: max %d, "
  2225. "default %d, current %d\n",
  2226. data_value[0], data_value[1], response);
  2227. }
  2228. ENHANCEMENT(hpos, HPOS);
  2229. ENHANCEMENT(vpos, VPOS);
  2230. ENHANCEMENT(saturation, SATURATION);
  2231. ENHANCEMENT(contrast, CONTRAST);
  2232. ENHANCEMENT(hue, HUE);
  2233. ENHANCEMENT(sharpness, SHARPNESS);
  2234. ENHANCEMENT(brightness, BRIGHTNESS);
  2235. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2236. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2237. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2238. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2239. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2240. if (enhancements.dot_crawl) {
  2241. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2242. return false;
  2243. intel_sdvo_connector->max_dot_crawl = 1;
  2244. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2245. intel_sdvo_connector->dot_crawl =
  2246. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2247. if (!intel_sdvo_connector->dot_crawl)
  2248. return false;
  2249. drm_object_attach_property(&connector->base,
  2250. intel_sdvo_connector->dot_crawl,
  2251. intel_sdvo_connector->cur_dot_crawl);
  2252. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2253. }
  2254. return true;
  2255. }
  2256. static bool
  2257. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2258. struct intel_sdvo_connector *intel_sdvo_connector,
  2259. struct intel_sdvo_enhancements_reply enhancements)
  2260. {
  2261. struct drm_device *dev = intel_sdvo->base.base.dev;
  2262. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2263. uint16_t response, data_value[2];
  2264. ENHANCEMENT(brightness, BRIGHTNESS);
  2265. return true;
  2266. }
  2267. #undef ENHANCEMENT
  2268. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2269. struct intel_sdvo_connector *intel_sdvo_connector)
  2270. {
  2271. union {
  2272. struct intel_sdvo_enhancements_reply reply;
  2273. uint16_t response;
  2274. } enhancements;
  2275. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2276. enhancements.response = 0;
  2277. intel_sdvo_get_value(intel_sdvo,
  2278. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2279. &enhancements, sizeof(enhancements));
  2280. if (enhancements.response == 0) {
  2281. DRM_DEBUG_KMS("No enhancement is supported\n");
  2282. return true;
  2283. }
  2284. if (IS_TV(intel_sdvo_connector))
  2285. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2286. else if (IS_LVDS(intel_sdvo_connector))
  2287. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2288. else
  2289. return true;
  2290. }
  2291. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2292. struct i2c_msg *msgs,
  2293. int num)
  2294. {
  2295. struct intel_sdvo *sdvo = adapter->algo_data;
  2296. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2297. return -EIO;
  2298. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2299. }
  2300. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2301. {
  2302. struct intel_sdvo *sdvo = adapter->algo_data;
  2303. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2304. }
  2305. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2306. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2307. .functionality = intel_sdvo_ddc_proxy_func
  2308. };
  2309. static bool
  2310. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2311. struct drm_device *dev)
  2312. {
  2313. sdvo->ddc.owner = THIS_MODULE;
  2314. sdvo->ddc.class = I2C_CLASS_DDC;
  2315. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2316. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2317. sdvo->ddc.algo_data = sdvo;
  2318. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2319. return i2c_add_adapter(&sdvo->ddc) == 0;
  2320. }
  2321. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2322. {
  2323. struct drm_i915_private *dev_priv = dev->dev_private;
  2324. struct intel_encoder *intel_encoder;
  2325. struct intel_sdvo *intel_sdvo;
  2326. u32 hotplug_mask;
  2327. int i;
  2328. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2329. if (!intel_sdvo)
  2330. return false;
  2331. intel_sdvo->sdvo_reg = sdvo_reg;
  2332. intel_sdvo->is_sdvob = is_sdvob;
  2333. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2334. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2335. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2336. goto err_i2c_bus;
  2337. /* encoder type will be decided later */
  2338. intel_encoder = &intel_sdvo->base;
  2339. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2340. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2341. /* Read the regs to test if we can talk to the device */
  2342. for (i = 0; i < 0x40; i++) {
  2343. u8 byte;
  2344. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2345. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2346. SDVO_NAME(intel_sdvo));
  2347. goto err;
  2348. }
  2349. }
  2350. hotplug_mask = 0;
  2351. if (IS_G4X(dev)) {
  2352. hotplug_mask = intel_sdvo->is_sdvob ?
  2353. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2354. } else if (IS_GEN4(dev)) {
  2355. hotplug_mask = intel_sdvo->is_sdvob ?
  2356. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2357. } else {
  2358. hotplug_mask = intel_sdvo->is_sdvob ?
  2359. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2360. }
  2361. drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
  2362. intel_encoder->disable = intel_disable_sdvo;
  2363. intel_encoder->enable = intel_enable_sdvo;
  2364. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2365. /* In default case sdvo lvds is false */
  2366. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2367. goto err;
  2368. if (intel_sdvo_output_setup(intel_sdvo,
  2369. intel_sdvo->caps.output_flags) != true) {
  2370. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2371. SDVO_NAME(intel_sdvo));
  2372. /* Output_setup can leave behind connectors! */
  2373. goto err_output;
  2374. }
  2375. /*
  2376. * Cloning SDVO with anything is often impossible, since the SDVO
  2377. * encoder can request a special input timing mode. And even if that's
  2378. * not the case we have evidence that cloning a plain unscaled mode with
  2379. * VGA doesn't really work. Furthermore the cloning flags are way too
  2380. * simplistic anyway to express such constraints, so just give up on
  2381. * cloning for SDVO encoders.
  2382. */
  2383. intel_sdvo->base.cloneable = false;
  2384. /* Only enable the hotplug irq if we need it, to work around noisy
  2385. * hotplug lines.
  2386. */
  2387. if (intel_sdvo->hotplug_active)
  2388. dev_priv->hotplug_supported_mask |= hotplug_mask;
  2389. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2390. /* Set the input timing to the screen. Assume always input 0. */
  2391. if (!intel_sdvo_set_target_input(intel_sdvo))
  2392. goto err_output;
  2393. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2394. &intel_sdvo->pixel_clock_min,
  2395. &intel_sdvo->pixel_clock_max))
  2396. goto err_output;
  2397. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2398. "clock range %dMHz - %dMHz, "
  2399. "input 1: %c, input 2: %c, "
  2400. "output 1: %c, output 2: %c\n",
  2401. SDVO_NAME(intel_sdvo),
  2402. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2403. intel_sdvo->caps.device_rev_id,
  2404. intel_sdvo->pixel_clock_min / 1000,
  2405. intel_sdvo->pixel_clock_max / 1000,
  2406. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2407. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2408. /* check currently supported outputs */
  2409. intel_sdvo->caps.output_flags &
  2410. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2411. intel_sdvo->caps.output_flags &
  2412. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2413. return true;
  2414. err_output:
  2415. intel_sdvo_output_cleanup(intel_sdvo);
  2416. err:
  2417. drm_encoder_cleanup(&intel_encoder->base);
  2418. i2c_del_adapter(&intel_sdvo->ddc);
  2419. err_i2c_bus:
  2420. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2421. kfree(intel_sdvo);
  2422. return false;
  2423. }