psb_intel_sdvo.c 81 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/module.h>
  29. #include <linux/i2c.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "psb_intel_drv.h"
  36. #include <drm/gma_drm.h>
  37. #include "psb_drv.h"
  38. #include "psb_intel_sdvo_regs.h"
  39. #include "psb_intel_reg.h"
  40. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  41. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  42. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  43. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
  44. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  45. SDVO_TV_MASK)
  46. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  47. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  48. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  49. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct psb_intel_sdvo {
  61. struct psb_intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. int sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct psb_intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /**
  82. * This is used to select the color range of RBG outputs in HDMI mode.
  83. * It is only valid when using TMDS encoding and 8 bit per color mode.
  84. */
  85. uint32_t color_range;
  86. /**
  87. * This is set if we're going to treat the device as TV-out.
  88. *
  89. * While we have these nice friendly flags for output types that ought
  90. * to decide this for us, the S-Video output on our HDMI+S-Video card
  91. * shows up as RGB1 (VGA).
  92. */
  93. bool is_tv;
  94. /* This is for current tv format name */
  95. int tv_format_index;
  96. /**
  97. * This is set if we treat the device as HDMI, instead of DVI.
  98. */
  99. bool is_hdmi;
  100. bool has_hdmi_monitor;
  101. bool has_hdmi_audio;
  102. /**
  103. * This is set if we detect output of sdvo device as LVDS and
  104. * have a valid fixed mode to use with the panel.
  105. */
  106. bool is_lvds;
  107. /**
  108. * This is sdvo fixed pannel mode pointer
  109. */
  110. struct drm_display_mode *sdvo_lvds_fixed_mode;
  111. /* DDC bus used by this SDVO encoder */
  112. uint8_t ddc_bus;
  113. /* Input timings for adjusted_mode */
  114. struct psb_intel_sdvo_dtd input_dtd;
  115. };
  116. struct psb_intel_sdvo_connector {
  117. struct psb_intel_connector base;
  118. /* Mark the type of connector */
  119. uint16_t output_flag;
  120. int force_audio;
  121. /* This contains all current supported TV format */
  122. u8 tv_format_supported[TV_FORMAT_NUM];
  123. int format_supported_num;
  124. struct drm_property *tv_format;
  125. /* add the property for the SDVO-TV */
  126. struct drm_property *left;
  127. struct drm_property *right;
  128. struct drm_property *top;
  129. struct drm_property *bottom;
  130. struct drm_property *hpos;
  131. struct drm_property *vpos;
  132. struct drm_property *contrast;
  133. struct drm_property *saturation;
  134. struct drm_property *hue;
  135. struct drm_property *sharpness;
  136. struct drm_property *flicker_filter;
  137. struct drm_property *flicker_filter_adaptive;
  138. struct drm_property *flicker_filter_2d;
  139. struct drm_property *tv_chroma_filter;
  140. struct drm_property *tv_luma_filter;
  141. struct drm_property *dot_crawl;
  142. /* add the property for the SDVO-TV/LVDS */
  143. struct drm_property *brightness;
  144. /* Add variable to record current setting for the above property */
  145. u32 left_margin, right_margin, top_margin, bottom_margin;
  146. /* this is to get the range of margin.*/
  147. u32 max_hscan, max_vscan;
  148. u32 max_hpos, cur_hpos;
  149. u32 max_vpos, cur_vpos;
  150. u32 cur_brightness, max_brightness;
  151. u32 cur_contrast, max_contrast;
  152. u32 cur_saturation, max_saturation;
  153. u32 cur_hue, max_hue;
  154. u32 cur_sharpness, max_sharpness;
  155. u32 cur_flicker_filter, max_flicker_filter;
  156. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  157. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  158. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  159. u32 cur_tv_luma_filter, max_tv_luma_filter;
  160. u32 cur_dot_crawl, max_dot_crawl;
  161. };
  162. static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder)
  163. {
  164. return container_of(encoder, struct psb_intel_sdvo, base.base);
  165. }
  166. static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  167. {
  168. return container_of(psb_intel_attached_encoder(connector),
  169. struct psb_intel_sdvo, base);
  170. }
  171. static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector)
  172. {
  173. return container_of(to_psb_intel_connector(connector), struct psb_intel_sdvo_connector, base);
  174. }
  175. static bool
  176. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags);
  177. static bool
  178. psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  179. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  180. int type);
  181. static bool
  182. psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  183. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector);
  184. /**
  185. * Writes the SDVOB or SDVOC with the given value, but always writes both
  186. * SDVOB and SDVOC to work around apparent hardware issues (according to
  187. * comments in the BIOS).
  188. */
  189. static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo, u32 val)
  190. {
  191. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  192. u32 bval = val, cval = val;
  193. int i;
  194. if (psb_intel_sdvo->sdvo_reg == SDVOB) {
  195. cval = REG_READ(SDVOC);
  196. } else {
  197. bval = REG_READ(SDVOB);
  198. }
  199. /*
  200. * Write the registers twice for luck. Sometimes,
  201. * writing them only once doesn't appear to 'stick'.
  202. * The BIOS does this too. Yay, magic
  203. */
  204. for (i = 0; i < 2; i++)
  205. {
  206. REG_WRITE(SDVOB, bval);
  207. REG_READ(SDVOB);
  208. REG_WRITE(SDVOC, cval);
  209. REG_READ(SDVOC);
  210. }
  211. }
  212. static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo, u8 addr, u8 *ch)
  213. {
  214. struct i2c_msg msgs[] = {
  215. {
  216. .addr = psb_intel_sdvo->slave_addr,
  217. .flags = 0,
  218. .len = 1,
  219. .buf = &addr,
  220. },
  221. {
  222. .addr = psb_intel_sdvo->slave_addr,
  223. .flags = I2C_M_RD,
  224. .len = 1,
  225. .buf = ch,
  226. }
  227. };
  228. int ret;
  229. if ((ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, 2)) == 2)
  230. return true;
  231. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  232. return false;
  233. }
  234. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  235. /** Mapping of command numbers to names, for debug output */
  236. static const struct _sdvo_cmd_name {
  237. u8 cmd;
  238. const char *name;
  239. } sdvo_cmd_names[] = {
  240. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  241. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  242. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  243. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  244. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  245. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  246. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  247. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  248. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  249. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  250. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  251. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  252. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  253. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  254. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  283. /* Add the op code for SDVO enhancements */
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  298. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  328. /* HDMI op code */
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  343. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  349. };
  350. #define IS_SDVOB(reg) (reg == SDVOB)
  351. #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
  352. static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  353. const void *args, int args_len)
  354. {
  355. int i;
  356. DRM_DEBUG_KMS("%s: W: %02X ",
  357. SDVO_NAME(psb_intel_sdvo), cmd);
  358. for (i = 0; i < args_len; i++)
  359. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  360. for (; i < 8; i++)
  361. DRM_LOG_KMS(" ");
  362. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  363. if (cmd == sdvo_cmd_names[i].cmd) {
  364. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  365. break;
  366. }
  367. }
  368. if (i == ARRAY_SIZE(sdvo_cmd_names))
  369. DRM_LOG_KMS("(%02X)", cmd);
  370. DRM_LOG_KMS("\n");
  371. }
  372. static const char *cmd_status_names[] = {
  373. "Power on",
  374. "Success",
  375. "Not supported",
  376. "Invalid arg",
  377. "Pending",
  378. "Target not specified",
  379. "Scaling not supported"
  380. };
  381. static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  382. const void *args, int args_len)
  383. {
  384. u8 buf[args_len*2 + 2], status;
  385. struct i2c_msg msgs[args_len + 3];
  386. int i, ret;
  387. psb_intel_sdvo_debug_write(psb_intel_sdvo, cmd, args, args_len);
  388. for (i = 0; i < args_len; i++) {
  389. msgs[i].addr = psb_intel_sdvo->slave_addr;
  390. msgs[i].flags = 0;
  391. msgs[i].len = 2;
  392. msgs[i].buf = buf + 2 *i;
  393. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  394. buf[2*i + 1] = ((u8*)args)[i];
  395. }
  396. msgs[i].addr = psb_intel_sdvo->slave_addr;
  397. msgs[i].flags = 0;
  398. msgs[i].len = 2;
  399. msgs[i].buf = buf + 2*i;
  400. buf[2*i + 0] = SDVO_I2C_OPCODE;
  401. buf[2*i + 1] = cmd;
  402. /* the following two are to read the response */
  403. status = SDVO_I2C_CMD_STATUS;
  404. msgs[i+1].addr = psb_intel_sdvo->slave_addr;
  405. msgs[i+1].flags = 0;
  406. msgs[i+1].len = 1;
  407. msgs[i+1].buf = &status;
  408. msgs[i+2].addr = psb_intel_sdvo->slave_addr;
  409. msgs[i+2].flags = I2C_M_RD;
  410. msgs[i+2].len = 1;
  411. msgs[i+2].buf = &status;
  412. ret = i2c_transfer(psb_intel_sdvo->i2c, msgs, i+3);
  413. if (ret < 0) {
  414. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  415. return false;
  416. }
  417. if (ret != i+3) {
  418. /* failure in I2C transfer */
  419. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  420. return false;
  421. }
  422. return true;
  423. }
  424. static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo,
  425. void *response, int response_len)
  426. {
  427. u8 retry = 5;
  428. u8 status;
  429. int i;
  430. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(psb_intel_sdvo));
  431. /*
  432. * The documentation states that all commands will be
  433. * processed within 15µs, and that we need only poll
  434. * the status byte a maximum of 3 times in order for the
  435. * command to be complete.
  436. *
  437. * Check 5 times in case the hardware failed to read the docs.
  438. */
  439. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  440. SDVO_I2C_CMD_STATUS,
  441. &status))
  442. goto log_fail;
  443. while (status == SDVO_CMD_STATUS_PENDING && retry--) {
  444. udelay(15);
  445. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  446. SDVO_I2C_CMD_STATUS,
  447. &status))
  448. goto log_fail;
  449. }
  450. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  451. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  452. else
  453. DRM_LOG_KMS("(??? %d)", status);
  454. if (status != SDVO_CMD_STATUS_SUCCESS)
  455. goto log_fail;
  456. /* Read the command response */
  457. for (i = 0; i < response_len; i++) {
  458. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo,
  459. SDVO_I2C_RETURN_0 + i,
  460. &((u8 *)response)[i]))
  461. goto log_fail;
  462. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  463. }
  464. DRM_LOG_KMS("\n");
  465. return true;
  466. log_fail:
  467. DRM_LOG_KMS("... failed\n");
  468. return false;
  469. }
  470. static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  471. {
  472. if (mode->clock >= 100000)
  473. return 1;
  474. else if (mode->clock >= 50000)
  475. return 2;
  476. else
  477. return 4;
  478. }
  479. static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo,
  480. u8 ddc_bus)
  481. {
  482. /* This must be the immediately preceding write before the i2c xfer */
  483. return psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  484. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  485. &ddc_bus, 1);
  486. }
  487. static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, const void *data, int len)
  488. {
  489. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, data, len))
  490. return false;
  491. return psb_intel_sdvo_read_response(psb_intel_sdvo, NULL, 0);
  492. }
  493. static bool
  494. psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd, void *value, int len)
  495. {
  496. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo, cmd, NULL, 0))
  497. return false;
  498. return psb_intel_sdvo_read_response(psb_intel_sdvo, value, len);
  499. }
  500. static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo)
  501. {
  502. struct psb_intel_sdvo_set_target_input_args targets = {0};
  503. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  504. SDVO_CMD_SET_TARGET_INPUT,
  505. &targets, sizeof(targets));
  506. }
  507. /**
  508. * Return whether each input is trained.
  509. *
  510. * This function is making an assumption about the layout of the response,
  511. * which should be checked against the docs.
  512. */
  513. static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo, bool *input_1, bool *input_2)
  514. {
  515. struct psb_intel_sdvo_get_trained_inputs_response response;
  516. BUILD_BUG_ON(sizeof(response) != 1);
  517. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  518. &response, sizeof(response)))
  519. return false;
  520. *input_1 = response.input0_trained;
  521. *input_2 = response.input1_trained;
  522. return true;
  523. }
  524. static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo,
  525. u16 outputs)
  526. {
  527. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  528. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  529. &outputs, sizeof(outputs));
  530. }
  531. static bool psb_intel_sdvo_set_encoder_power_state(struct psb_intel_sdvo *psb_intel_sdvo,
  532. int mode)
  533. {
  534. u8 state = SDVO_ENCODER_STATE_ON;
  535. switch (mode) {
  536. case DRM_MODE_DPMS_ON:
  537. state = SDVO_ENCODER_STATE_ON;
  538. break;
  539. case DRM_MODE_DPMS_STANDBY:
  540. state = SDVO_ENCODER_STATE_STANDBY;
  541. break;
  542. case DRM_MODE_DPMS_SUSPEND:
  543. state = SDVO_ENCODER_STATE_SUSPEND;
  544. break;
  545. case DRM_MODE_DPMS_OFF:
  546. state = SDVO_ENCODER_STATE_OFF;
  547. break;
  548. }
  549. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  550. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  551. }
  552. static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo,
  553. int *clock_min,
  554. int *clock_max)
  555. {
  556. struct psb_intel_sdvo_pixel_clock_range clocks;
  557. BUILD_BUG_ON(sizeof(clocks) != 4);
  558. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  559. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  560. &clocks, sizeof(clocks)))
  561. return false;
  562. /* Convert the values from units of 10 kHz to kHz. */
  563. *clock_min = clocks.min * 10;
  564. *clock_max = clocks.max * 10;
  565. return true;
  566. }
  567. static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo,
  568. u16 outputs)
  569. {
  570. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  571. SDVO_CMD_SET_TARGET_OUTPUT,
  572. &outputs, sizeof(outputs));
  573. }
  574. static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo, u8 cmd,
  575. struct psb_intel_sdvo_dtd *dtd)
  576. {
  577. return psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  578. psb_intel_sdvo_set_value(psb_intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  579. }
  580. static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  581. struct psb_intel_sdvo_dtd *dtd)
  582. {
  583. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  584. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  585. }
  586. static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  587. struct psb_intel_sdvo_dtd *dtd)
  588. {
  589. return psb_intel_sdvo_set_timing(psb_intel_sdvo,
  590. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  591. }
  592. static bool
  593. psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  594. uint16_t clock,
  595. uint16_t width,
  596. uint16_t height)
  597. {
  598. struct psb_intel_sdvo_preferred_input_timing_args args;
  599. memset(&args, 0, sizeof(args));
  600. args.clock = clock;
  601. args.width = width;
  602. args.height = height;
  603. args.interlace = 0;
  604. if (psb_intel_sdvo->is_lvds &&
  605. (psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  606. psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  607. args.scaled = 1;
  608. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  609. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  610. &args, sizeof(args));
  611. }
  612. static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo,
  613. struct psb_intel_sdvo_dtd *dtd)
  614. {
  615. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  616. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  617. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  618. &dtd->part1, sizeof(dtd->part1)) &&
  619. psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  620. &dtd->part2, sizeof(dtd->part2));
  621. }
  622. static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo, u8 val)
  623. {
  624. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  625. }
  626. static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd,
  627. const struct drm_display_mode *mode)
  628. {
  629. uint16_t width, height;
  630. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  631. uint16_t h_sync_offset, v_sync_offset;
  632. width = mode->crtc_hdisplay;
  633. height = mode->crtc_vdisplay;
  634. /* do some mode translations */
  635. h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
  636. h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
  637. v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
  638. v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
  639. h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
  640. v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
  641. dtd->part1.clock = mode->clock / 10;
  642. dtd->part1.h_active = width & 0xff;
  643. dtd->part1.h_blank = h_blank_len & 0xff;
  644. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  645. ((h_blank_len >> 8) & 0xf);
  646. dtd->part1.v_active = height & 0xff;
  647. dtd->part1.v_blank = v_blank_len & 0xff;
  648. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  649. ((v_blank_len >> 8) & 0xf);
  650. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  651. dtd->part2.h_sync_width = h_sync_len & 0xff;
  652. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  653. (v_sync_len & 0xf);
  654. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  655. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  656. ((v_sync_len & 0x30) >> 4);
  657. dtd->part2.dtd_flags = 0x18;
  658. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  659. dtd->part2.dtd_flags |= 0x2;
  660. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  661. dtd->part2.dtd_flags |= 0x4;
  662. dtd->part2.sdvo_flags = 0;
  663. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  664. dtd->part2.reserved = 0;
  665. }
  666. static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  667. const struct psb_intel_sdvo_dtd *dtd)
  668. {
  669. mode->hdisplay = dtd->part1.h_active;
  670. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  671. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  672. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  673. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  674. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  675. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  676. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  677. mode->vdisplay = dtd->part1.v_active;
  678. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  679. mode->vsync_start = mode->vdisplay;
  680. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  681. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  682. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  683. mode->vsync_end = mode->vsync_start +
  684. (dtd->part2.v_sync_off_width & 0xf);
  685. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  686. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  687. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  688. mode->clock = dtd->part1.clock * 10;
  689. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  690. if (dtd->part2.dtd_flags & 0x2)
  691. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  692. if (dtd->part2.dtd_flags & 0x4)
  693. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  694. }
  695. static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo)
  696. {
  697. struct psb_intel_sdvo_encode encode;
  698. BUILD_BUG_ON(sizeof(encode) != 2);
  699. return psb_intel_sdvo_get_value(psb_intel_sdvo,
  700. SDVO_CMD_GET_SUPP_ENCODE,
  701. &encode, sizeof(encode));
  702. }
  703. static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo,
  704. uint8_t mode)
  705. {
  706. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  707. }
  708. static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo,
  709. uint8_t mode)
  710. {
  711. return psb_intel_sdvo_set_value(psb_intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  712. }
  713. #if 0
  714. static void psb_intel_sdvo_dump_hdmi_buf(struct psb_intel_sdvo *psb_intel_sdvo)
  715. {
  716. int i, j;
  717. uint8_t set_buf_index[2];
  718. uint8_t av_split;
  719. uint8_t buf_size;
  720. uint8_t buf[48];
  721. uint8_t *pos;
  722. psb_intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  723. for (i = 0; i <= av_split; i++) {
  724. set_buf_index[0] = i; set_buf_index[1] = 0;
  725. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  726. set_buf_index, 2);
  727. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  728. psb_intel_sdvo_read_response(encoder, &buf_size, 1);
  729. pos = buf;
  730. for (j = 0; j <= buf_size; j += 8) {
  731. psb_intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  732. NULL, 0);
  733. psb_intel_sdvo_read_response(encoder, pos, 8);
  734. pos += 8;
  735. }
  736. }
  737. }
  738. #endif
  739. static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo)
  740. {
  741. DRM_INFO("HDMI is not supported yet");
  742. return false;
  743. #if 0
  744. struct dip_infoframe avi_if = {
  745. .type = DIP_TYPE_AVI,
  746. .ver = DIP_VERSION_AVI,
  747. .len = DIP_LEN_AVI,
  748. };
  749. uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
  750. uint8_t set_buf_index[2] = { 1, 0 };
  751. uint64_t *data = (uint64_t *)&avi_if;
  752. unsigned i;
  753. intel_dip_infoframe_csum(&avi_if);
  754. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  755. SDVO_CMD_SET_HBUF_INDEX,
  756. set_buf_index, 2))
  757. return false;
  758. for (i = 0; i < sizeof(avi_if); i += 8) {
  759. if (!psb_intel_sdvo_set_value(psb_intel_sdvo,
  760. SDVO_CMD_SET_HBUF_DATA,
  761. data, 8))
  762. return false;
  763. data++;
  764. }
  765. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  766. SDVO_CMD_SET_HBUF_TXRATE,
  767. &tx_rate, 1);
  768. #endif
  769. }
  770. static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo)
  771. {
  772. struct psb_intel_sdvo_tv_format format;
  773. uint32_t format_map;
  774. format_map = 1 << psb_intel_sdvo->tv_format_index;
  775. memset(&format, 0, sizeof(format));
  776. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  777. BUILD_BUG_ON(sizeof(format) != 6);
  778. return psb_intel_sdvo_set_value(psb_intel_sdvo,
  779. SDVO_CMD_SET_TV_FORMAT,
  780. &format, sizeof(format));
  781. }
  782. static bool
  783. psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  784. const struct drm_display_mode *mode)
  785. {
  786. struct psb_intel_sdvo_dtd output_dtd;
  787. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  788. psb_intel_sdvo->attached_output))
  789. return false;
  790. psb_intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  791. if (!psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &output_dtd))
  792. return false;
  793. return true;
  794. }
  795. static bool
  796. psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo,
  797. const struct drm_display_mode *mode,
  798. struct drm_display_mode *adjusted_mode)
  799. {
  800. /* Reset the input timing to the screen. Assume always input 0. */
  801. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  802. return false;
  803. if (!psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo,
  804. mode->clock / 10,
  805. mode->hdisplay,
  806. mode->vdisplay))
  807. return false;
  808. if (!psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo,
  809. &psb_intel_sdvo->input_dtd))
  810. return false;
  811. psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, &psb_intel_sdvo->input_dtd);
  812. drm_mode_set_crtcinfo(adjusted_mode, 0);
  813. return true;
  814. }
  815. static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder,
  816. const struct drm_display_mode *mode,
  817. struct drm_display_mode *adjusted_mode)
  818. {
  819. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  820. int multiplier;
  821. /* We need to construct preferred input timings based on our
  822. * output timings. To do that, we have to set the output
  823. * timings, even though this isn't really the right place in
  824. * the sequence to do it. Oh well.
  825. */
  826. if (psb_intel_sdvo->is_tv) {
  827. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode))
  828. return false;
  829. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  830. mode,
  831. adjusted_mode);
  832. } else if (psb_intel_sdvo->is_lvds) {
  833. if (!psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo,
  834. psb_intel_sdvo->sdvo_lvds_fixed_mode))
  835. return false;
  836. (void) psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo,
  837. mode,
  838. adjusted_mode);
  839. }
  840. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  841. * SDVO device will factor out the multiplier during mode_set.
  842. */
  843. multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode);
  844. psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
  845. return true;
  846. }
  847. static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder,
  848. struct drm_display_mode *mode,
  849. struct drm_display_mode *adjusted_mode)
  850. {
  851. struct drm_device *dev = encoder->dev;
  852. struct drm_crtc *crtc = encoder->crtc;
  853. struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
  854. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  855. u32 sdvox;
  856. struct psb_intel_sdvo_in_out_map in_out;
  857. struct psb_intel_sdvo_dtd input_dtd;
  858. int pixel_multiplier = psb_intel_mode_get_pixel_multiplier(adjusted_mode);
  859. int rate;
  860. if (!mode)
  861. return;
  862. /* First, set the input mapping for the first input to our controlled
  863. * output. This is only correct if we're a single-input device, in
  864. * which case the first input is the output from the appropriate SDVO
  865. * channel on the motherboard. In a two-input device, the first input
  866. * will be SDVOB and the second SDVOC.
  867. */
  868. in_out.in0 = psb_intel_sdvo->attached_output;
  869. in_out.in1 = 0;
  870. psb_intel_sdvo_set_value(psb_intel_sdvo,
  871. SDVO_CMD_SET_IN_OUT_MAP,
  872. &in_out, sizeof(in_out));
  873. /* Set the output timings to the screen */
  874. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  875. psb_intel_sdvo->attached_output))
  876. return;
  877. /* We have tried to get input timing in mode_fixup, and filled into
  878. * adjusted_mode.
  879. */
  880. if (psb_intel_sdvo->is_tv || psb_intel_sdvo->is_lvds) {
  881. input_dtd = psb_intel_sdvo->input_dtd;
  882. } else {
  883. /* Set the output timing to the screen */
  884. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo,
  885. psb_intel_sdvo->attached_output))
  886. return;
  887. psb_intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  888. (void) psb_intel_sdvo_set_output_timing(psb_intel_sdvo, &input_dtd);
  889. }
  890. /* Set the input timing to the screen. Assume always input 0. */
  891. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  892. return;
  893. if (psb_intel_sdvo->has_hdmi_monitor) {
  894. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_HDMI);
  895. psb_intel_sdvo_set_colorimetry(psb_intel_sdvo,
  896. SDVO_COLORIMETRY_RGB256);
  897. psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo);
  898. } else
  899. psb_intel_sdvo_set_encode(psb_intel_sdvo, SDVO_ENCODE_DVI);
  900. if (psb_intel_sdvo->is_tv &&
  901. !psb_intel_sdvo_set_tv_format(psb_intel_sdvo))
  902. return;
  903. (void) psb_intel_sdvo_set_input_timing(psb_intel_sdvo, &input_dtd);
  904. switch (pixel_multiplier) {
  905. default:
  906. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  907. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  908. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  909. }
  910. if (!psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, rate))
  911. return;
  912. /* Set the SDVO control regs. */
  913. sdvox = REG_READ(psb_intel_sdvo->sdvo_reg);
  914. switch (psb_intel_sdvo->sdvo_reg) {
  915. case SDVOB:
  916. sdvox &= SDVOB_PRESERVE_MASK;
  917. break;
  918. case SDVOC:
  919. sdvox &= SDVOC_PRESERVE_MASK;
  920. break;
  921. }
  922. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  923. if (psb_intel_crtc->pipe == 1)
  924. sdvox |= SDVO_PIPE_B_SELECT;
  925. if (psb_intel_sdvo->has_hdmi_audio)
  926. sdvox |= SDVO_AUDIO_ENABLE;
  927. /* FIXME: Check if this is needed for PSB
  928. sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
  929. */
  930. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
  931. sdvox |= SDVO_STALL_SELECT;
  932. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox);
  933. }
  934. static void psb_intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
  935. {
  936. struct drm_device *dev = encoder->dev;
  937. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  938. u32 temp;
  939. switch (mode) {
  940. case DRM_MODE_DPMS_ON:
  941. DRM_DEBUG("DPMS_ON");
  942. break;
  943. case DRM_MODE_DPMS_OFF:
  944. DRM_DEBUG("DPMS_OFF");
  945. break;
  946. default:
  947. DRM_DEBUG("DPMS: %d", mode);
  948. }
  949. if (mode != DRM_MODE_DPMS_ON) {
  950. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0);
  951. if (0)
  952. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  953. if (mode == DRM_MODE_DPMS_OFF) {
  954. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  955. if ((temp & SDVO_ENABLE) != 0) {
  956. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & ~SDVO_ENABLE);
  957. }
  958. }
  959. } else {
  960. bool input1, input2;
  961. int i;
  962. u8 status;
  963. temp = REG_READ(psb_intel_sdvo->sdvo_reg);
  964. if ((temp & SDVO_ENABLE) == 0)
  965. psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | SDVO_ENABLE);
  966. for (i = 0; i < 2; i++)
  967. psb_intel_wait_for_vblank(dev);
  968. status = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, &input1, &input2);
  969. /* Warn if the device reported failure to sync.
  970. * A lot of SDVO devices fail to notify of sync, but it's
  971. * a given it the status is a success, we succeeded.
  972. */
  973. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  974. DRM_DEBUG_KMS("First %s output reported failure to "
  975. "sync\n", SDVO_NAME(psb_intel_sdvo));
  976. }
  977. if (0)
  978. psb_intel_sdvo_set_encoder_power_state(psb_intel_sdvo, mode);
  979. psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, psb_intel_sdvo->attached_output);
  980. }
  981. return;
  982. }
  983. static int psb_intel_sdvo_mode_valid(struct drm_connector *connector,
  984. struct drm_display_mode *mode)
  985. {
  986. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  987. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  988. return MODE_NO_DBLESCAN;
  989. if (psb_intel_sdvo->pixel_clock_min > mode->clock)
  990. return MODE_CLOCK_LOW;
  991. if (psb_intel_sdvo->pixel_clock_max < mode->clock)
  992. return MODE_CLOCK_HIGH;
  993. if (psb_intel_sdvo->is_lvds) {
  994. if (mode->hdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  995. return MODE_PANEL;
  996. if (mode->vdisplay > psb_intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  997. return MODE_PANEL;
  998. }
  999. return MODE_OK;
  1000. }
  1001. static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo, struct psb_intel_sdvo_caps *caps)
  1002. {
  1003. BUILD_BUG_ON(sizeof(*caps) != 8);
  1004. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1005. SDVO_CMD_GET_DEVICE_CAPS,
  1006. caps, sizeof(*caps)))
  1007. return false;
  1008. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1009. " vendor_id: %d\n"
  1010. " device_id: %d\n"
  1011. " device_rev_id: %d\n"
  1012. " sdvo_version_major: %d\n"
  1013. " sdvo_version_minor: %d\n"
  1014. " sdvo_inputs_mask: %d\n"
  1015. " smooth_scaling: %d\n"
  1016. " sharp_scaling: %d\n"
  1017. " up_scaling: %d\n"
  1018. " down_scaling: %d\n"
  1019. " stall_support: %d\n"
  1020. " output_flags: %d\n",
  1021. caps->vendor_id,
  1022. caps->device_id,
  1023. caps->device_rev_id,
  1024. caps->sdvo_version_major,
  1025. caps->sdvo_version_minor,
  1026. caps->sdvo_inputs_mask,
  1027. caps->smooth_scaling,
  1028. caps->sharp_scaling,
  1029. caps->up_scaling,
  1030. caps->down_scaling,
  1031. caps->stall_support,
  1032. caps->output_flags);
  1033. return true;
  1034. }
  1035. /* No use! */
  1036. #if 0
  1037. struct drm_connector* psb_intel_sdvo_find(struct drm_device *dev, int sdvoB)
  1038. {
  1039. struct drm_connector *connector = NULL;
  1040. struct psb_intel_sdvo *iout = NULL;
  1041. struct psb_intel_sdvo *sdvo;
  1042. /* find the sdvo connector */
  1043. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  1044. iout = to_psb_intel_sdvo(connector);
  1045. if (iout->type != INTEL_OUTPUT_SDVO)
  1046. continue;
  1047. sdvo = iout->dev_priv;
  1048. if (sdvo->sdvo_reg == SDVOB && sdvoB)
  1049. return connector;
  1050. if (sdvo->sdvo_reg == SDVOC && !sdvoB)
  1051. return connector;
  1052. }
  1053. return NULL;
  1054. }
  1055. int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector)
  1056. {
  1057. u8 response[2];
  1058. u8 status;
  1059. struct psb_intel_sdvo *psb_intel_sdvo;
  1060. DRM_DEBUG_KMS("\n");
  1061. if (!connector)
  1062. return 0;
  1063. psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1064. return psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1065. &response, 2) && response[0];
  1066. }
  1067. void psb_intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
  1068. {
  1069. u8 response[2];
  1070. u8 status;
  1071. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(connector);
  1072. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1073. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1074. if (on) {
  1075. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
  1076. status = psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1077. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1078. } else {
  1079. response[0] = 0;
  1080. response[1] = 0;
  1081. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
  1082. }
  1083. psb_intel_sdvo_write_cmd(psb_intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
  1084. psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2);
  1085. }
  1086. #endif
  1087. static bool
  1088. psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo)
  1089. {
  1090. /* Is there more than one type of output? */
  1091. int caps = psb_intel_sdvo->caps.output_flags & 0xf;
  1092. return caps & -caps;
  1093. }
  1094. static struct edid *
  1095. psb_intel_sdvo_get_edid(struct drm_connector *connector)
  1096. {
  1097. struct psb_intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1098. return drm_get_edid(connector, &sdvo->ddc);
  1099. }
  1100. /* Mac mini hack -- use the same DDC as the analog connector */
  1101. static struct edid *
  1102. psb_intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1103. {
  1104. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1105. return drm_get_edid(connector,
  1106. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  1107. }
  1108. static enum drm_connector_status
  1109. psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
  1110. {
  1111. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1112. enum drm_connector_status status;
  1113. struct edid *edid;
  1114. edid = psb_intel_sdvo_get_edid(connector);
  1115. if (edid == NULL && psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo)) {
  1116. u8 ddc, saved_ddc = psb_intel_sdvo->ddc_bus;
  1117. /*
  1118. * Don't use the 1 as the argument of DDC bus switch to get
  1119. * the EDID. It is used for SDVO SPD ROM.
  1120. */
  1121. for (ddc = psb_intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1122. psb_intel_sdvo->ddc_bus = ddc;
  1123. edid = psb_intel_sdvo_get_edid(connector);
  1124. if (edid)
  1125. break;
  1126. }
  1127. /*
  1128. * If we found the EDID on the other bus,
  1129. * assume that is the correct DDC bus.
  1130. */
  1131. if (edid == NULL)
  1132. psb_intel_sdvo->ddc_bus = saved_ddc;
  1133. }
  1134. /*
  1135. * When there is no edid and no monitor is connected with VGA
  1136. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1137. */
  1138. if (edid == NULL)
  1139. edid = psb_intel_sdvo_get_analog_edid(connector);
  1140. status = connector_status_unknown;
  1141. if (edid != NULL) {
  1142. /* DDC bus is shared, match EDID to connector type */
  1143. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1144. status = connector_status_connected;
  1145. if (psb_intel_sdvo->is_hdmi) {
  1146. psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1147. psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1148. }
  1149. } else
  1150. status = connector_status_disconnected;
  1151. kfree(edid);
  1152. }
  1153. if (status == connector_status_connected) {
  1154. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1155. if (psb_intel_sdvo_connector->force_audio)
  1156. psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0;
  1157. }
  1158. return status;
  1159. }
  1160. static enum drm_connector_status
  1161. psb_intel_sdvo_detect(struct drm_connector *connector, bool force)
  1162. {
  1163. uint16_t response;
  1164. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1165. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1166. enum drm_connector_status ret;
  1167. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1168. SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
  1169. return connector_status_unknown;
  1170. /* add 30ms delay when the output type might be TV */
  1171. if (psb_intel_sdvo->caps.output_flags &
  1172. (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
  1173. mdelay(30);
  1174. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &response, 2))
  1175. return connector_status_unknown;
  1176. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1177. response & 0xff, response >> 8,
  1178. psb_intel_sdvo_connector->output_flag);
  1179. if (response == 0)
  1180. return connector_status_disconnected;
  1181. psb_intel_sdvo->attached_output = response;
  1182. psb_intel_sdvo->has_hdmi_monitor = false;
  1183. psb_intel_sdvo->has_hdmi_audio = false;
  1184. if ((psb_intel_sdvo_connector->output_flag & response) == 0)
  1185. ret = connector_status_disconnected;
  1186. else if (IS_TMDS(psb_intel_sdvo_connector))
  1187. ret = psb_intel_sdvo_hdmi_sink_detect(connector);
  1188. else {
  1189. struct edid *edid;
  1190. /* if we have an edid check it matches the connection */
  1191. edid = psb_intel_sdvo_get_edid(connector);
  1192. if (edid == NULL)
  1193. edid = psb_intel_sdvo_get_analog_edid(connector);
  1194. if (edid != NULL) {
  1195. if (edid->input & DRM_EDID_INPUT_DIGITAL)
  1196. ret = connector_status_disconnected;
  1197. else
  1198. ret = connector_status_connected;
  1199. kfree(edid);
  1200. } else
  1201. ret = connector_status_connected;
  1202. }
  1203. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1204. if (ret == connector_status_connected) {
  1205. psb_intel_sdvo->is_tv = false;
  1206. psb_intel_sdvo->is_lvds = false;
  1207. psb_intel_sdvo->base.needs_tv_clock = false;
  1208. if (response & SDVO_TV_MASK) {
  1209. psb_intel_sdvo->is_tv = true;
  1210. psb_intel_sdvo->base.needs_tv_clock = true;
  1211. }
  1212. if (response & SDVO_LVDS_MASK)
  1213. psb_intel_sdvo->is_lvds = psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1214. }
  1215. return ret;
  1216. }
  1217. static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1218. {
  1219. struct edid *edid;
  1220. /* set the bus switch and get the modes */
  1221. edid = psb_intel_sdvo_get_edid(connector);
  1222. /*
  1223. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1224. * link between analog and digital outputs. So, if the regular SDVO
  1225. * DDC fails, check to see if the analog output is disconnected, in
  1226. * which case we'll look there for the digital DDC data.
  1227. */
  1228. if (edid == NULL)
  1229. edid = psb_intel_sdvo_get_analog_edid(connector);
  1230. if (edid != NULL) {
  1231. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1232. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1233. bool connector_is_digital = !!IS_TMDS(psb_intel_sdvo_connector);
  1234. if (connector_is_digital == monitor_is_digital) {
  1235. drm_mode_connector_update_edid_property(connector, edid);
  1236. drm_add_edid_modes(connector, edid);
  1237. }
  1238. kfree(edid);
  1239. }
  1240. }
  1241. /*
  1242. * Set of SDVO TV modes.
  1243. * Note! This is in reply order (see loop in get_tv_modes).
  1244. * XXX: all 60Hz refresh?
  1245. */
  1246. static const struct drm_display_mode sdvo_tv_modes[] = {
  1247. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1248. 416, 0, 200, 201, 232, 233, 0,
  1249. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1250. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1251. 416, 0, 240, 241, 272, 273, 0,
  1252. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1253. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1254. 496, 0, 300, 301, 332, 333, 0,
  1255. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1256. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1257. 736, 0, 350, 351, 382, 383, 0,
  1258. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1259. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1260. 736, 0, 400, 401, 432, 433, 0,
  1261. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1262. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1263. 736, 0, 480, 481, 512, 513, 0,
  1264. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1265. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1266. 800, 0, 480, 481, 512, 513, 0,
  1267. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1268. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1269. 800, 0, 576, 577, 608, 609, 0,
  1270. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1271. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1272. 816, 0, 350, 351, 382, 383, 0,
  1273. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1274. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1275. 816, 0, 400, 401, 432, 433, 0,
  1276. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1277. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1278. 816, 0, 480, 481, 512, 513, 0,
  1279. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1280. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1281. 816, 0, 540, 541, 572, 573, 0,
  1282. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1283. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1284. 816, 0, 576, 577, 608, 609, 0,
  1285. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1286. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1287. 864, 0, 576, 577, 608, 609, 0,
  1288. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1289. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1290. 896, 0, 600, 601, 632, 633, 0,
  1291. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1292. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1293. 928, 0, 624, 625, 656, 657, 0,
  1294. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1295. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1296. 1016, 0, 766, 767, 798, 799, 0,
  1297. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1298. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1299. 1120, 0, 768, 769, 800, 801, 0,
  1300. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1301. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1302. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1303. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1304. };
  1305. static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1306. {
  1307. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1308. struct psb_intel_sdvo_sdtv_resolution_request tv_res;
  1309. uint32_t reply = 0, format_map = 0;
  1310. int i;
  1311. /* Read the list of supported input resolutions for the selected TV
  1312. * format.
  1313. */
  1314. format_map = 1 << psb_intel_sdvo->tv_format_index;
  1315. memcpy(&tv_res, &format_map,
  1316. min(sizeof(format_map), sizeof(struct psb_intel_sdvo_sdtv_resolution_request)));
  1317. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, psb_intel_sdvo->attached_output))
  1318. return;
  1319. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1320. if (!psb_intel_sdvo_write_cmd(psb_intel_sdvo,
  1321. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1322. &tv_res, sizeof(tv_res)))
  1323. return;
  1324. if (!psb_intel_sdvo_read_response(psb_intel_sdvo, &reply, 3))
  1325. return;
  1326. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1327. if (reply & (1 << i)) {
  1328. struct drm_display_mode *nmode;
  1329. nmode = drm_mode_duplicate(connector->dev,
  1330. &sdvo_tv_modes[i]);
  1331. if (nmode)
  1332. drm_mode_probed_add(connector, nmode);
  1333. }
  1334. }
  1335. static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1336. {
  1337. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1338. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1339. struct drm_display_mode *newmode;
  1340. /*
  1341. * Attempt to get the mode list from DDC.
  1342. * Assume that the preferred modes are
  1343. * arranged in priority order.
  1344. */
  1345. psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c);
  1346. if (list_empty(&connector->probed_modes) == false)
  1347. goto end;
  1348. /* Fetch modes from VBT */
  1349. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1350. newmode = drm_mode_duplicate(connector->dev,
  1351. dev_priv->sdvo_lvds_vbt_mode);
  1352. if (newmode != NULL) {
  1353. /* Guarantee the mode is preferred */
  1354. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1355. DRM_MODE_TYPE_DRIVER);
  1356. drm_mode_probed_add(connector, newmode);
  1357. }
  1358. }
  1359. end:
  1360. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1361. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1362. psb_intel_sdvo->sdvo_lvds_fixed_mode =
  1363. drm_mode_duplicate(connector->dev, newmode);
  1364. drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode,
  1365. 0);
  1366. psb_intel_sdvo->is_lvds = true;
  1367. break;
  1368. }
  1369. }
  1370. }
  1371. static int psb_intel_sdvo_get_modes(struct drm_connector *connector)
  1372. {
  1373. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1374. if (IS_TV(psb_intel_sdvo_connector))
  1375. psb_intel_sdvo_get_tv_modes(connector);
  1376. else if (IS_LVDS(psb_intel_sdvo_connector))
  1377. psb_intel_sdvo_get_lvds_modes(connector);
  1378. else
  1379. psb_intel_sdvo_get_ddc_modes(connector);
  1380. return !list_empty(&connector->probed_modes);
  1381. }
  1382. static void
  1383. psb_intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1384. {
  1385. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1386. struct drm_device *dev = connector->dev;
  1387. if (psb_intel_sdvo_connector->left)
  1388. drm_property_destroy(dev, psb_intel_sdvo_connector->left);
  1389. if (psb_intel_sdvo_connector->right)
  1390. drm_property_destroy(dev, psb_intel_sdvo_connector->right);
  1391. if (psb_intel_sdvo_connector->top)
  1392. drm_property_destroy(dev, psb_intel_sdvo_connector->top);
  1393. if (psb_intel_sdvo_connector->bottom)
  1394. drm_property_destroy(dev, psb_intel_sdvo_connector->bottom);
  1395. if (psb_intel_sdvo_connector->hpos)
  1396. drm_property_destroy(dev, psb_intel_sdvo_connector->hpos);
  1397. if (psb_intel_sdvo_connector->vpos)
  1398. drm_property_destroy(dev, psb_intel_sdvo_connector->vpos);
  1399. if (psb_intel_sdvo_connector->saturation)
  1400. drm_property_destroy(dev, psb_intel_sdvo_connector->saturation);
  1401. if (psb_intel_sdvo_connector->contrast)
  1402. drm_property_destroy(dev, psb_intel_sdvo_connector->contrast);
  1403. if (psb_intel_sdvo_connector->hue)
  1404. drm_property_destroy(dev, psb_intel_sdvo_connector->hue);
  1405. if (psb_intel_sdvo_connector->sharpness)
  1406. drm_property_destroy(dev, psb_intel_sdvo_connector->sharpness);
  1407. if (psb_intel_sdvo_connector->flicker_filter)
  1408. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter);
  1409. if (psb_intel_sdvo_connector->flicker_filter_2d)
  1410. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_2d);
  1411. if (psb_intel_sdvo_connector->flicker_filter_adaptive)
  1412. drm_property_destroy(dev, psb_intel_sdvo_connector->flicker_filter_adaptive);
  1413. if (psb_intel_sdvo_connector->tv_luma_filter)
  1414. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_luma_filter);
  1415. if (psb_intel_sdvo_connector->tv_chroma_filter)
  1416. drm_property_destroy(dev, psb_intel_sdvo_connector->tv_chroma_filter);
  1417. if (psb_intel_sdvo_connector->dot_crawl)
  1418. drm_property_destroy(dev, psb_intel_sdvo_connector->dot_crawl);
  1419. if (psb_intel_sdvo_connector->brightness)
  1420. drm_property_destroy(dev, psb_intel_sdvo_connector->brightness);
  1421. }
  1422. static void psb_intel_sdvo_destroy(struct drm_connector *connector)
  1423. {
  1424. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1425. if (psb_intel_sdvo_connector->tv_format)
  1426. drm_property_destroy(connector->dev,
  1427. psb_intel_sdvo_connector->tv_format);
  1428. psb_intel_sdvo_destroy_enhance_property(connector);
  1429. drm_sysfs_connector_remove(connector);
  1430. drm_connector_cleanup(connector);
  1431. kfree(connector);
  1432. }
  1433. static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1434. {
  1435. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1436. struct edid *edid;
  1437. bool has_audio = false;
  1438. if (!psb_intel_sdvo->is_hdmi)
  1439. return false;
  1440. edid = psb_intel_sdvo_get_edid(connector);
  1441. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1442. has_audio = drm_detect_monitor_audio(edid);
  1443. return has_audio;
  1444. }
  1445. static int
  1446. psb_intel_sdvo_set_property(struct drm_connector *connector,
  1447. struct drm_property *property,
  1448. uint64_t val)
  1449. {
  1450. struct psb_intel_sdvo *psb_intel_sdvo = intel_attached_sdvo(connector);
  1451. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector = to_psb_intel_sdvo_connector(connector);
  1452. struct drm_psb_private *dev_priv = connector->dev->dev_private;
  1453. uint16_t temp_value;
  1454. uint8_t cmd;
  1455. int ret;
  1456. ret = drm_object_property_set_value(&connector->base, property, val);
  1457. if (ret)
  1458. return ret;
  1459. if (property == dev_priv->force_audio_property) {
  1460. int i = val;
  1461. bool has_audio;
  1462. if (i == psb_intel_sdvo_connector->force_audio)
  1463. return 0;
  1464. psb_intel_sdvo_connector->force_audio = i;
  1465. if (i == 0)
  1466. has_audio = psb_intel_sdvo_detect_hdmi_audio(connector);
  1467. else
  1468. has_audio = i > 0;
  1469. if (has_audio == psb_intel_sdvo->has_hdmi_audio)
  1470. return 0;
  1471. psb_intel_sdvo->has_hdmi_audio = has_audio;
  1472. goto done;
  1473. }
  1474. if (property == dev_priv->broadcast_rgb_property) {
  1475. if (val == !!psb_intel_sdvo->color_range)
  1476. return 0;
  1477. psb_intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
  1478. goto done;
  1479. }
  1480. #define CHECK_PROPERTY(name, NAME) \
  1481. if (psb_intel_sdvo_connector->name == property) { \
  1482. if (psb_intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1483. if (psb_intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1484. cmd = SDVO_CMD_SET_##NAME; \
  1485. psb_intel_sdvo_connector->cur_##name = temp_value; \
  1486. goto set_value; \
  1487. }
  1488. if (property == psb_intel_sdvo_connector->tv_format) {
  1489. if (val >= TV_FORMAT_NUM)
  1490. return -EINVAL;
  1491. if (psb_intel_sdvo->tv_format_index ==
  1492. psb_intel_sdvo_connector->tv_format_supported[val])
  1493. return 0;
  1494. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[val];
  1495. goto done;
  1496. } else if (IS_TV_OR_LVDS(psb_intel_sdvo_connector)) {
  1497. temp_value = val;
  1498. if (psb_intel_sdvo_connector->left == property) {
  1499. drm_object_property_set_value(&connector->base,
  1500. psb_intel_sdvo_connector->right, val);
  1501. if (psb_intel_sdvo_connector->left_margin == temp_value)
  1502. return 0;
  1503. psb_intel_sdvo_connector->left_margin = temp_value;
  1504. psb_intel_sdvo_connector->right_margin = temp_value;
  1505. temp_value = psb_intel_sdvo_connector->max_hscan -
  1506. psb_intel_sdvo_connector->left_margin;
  1507. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1508. goto set_value;
  1509. } else if (psb_intel_sdvo_connector->right == property) {
  1510. drm_object_property_set_value(&connector->base,
  1511. psb_intel_sdvo_connector->left, val);
  1512. if (psb_intel_sdvo_connector->right_margin == temp_value)
  1513. return 0;
  1514. psb_intel_sdvo_connector->left_margin = temp_value;
  1515. psb_intel_sdvo_connector->right_margin = temp_value;
  1516. temp_value = psb_intel_sdvo_connector->max_hscan -
  1517. psb_intel_sdvo_connector->left_margin;
  1518. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1519. goto set_value;
  1520. } else if (psb_intel_sdvo_connector->top == property) {
  1521. drm_object_property_set_value(&connector->base,
  1522. psb_intel_sdvo_connector->bottom, val);
  1523. if (psb_intel_sdvo_connector->top_margin == temp_value)
  1524. return 0;
  1525. psb_intel_sdvo_connector->top_margin = temp_value;
  1526. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1527. temp_value = psb_intel_sdvo_connector->max_vscan -
  1528. psb_intel_sdvo_connector->top_margin;
  1529. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1530. goto set_value;
  1531. } else if (psb_intel_sdvo_connector->bottom == property) {
  1532. drm_object_property_set_value(&connector->base,
  1533. psb_intel_sdvo_connector->top, val);
  1534. if (psb_intel_sdvo_connector->bottom_margin == temp_value)
  1535. return 0;
  1536. psb_intel_sdvo_connector->top_margin = temp_value;
  1537. psb_intel_sdvo_connector->bottom_margin = temp_value;
  1538. temp_value = psb_intel_sdvo_connector->max_vscan -
  1539. psb_intel_sdvo_connector->top_margin;
  1540. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1541. goto set_value;
  1542. }
  1543. CHECK_PROPERTY(hpos, HPOS)
  1544. CHECK_PROPERTY(vpos, VPOS)
  1545. CHECK_PROPERTY(saturation, SATURATION)
  1546. CHECK_PROPERTY(contrast, CONTRAST)
  1547. CHECK_PROPERTY(hue, HUE)
  1548. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1549. CHECK_PROPERTY(sharpness, SHARPNESS)
  1550. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1551. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1552. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1553. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1554. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1555. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1556. }
  1557. return -EINVAL; /* unknown property */
  1558. set_value:
  1559. if (!psb_intel_sdvo_set_value(psb_intel_sdvo, cmd, &temp_value, 2))
  1560. return -EIO;
  1561. done:
  1562. if (psb_intel_sdvo->base.base.crtc) {
  1563. struct drm_crtc *crtc = psb_intel_sdvo->base.base.crtc;
  1564. drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
  1565. crtc->y, crtc->fb);
  1566. }
  1567. return 0;
  1568. #undef CHECK_PROPERTY
  1569. }
  1570. static const struct drm_encoder_helper_funcs psb_intel_sdvo_helper_funcs = {
  1571. .dpms = psb_intel_sdvo_dpms,
  1572. .mode_fixup = psb_intel_sdvo_mode_fixup,
  1573. .prepare = psb_intel_encoder_prepare,
  1574. .mode_set = psb_intel_sdvo_mode_set,
  1575. .commit = psb_intel_encoder_commit,
  1576. };
  1577. static const struct drm_connector_funcs psb_intel_sdvo_connector_funcs = {
  1578. .dpms = drm_helper_connector_dpms,
  1579. .detect = psb_intel_sdvo_detect,
  1580. .fill_modes = drm_helper_probe_single_connector_modes,
  1581. .set_property = psb_intel_sdvo_set_property,
  1582. .destroy = psb_intel_sdvo_destroy,
  1583. };
  1584. static const struct drm_connector_helper_funcs psb_intel_sdvo_connector_helper_funcs = {
  1585. .get_modes = psb_intel_sdvo_get_modes,
  1586. .mode_valid = psb_intel_sdvo_mode_valid,
  1587. .best_encoder = psb_intel_best_encoder,
  1588. };
  1589. static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1590. {
  1591. struct psb_intel_sdvo *psb_intel_sdvo = to_psb_intel_sdvo(encoder);
  1592. if (psb_intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1593. drm_mode_destroy(encoder->dev,
  1594. psb_intel_sdvo->sdvo_lvds_fixed_mode);
  1595. i2c_del_adapter(&psb_intel_sdvo->ddc);
  1596. psb_intel_encoder_destroy(encoder);
  1597. }
  1598. static const struct drm_encoder_funcs psb_intel_sdvo_enc_funcs = {
  1599. .destroy = psb_intel_sdvo_enc_destroy,
  1600. };
  1601. static void
  1602. psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo)
  1603. {
  1604. /* FIXME: At the moment, ddc_bus = 2 is the only thing that works.
  1605. * We need to figure out if this is true for all available poulsbo
  1606. * hardware, or if we need to fiddle with the guessing code above.
  1607. * The problem might go away if we can parse sdvo mappings from bios */
  1608. sdvo->ddc_bus = 2;
  1609. #if 0
  1610. uint16_t mask = 0;
  1611. unsigned int num_bits;
  1612. /* Make a mask of outputs less than or equal to our own priority in the
  1613. * list.
  1614. */
  1615. switch (sdvo->controlled_output) {
  1616. case SDVO_OUTPUT_LVDS1:
  1617. mask |= SDVO_OUTPUT_LVDS1;
  1618. case SDVO_OUTPUT_LVDS0:
  1619. mask |= SDVO_OUTPUT_LVDS0;
  1620. case SDVO_OUTPUT_TMDS1:
  1621. mask |= SDVO_OUTPUT_TMDS1;
  1622. case SDVO_OUTPUT_TMDS0:
  1623. mask |= SDVO_OUTPUT_TMDS0;
  1624. case SDVO_OUTPUT_RGB1:
  1625. mask |= SDVO_OUTPUT_RGB1;
  1626. case SDVO_OUTPUT_RGB0:
  1627. mask |= SDVO_OUTPUT_RGB0;
  1628. break;
  1629. }
  1630. /* Count bits to find what number we are in the priority list. */
  1631. mask &= sdvo->caps.output_flags;
  1632. num_bits = hweight16(mask);
  1633. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1634. if (num_bits > 3)
  1635. num_bits = 3;
  1636. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1637. sdvo->ddc_bus = 1 << num_bits;
  1638. #endif
  1639. }
  1640. /**
  1641. * Choose the appropriate DDC bus for control bus switch command for this
  1642. * SDVO output based on the controlled output.
  1643. *
  1644. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1645. * outputs, then LVDS outputs.
  1646. */
  1647. static void
  1648. psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv,
  1649. struct psb_intel_sdvo *sdvo, u32 reg)
  1650. {
  1651. struct sdvo_device_mapping *mapping;
  1652. if (IS_SDVOB(reg))
  1653. mapping = &(dev_priv->sdvo_mappings[0]);
  1654. else
  1655. mapping = &(dev_priv->sdvo_mappings[1]);
  1656. if (mapping->initialized)
  1657. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1658. else
  1659. psb_intel_sdvo_guess_ddc_bus(sdvo);
  1660. }
  1661. static void
  1662. psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv,
  1663. struct psb_intel_sdvo *sdvo, u32 reg)
  1664. {
  1665. struct sdvo_device_mapping *mapping;
  1666. u8 pin, speed;
  1667. if (IS_SDVOB(reg))
  1668. mapping = &dev_priv->sdvo_mappings[0];
  1669. else
  1670. mapping = &dev_priv->sdvo_mappings[1];
  1671. pin = GMBUS_PORT_DPB;
  1672. speed = GMBUS_RATE_1MHZ >> 8;
  1673. if (mapping->initialized) {
  1674. pin = mapping->i2c_pin;
  1675. speed = mapping->i2c_speed;
  1676. }
  1677. if (pin < GMBUS_NUM_PORTS) {
  1678. sdvo->i2c = &dev_priv->gmbus[pin].adapter;
  1679. gma_intel_gmbus_set_speed(sdvo->i2c, speed);
  1680. gma_intel_gmbus_force_bit(sdvo->i2c, true);
  1681. } else
  1682. sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
  1683. }
  1684. static bool
  1685. psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1686. {
  1687. return psb_intel_sdvo_check_supp_encode(psb_intel_sdvo);
  1688. }
  1689. static u8
  1690. psb_intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
  1691. {
  1692. struct drm_psb_private *dev_priv = dev->dev_private;
  1693. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1694. if (IS_SDVOB(sdvo_reg)) {
  1695. my_mapping = &dev_priv->sdvo_mappings[0];
  1696. other_mapping = &dev_priv->sdvo_mappings[1];
  1697. } else {
  1698. my_mapping = &dev_priv->sdvo_mappings[1];
  1699. other_mapping = &dev_priv->sdvo_mappings[0];
  1700. }
  1701. /* If the BIOS described our SDVO device, take advantage of it. */
  1702. if (my_mapping->slave_addr)
  1703. return my_mapping->slave_addr;
  1704. /* If the BIOS only described a different SDVO device, use the
  1705. * address that it isn't using.
  1706. */
  1707. if (other_mapping->slave_addr) {
  1708. if (other_mapping->slave_addr == 0x70)
  1709. return 0x72;
  1710. else
  1711. return 0x70;
  1712. }
  1713. /* No SDVO device info is found for another DVO port,
  1714. * so use mapping assumption we had before BIOS parsing.
  1715. */
  1716. if (IS_SDVOB(sdvo_reg))
  1717. return 0x70;
  1718. else
  1719. return 0x72;
  1720. }
  1721. static void
  1722. psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector,
  1723. struct psb_intel_sdvo *encoder)
  1724. {
  1725. drm_connector_init(encoder->base.base.dev,
  1726. &connector->base.base,
  1727. &psb_intel_sdvo_connector_funcs,
  1728. connector->base.base.connector_type);
  1729. drm_connector_helper_add(&connector->base.base,
  1730. &psb_intel_sdvo_connector_helper_funcs);
  1731. connector->base.base.interlace_allowed = 0;
  1732. connector->base.base.doublescan_allowed = 0;
  1733. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1734. psb_intel_connector_attach_encoder(&connector->base, &encoder->base);
  1735. drm_sysfs_connector_add(&connector->base.base);
  1736. }
  1737. static void
  1738. psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector)
  1739. {
  1740. /* FIXME: We don't support HDMI at the moment
  1741. struct drm_device *dev = connector->base.base.dev;
  1742. intel_attach_force_audio_property(&connector->base.base);
  1743. intel_attach_broadcast_rgb_property(&connector->base.base);
  1744. */
  1745. }
  1746. static bool
  1747. psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1748. {
  1749. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1750. struct drm_connector *connector;
  1751. struct psb_intel_connector *intel_connector;
  1752. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1753. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1754. if (!psb_intel_sdvo_connector)
  1755. return false;
  1756. if (device == 0) {
  1757. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1758. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1759. } else if (device == 1) {
  1760. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1761. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1762. }
  1763. intel_connector = &psb_intel_sdvo_connector->base;
  1764. connector = &intel_connector->base;
  1765. // connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1766. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1767. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1768. if (psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device)) {
  1769. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1770. psb_intel_sdvo->is_hdmi = true;
  1771. }
  1772. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1773. (1 << INTEL_ANALOG_CLONE_BIT));
  1774. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1775. if (psb_intel_sdvo->is_hdmi)
  1776. psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector);
  1777. return true;
  1778. }
  1779. static bool
  1780. psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo, int type)
  1781. {
  1782. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1783. struct drm_connector *connector;
  1784. struct psb_intel_connector *intel_connector;
  1785. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1786. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1787. if (!psb_intel_sdvo_connector)
  1788. return false;
  1789. intel_connector = &psb_intel_sdvo_connector->base;
  1790. connector = &intel_connector->base;
  1791. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1792. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1793. psb_intel_sdvo->controlled_output |= type;
  1794. psb_intel_sdvo_connector->output_flag = type;
  1795. psb_intel_sdvo->is_tv = true;
  1796. psb_intel_sdvo->base.needs_tv_clock = true;
  1797. psb_intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
  1798. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1799. if (!psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type))
  1800. goto err;
  1801. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1802. goto err;
  1803. return true;
  1804. err:
  1805. psb_intel_sdvo_destroy(connector);
  1806. return false;
  1807. }
  1808. static bool
  1809. psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1810. {
  1811. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1812. struct drm_connector *connector;
  1813. struct psb_intel_connector *intel_connector;
  1814. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1815. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1816. if (!psb_intel_sdvo_connector)
  1817. return false;
  1818. intel_connector = &psb_intel_sdvo_connector->base;
  1819. connector = &intel_connector->base;
  1820. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  1821. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  1822. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  1823. if (device == 0) {
  1824. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  1825. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  1826. } else if (device == 1) {
  1827. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  1828. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  1829. }
  1830. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  1831. (1 << INTEL_ANALOG_CLONE_BIT));
  1832. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector,
  1833. psb_intel_sdvo);
  1834. return true;
  1835. }
  1836. static bool
  1837. psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo, int device)
  1838. {
  1839. struct drm_encoder *encoder = &psb_intel_sdvo->base.base;
  1840. struct drm_connector *connector;
  1841. struct psb_intel_connector *intel_connector;
  1842. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector;
  1843. psb_intel_sdvo_connector = kzalloc(sizeof(struct psb_intel_sdvo_connector), GFP_KERNEL);
  1844. if (!psb_intel_sdvo_connector)
  1845. return false;
  1846. intel_connector = &psb_intel_sdvo_connector->base;
  1847. connector = &intel_connector->base;
  1848. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  1849. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  1850. if (device == 0) {
  1851. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  1852. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  1853. } else if (device == 1) {
  1854. psb_intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  1855. psb_intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  1856. }
  1857. psb_intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
  1858. (1 << INTEL_SDVO_LVDS_CLONE_BIT));
  1859. psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo);
  1860. if (!psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector))
  1861. goto err;
  1862. return true;
  1863. err:
  1864. psb_intel_sdvo_destroy(connector);
  1865. return false;
  1866. }
  1867. static bool
  1868. psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo, uint16_t flags)
  1869. {
  1870. psb_intel_sdvo->is_tv = false;
  1871. psb_intel_sdvo->base.needs_tv_clock = false;
  1872. psb_intel_sdvo->is_lvds = false;
  1873. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  1874. if (flags & SDVO_OUTPUT_TMDS0)
  1875. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0))
  1876. return false;
  1877. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  1878. if (!psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1))
  1879. return false;
  1880. /* TV has no XXX1 function block */
  1881. if (flags & SDVO_OUTPUT_SVID0)
  1882. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_SVID0))
  1883. return false;
  1884. if (flags & SDVO_OUTPUT_CVBS0)
  1885. if (!psb_intel_sdvo_tv_init(psb_intel_sdvo, SDVO_OUTPUT_CVBS0))
  1886. return false;
  1887. if (flags & SDVO_OUTPUT_RGB0)
  1888. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 0))
  1889. return false;
  1890. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  1891. if (!psb_intel_sdvo_analog_init(psb_intel_sdvo, 1))
  1892. return false;
  1893. if (flags & SDVO_OUTPUT_LVDS0)
  1894. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0))
  1895. return false;
  1896. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  1897. if (!psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1))
  1898. return false;
  1899. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  1900. unsigned char bytes[2];
  1901. psb_intel_sdvo->controlled_output = 0;
  1902. memcpy(bytes, &psb_intel_sdvo->caps.output_flags, 2);
  1903. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  1904. SDVO_NAME(psb_intel_sdvo),
  1905. bytes[0], bytes[1]);
  1906. return false;
  1907. }
  1908. psb_intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
  1909. return true;
  1910. }
  1911. static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo,
  1912. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1913. int type)
  1914. {
  1915. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1916. struct psb_intel_sdvo_tv_format format;
  1917. uint32_t format_map, i;
  1918. if (!psb_intel_sdvo_set_target_output(psb_intel_sdvo, type))
  1919. return false;
  1920. BUILD_BUG_ON(sizeof(format) != 6);
  1921. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1922. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  1923. &format, sizeof(format)))
  1924. return false;
  1925. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  1926. if (format_map == 0)
  1927. return false;
  1928. psb_intel_sdvo_connector->format_supported_num = 0;
  1929. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  1930. if (format_map & (1 << i))
  1931. psb_intel_sdvo_connector->tv_format_supported[psb_intel_sdvo_connector->format_supported_num++] = i;
  1932. psb_intel_sdvo_connector->tv_format =
  1933. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  1934. "mode", psb_intel_sdvo_connector->format_supported_num);
  1935. if (!psb_intel_sdvo_connector->tv_format)
  1936. return false;
  1937. for (i = 0; i < psb_intel_sdvo_connector->format_supported_num; i++)
  1938. drm_property_add_enum(
  1939. psb_intel_sdvo_connector->tv_format, i,
  1940. i, tv_format_names[psb_intel_sdvo_connector->tv_format_supported[i]]);
  1941. psb_intel_sdvo->tv_format_index = psb_intel_sdvo_connector->tv_format_supported[0];
  1942. drm_object_attach_property(&psb_intel_sdvo_connector->base.base.base,
  1943. psb_intel_sdvo_connector->tv_format, 0);
  1944. return true;
  1945. }
  1946. #define ENHANCEMENT(name, NAME) do { \
  1947. if (enhancements.name) { \
  1948. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  1949. !psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  1950. return false; \
  1951. psb_intel_sdvo_connector->max_##name = data_value[0]; \
  1952. psb_intel_sdvo_connector->cur_##name = response; \
  1953. psb_intel_sdvo_connector->name = \
  1954. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  1955. if (!psb_intel_sdvo_connector->name) return false; \
  1956. drm_object_attach_property(&connector->base, \
  1957. psb_intel_sdvo_connector->name, \
  1958. psb_intel_sdvo_connector->cur_##name); \
  1959. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  1960. data_value[0], data_value[1], response); \
  1961. } \
  1962. } while(0)
  1963. static bool
  1964. psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo,
  1965. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  1966. struct psb_intel_sdvo_enhancements_reply enhancements)
  1967. {
  1968. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  1969. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  1970. uint16_t response, data_value[2];
  1971. /* when horizontal overscan is supported, Add the left/right property */
  1972. if (enhancements.overscan_h) {
  1973. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1974. SDVO_CMD_GET_MAX_OVERSCAN_H,
  1975. &data_value, 4))
  1976. return false;
  1977. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  1978. SDVO_CMD_GET_OVERSCAN_H,
  1979. &response, 2))
  1980. return false;
  1981. psb_intel_sdvo_connector->max_hscan = data_value[0];
  1982. psb_intel_sdvo_connector->left_margin = data_value[0] - response;
  1983. psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin;
  1984. psb_intel_sdvo_connector->left =
  1985. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  1986. if (!psb_intel_sdvo_connector->left)
  1987. return false;
  1988. drm_object_attach_property(&connector->base,
  1989. psb_intel_sdvo_connector->left,
  1990. psb_intel_sdvo_connector->left_margin);
  1991. psb_intel_sdvo_connector->right =
  1992. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  1993. if (!psb_intel_sdvo_connector->right)
  1994. return false;
  1995. drm_object_attach_property(&connector->base,
  1996. psb_intel_sdvo_connector->right,
  1997. psb_intel_sdvo_connector->right_margin);
  1998. DRM_DEBUG_KMS("h_overscan: max %d, "
  1999. "default %d, current %d\n",
  2000. data_value[0], data_value[1], response);
  2001. }
  2002. if (enhancements.overscan_v) {
  2003. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2004. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2005. &data_value, 4))
  2006. return false;
  2007. if (!psb_intel_sdvo_get_value(psb_intel_sdvo,
  2008. SDVO_CMD_GET_OVERSCAN_V,
  2009. &response, 2))
  2010. return false;
  2011. psb_intel_sdvo_connector->max_vscan = data_value[0];
  2012. psb_intel_sdvo_connector->top_margin = data_value[0] - response;
  2013. psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin;
  2014. psb_intel_sdvo_connector->top =
  2015. drm_property_create_range(dev, 0, "top_margin", 0, data_value[0]);
  2016. if (!psb_intel_sdvo_connector->top)
  2017. return false;
  2018. drm_object_attach_property(&connector->base,
  2019. psb_intel_sdvo_connector->top,
  2020. psb_intel_sdvo_connector->top_margin);
  2021. psb_intel_sdvo_connector->bottom =
  2022. drm_property_create_range(dev, 0, "bottom_margin", 0, data_value[0]);
  2023. if (!psb_intel_sdvo_connector->bottom)
  2024. return false;
  2025. drm_object_attach_property(&connector->base,
  2026. psb_intel_sdvo_connector->bottom,
  2027. psb_intel_sdvo_connector->bottom_margin);
  2028. DRM_DEBUG_KMS("v_overscan: max %d, "
  2029. "default %d, current %d\n",
  2030. data_value[0], data_value[1], response);
  2031. }
  2032. ENHANCEMENT(hpos, HPOS);
  2033. ENHANCEMENT(vpos, VPOS);
  2034. ENHANCEMENT(saturation, SATURATION);
  2035. ENHANCEMENT(contrast, CONTRAST);
  2036. ENHANCEMENT(hue, HUE);
  2037. ENHANCEMENT(sharpness, SHARPNESS);
  2038. ENHANCEMENT(brightness, BRIGHTNESS);
  2039. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2040. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2041. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2042. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2043. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2044. if (enhancements.dot_crawl) {
  2045. if (!psb_intel_sdvo_get_value(psb_intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2046. return false;
  2047. psb_intel_sdvo_connector->max_dot_crawl = 1;
  2048. psb_intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2049. psb_intel_sdvo_connector->dot_crawl =
  2050. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2051. if (!psb_intel_sdvo_connector->dot_crawl)
  2052. return false;
  2053. drm_object_attach_property(&connector->base,
  2054. psb_intel_sdvo_connector->dot_crawl,
  2055. psb_intel_sdvo_connector->cur_dot_crawl);
  2056. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2057. }
  2058. return true;
  2059. }
  2060. static bool
  2061. psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo,
  2062. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector,
  2063. struct psb_intel_sdvo_enhancements_reply enhancements)
  2064. {
  2065. struct drm_device *dev = psb_intel_sdvo->base.base.dev;
  2066. struct drm_connector *connector = &psb_intel_sdvo_connector->base.base;
  2067. uint16_t response, data_value[2];
  2068. ENHANCEMENT(brightness, BRIGHTNESS);
  2069. return true;
  2070. }
  2071. #undef ENHANCEMENT
  2072. static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo,
  2073. struct psb_intel_sdvo_connector *psb_intel_sdvo_connector)
  2074. {
  2075. union {
  2076. struct psb_intel_sdvo_enhancements_reply reply;
  2077. uint16_t response;
  2078. } enhancements;
  2079. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2080. enhancements.response = 0;
  2081. psb_intel_sdvo_get_value(psb_intel_sdvo,
  2082. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2083. &enhancements, sizeof(enhancements));
  2084. if (enhancements.response == 0) {
  2085. DRM_DEBUG_KMS("No enhancement is supported\n");
  2086. return true;
  2087. }
  2088. if (IS_TV(psb_intel_sdvo_connector))
  2089. return psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2090. else if(IS_LVDS(psb_intel_sdvo_connector))
  2091. return psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply);
  2092. else
  2093. return true;
  2094. }
  2095. static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2096. struct i2c_msg *msgs,
  2097. int num)
  2098. {
  2099. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2100. if (!psb_intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2101. return -EIO;
  2102. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2103. }
  2104. static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2105. {
  2106. struct psb_intel_sdvo *sdvo = adapter->algo_data;
  2107. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2108. }
  2109. static const struct i2c_algorithm psb_intel_sdvo_ddc_proxy = {
  2110. .master_xfer = psb_intel_sdvo_ddc_proxy_xfer,
  2111. .functionality = psb_intel_sdvo_ddc_proxy_func
  2112. };
  2113. static bool
  2114. psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo,
  2115. struct drm_device *dev)
  2116. {
  2117. sdvo->ddc.owner = THIS_MODULE;
  2118. sdvo->ddc.class = I2C_CLASS_DDC;
  2119. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2120. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2121. sdvo->ddc.algo_data = sdvo;
  2122. sdvo->ddc.algo = &psb_intel_sdvo_ddc_proxy;
  2123. return i2c_add_adapter(&sdvo->ddc) == 0;
  2124. }
  2125. bool psb_intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
  2126. {
  2127. struct drm_psb_private *dev_priv = dev->dev_private;
  2128. struct psb_intel_encoder *psb_intel_encoder;
  2129. struct psb_intel_sdvo *psb_intel_sdvo;
  2130. int i;
  2131. psb_intel_sdvo = kzalloc(sizeof(struct psb_intel_sdvo), GFP_KERNEL);
  2132. if (!psb_intel_sdvo)
  2133. return false;
  2134. psb_intel_sdvo->sdvo_reg = sdvo_reg;
  2135. psb_intel_sdvo->slave_addr = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
  2136. psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2137. if (!psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev)) {
  2138. kfree(psb_intel_sdvo);
  2139. return false;
  2140. }
  2141. /* encoder type will be decided later */
  2142. psb_intel_encoder = &psb_intel_sdvo->base;
  2143. psb_intel_encoder->type = INTEL_OUTPUT_SDVO;
  2144. drm_encoder_init(dev, &psb_intel_encoder->base, &psb_intel_sdvo_enc_funcs, 0);
  2145. /* Read the regs to test if we can talk to the device */
  2146. for (i = 0; i < 0x40; i++) {
  2147. u8 byte;
  2148. if (!psb_intel_sdvo_read_byte(psb_intel_sdvo, i, &byte)) {
  2149. DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
  2150. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2151. goto err;
  2152. }
  2153. }
  2154. if (IS_SDVOB(sdvo_reg))
  2155. dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
  2156. else
  2157. dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
  2158. drm_encoder_helper_add(&psb_intel_encoder->base, &psb_intel_sdvo_helper_funcs);
  2159. /* In default case sdvo lvds is false */
  2160. if (!psb_intel_sdvo_get_capabilities(psb_intel_sdvo, &psb_intel_sdvo->caps))
  2161. goto err;
  2162. if (psb_intel_sdvo_output_setup(psb_intel_sdvo,
  2163. psb_intel_sdvo->caps.output_flags) != true) {
  2164. DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
  2165. IS_SDVOB(sdvo_reg) ? 'B' : 'C');
  2166. goto err;
  2167. }
  2168. psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, sdvo_reg);
  2169. /* Set the input timing to the screen. Assume always input 0. */
  2170. if (!psb_intel_sdvo_set_target_input(psb_intel_sdvo))
  2171. goto err;
  2172. if (!psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo,
  2173. &psb_intel_sdvo->pixel_clock_min,
  2174. &psb_intel_sdvo->pixel_clock_max))
  2175. goto err;
  2176. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2177. "clock range %dMHz - %dMHz, "
  2178. "input 1: %c, input 2: %c, "
  2179. "output 1: %c, output 2: %c\n",
  2180. SDVO_NAME(psb_intel_sdvo),
  2181. psb_intel_sdvo->caps.vendor_id, psb_intel_sdvo->caps.device_id,
  2182. psb_intel_sdvo->caps.device_rev_id,
  2183. psb_intel_sdvo->pixel_clock_min / 1000,
  2184. psb_intel_sdvo->pixel_clock_max / 1000,
  2185. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2186. (psb_intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2187. /* check currently supported outputs */
  2188. psb_intel_sdvo->caps.output_flags &
  2189. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2190. psb_intel_sdvo->caps.output_flags &
  2191. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2192. return true;
  2193. err:
  2194. drm_encoder_cleanup(&psb_intel_encoder->base);
  2195. i2c_del_adapter(&psb_intel_sdvo->ddc);
  2196. kfree(psb_intel_sdvo);
  2197. return false;
  2198. }