cirrus_mode.c 15 KB

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  1. /*
  2. * Copyright 2012 Red Hat
  3. *
  4. * This file is subject to the terms and conditions of the GNU General
  5. * Public License version 2. See the file COPYING in the main
  6. * directory of this archive for more details.
  7. *
  8. * Authors: Matthew Garrett
  9. * Dave Airlie
  10. *
  11. * Portions of this code derived from cirrusfb.c:
  12. * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
  13. *
  14. * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
  15. */
  16. #include <drm/drmP.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <video/cirrus.h>
  19. #include "cirrus_drv.h"
  20. #define CIRRUS_LUT_SIZE 256
  21. #define PALETTE_INDEX 0x8
  22. #define PALETTE_DATA 0x9
  23. /*
  24. * This file contains setup code for the CRTC.
  25. */
  26. static void cirrus_crtc_load_lut(struct drm_crtc *crtc)
  27. {
  28. struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
  29. struct drm_device *dev = crtc->dev;
  30. struct cirrus_device *cdev = dev->dev_private;
  31. int i;
  32. if (!crtc->enabled)
  33. return;
  34. for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
  35. /* VGA registers */
  36. WREG8(PALETTE_INDEX, i);
  37. WREG8(PALETTE_DATA, cirrus_crtc->lut_r[i]);
  38. WREG8(PALETTE_DATA, cirrus_crtc->lut_g[i]);
  39. WREG8(PALETTE_DATA, cirrus_crtc->lut_b[i]);
  40. }
  41. }
  42. /*
  43. * The DRM core requires DPMS functions, but they make little sense in our
  44. * case and so are just stubs
  45. */
  46. static void cirrus_crtc_dpms(struct drm_crtc *crtc, int mode)
  47. {
  48. struct drm_device *dev = crtc->dev;
  49. struct cirrus_device *cdev = dev->dev_private;
  50. u8 sr01, gr0e;
  51. switch (mode) {
  52. case DRM_MODE_DPMS_ON:
  53. sr01 = 0x00;
  54. gr0e = 0x00;
  55. break;
  56. case DRM_MODE_DPMS_STANDBY:
  57. sr01 = 0x20;
  58. gr0e = 0x02;
  59. break;
  60. case DRM_MODE_DPMS_SUSPEND:
  61. sr01 = 0x20;
  62. gr0e = 0x04;
  63. break;
  64. case DRM_MODE_DPMS_OFF:
  65. sr01 = 0x20;
  66. gr0e = 0x06;
  67. break;
  68. default:
  69. return;
  70. }
  71. WREG8(SEQ_INDEX, 0x1);
  72. sr01 |= RREG8(SEQ_DATA) & ~0x20;
  73. WREG_SEQ(0x1, sr01);
  74. WREG8(GFX_INDEX, 0xe);
  75. gr0e |= RREG8(GFX_DATA) & ~0x06;
  76. WREG_GFX(0xe, gr0e);
  77. }
  78. /*
  79. * The core passes the desired mode to the CRTC code to see whether any
  80. * CRTC-specific modifications need to be made to it. We're in a position
  81. * to just pass that straight through, so this does nothing
  82. */
  83. static bool cirrus_crtc_mode_fixup(struct drm_crtc *crtc,
  84. const struct drm_display_mode *mode,
  85. struct drm_display_mode *adjusted_mode)
  86. {
  87. return true;
  88. }
  89. void cirrus_set_start_address(struct drm_crtc *crtc, unsigned offset)
  90. {
  91. struct cirrus_device *cdev = crtc->dev->dev_private;
  92. u32 addr;
  93. u8 tmp;
  94. addr = offset >> 2;
  95. WREG_CRT(0x0c, (u8)((addr >> 8) & 0xff));
  96. WREG_CRT(0x0d, (u8)(addr & 0xff));
  97. WREG8(CRT_INDEX, 0x1b);
  98. tmp = RREG8(CRT_DATA);
  99. tmp &= 0xf2;
  100. tmp |= (addr >> 16) & 0x01;
  101. tmp |= (addr >> 15) & 0x0c;
  102. WREG_CRT(0x1b, tmp);
  103. WREG8(CRT_INDEX, 0x1d);
  104. tmp = RREG8(CRT_DATA);
  105. tmp &= 0x7f;
  106. tmp |= (addr >> 12) & 0x80;
  107. WREG_CRT(0x1d, tmp);
  108. }
  109. /* cirrus is different - we will force move buffers out of VRAM */
  110. static int cirrus_crtc_do_set_base(struct drm_crtc *crtc,
  111. struct drm_framebuffer *fb,
  112. int x, int y, int atomic)
  113. {
  114. struct cirrus_device *cdev = crtc->dev->dev_private;
  115. struct drm_gem_object *obj;
  116. struct cirrus_framebuffer *cirrus_fb;
  117. struct cirrus_bo *bo;
  118. int ret;
  119. u64 gpu_addr;
  120. /* push the previous fb to system ram */
  121. if (!atomic && fb) {
  122. cirrus_fb = to_cirrus_framebuffer(fb);
  123. obj = cirrus_fb->obj;
  124. bo = gem_to_cirrus_bo(obj);
  125. ret = cirrus_bo_reserve(bo, false);
  126. if (ret)
  127. return ret;
  128. cirrus_bo_push_sysram(bo);
  129. cirrus_bo_unreserve(bo);
  130. }
  131. cirrus_fb = to_cirrus_framebuffer(crtc->fb);
  132. obj = cirrus_fb->obj;
  133. bo = gem_to_cirrus_bo(obj);
  134. ret = cirrus_bo_reserve(bo, false);
  135. if (ret)
  136. return ret;
  137. ret = cirrus_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
  138. if (ret) {
  139. cirrus_bo_unreserve(bo);
  140. return ret;
  141. }
  142. if (&cdev->mode_info.gfbdev->gfb == cirrus_fb) {
  143. /* if pushing console in kmap it */
  144. ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
  145. if (ret)
  146. DRM_ERROR("failed to kmap fbcon\n");
  147. }
  148. cirrus_bo_unreserve(bo);
  149. cirrus_set_start_address(crtc, (u32)gpu_addr);
  150. return 0;
  151. }
  152. static int cirrus_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
  153. struct drm_framebuffer *old_fb)
  154. {
  155. return cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
  156. }
  157. /*
  158. * The meat of this driver. The core passes us a mode and we have to program
  159. * it. The modesetting here is the bare minimum required to satisfy the qemu
  160. * emulation of this hardware, and running this against a real device is
  161. * likely to result in an inadequately programmed mode. We've already had
  162. * the opportunity to modify the mode, so whatever we receive here should
  163. * be something that can be correctly programmed and displayed
  164. */
  165. static int cirrus_crtc_mode_set(struct drm_crtc *crtc,
  166. struct drm_display_mode *mode,
  167. struct drm_display_mode *adjusted_mode,
  168. int x, int y, struct drm_framebuffer *old_fb)
  169. {
  170. struct drm_device *dev = crtc->dev;
  171. struct cirrus_device *cdev = dev->dev_private;
  172. int hsyncstart, hsyncend, htotal, hdispend;
  173. int vtotal, vdispend;
  174. int tmp;
  175. int sr07 = 0, hdr = 0;
  176. htotal = mode->htotal / 8;
  177. hsyncend = mode->hsync_end / 8;
  178. hsyncstart = mode->hsync_start / 8;
  179. hdispend = mode->hdisplay / 8;
  180. vtotal = mode->vtotal;
  181. vdispend = mode->vdisplay;
  182. vdispend -= 1;
  183. vtotal -= 2;
  184. htotal -= 5;
  185. hdispend -= 1;
  186. hsyncstart += 1;
  187. hsyncend += 1;
  188. WREG_CRT(VGA_CRTC_V_SYNC_END, 0x20);
  189. WREG_CRT(VGA_CRTC_H_TOTAL, htotal);
  190. WREG_CRT(VGA_CRTC_H_DISP, hdispend);
  191. WREG_CRT(VGA_CRTC_H_SYNC_START, hsyncstart);
  192. WREG_CRT(VGA_CRTC_H_SYNC_END, hsyncend);
  193. WREG_CRT(VGA_CRTC_V_TOTAL, vtotal & 0xff);
  194. WREG_CRT(VGA_CRTC_V_DISP_END, vdispend & 0xff);
  195. tmp = 0x40;
  196. if ((vdispend + 1) & 512)
  197. tmp |= 0x20;
  198. WREG_CRT(VGA_CRTC_MAX_SCAN, tmp);
  199. /*
  200. * Overflow bits for values that don't fit in the standard registers
  201. */
  202. tmp = 16;
  203. if (vtotal & 256)
  204. tmp |= 1;
  205. if (vdispend & 256)
  206. tmp |= 2;
  207. if ((vdispend + 1) & 256)
  208. tmp |= 8;
  209. if (vtotal & 512)
  210. tmp |= 32;
  211. if (vdispend & 512)
  212. tmp |= 64;
  213. WREG_CRT(VGA_CRTC_OVERFLOW, tmp);
  214. tmp = 0;
  215. /* More overflow bits */
  216. if ((htotal + 5) & 64)
  217. tmp |= 16;
  218. if ((htotal + 5) & 128)
  219. tmp |= 32;
  220. if (vtotal & 256)
  221. tmp |= 64;
  222. if (vtotal & 512)
  223. tmp |= 128;
  224. WREG_CRT(CL_CRT1A, tmp);
  225. /* Disable Hercules/CGA compatibility */
  226. WREG_CRT(VGA_CRTC_MODE, 0x03);
  227. WREG8(SEQ_INDEX, 0x7);
  228. sr07 = RREG8(SEQ_DATA);
  229. sr07 &= 0xe0;
  230. hdr = 0;
  231. switch (crtc->fb->bits_per_pixel) {
  232. case 8:
  233. sr07 |= 0x11;
  234. break;
  235. case 16:
  236. sr07 |= 0xc1;
  237. hdr = 0xc0;
  238. break;
  239. case 24:
  240. sr07 |= 0x15;
  241. hdr = 0xc5;
  242. break;
  243. case 32:
  244. sr07 |= 0x19;
  245. hdr = 0xc5;
  246. break;
  247. default:
  248. return -1;
  249. }
  250. WREG_SEQ(0x7, sr07);
  251. /* Program the pitch */
  252. tmp = crtc->fb->pitches[0] / 8;
  253. WREG_CRT(VGA_CRTC_OFFSET, tmp);
  254. /* Enable extended blanking and pitch bits, and enable full memory */
  255. tmp = 0x22;
  256. tmp |= (crtc->fb->pitches[0] >> 7) & 0x10;
  257. tmp |= (crtc->fb->pitches[0] >> 6) & 0x40;
  258. WREG_CRT(0x1b, tmp);
  259. /* Enable high-colour modes */
  260. WREG_GFX(VGA_GFX_MODE, 0x40);
  261. /* And set graphics mode */
  262. WREG_GFX(VGA_GFX_MISC, 0x01);
  263. WREG_HDR(hdr);
  264. cirrus_crtc_do_set_base(crtc, old_fb, x, y, 0);
  265. return 0;
  266. }
  267. /*
  268. * This is called before a mode is programmed. A typical use might be to
  269. * enable DPMS during the programming to avoid seeing intermediate stages,
  270. * but that's not relevant to us
  271. */
  272. static void cirrus_crtc_prepare(struct drm_crtc *crtc)
  273. {
  274. }
  275. /*
  276. * This is called after a mode is programmed. It should reverse anything done
  277. * by the prepare function
  278. */
  279. static void cirrus_crtc_commit(struct drm_crtc *crtc)
  280. {
  281. }
  282. /*
  283. * The core can pass us a set of gamma values to program. We actually only
  284. * use this for 8-bit mode so can't perform smooth fades on deeper modes,
  285. * but it's a requirement that we provide the function
  286. */
  287. static void cirrus_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  288. u16 *blue, uint32_t start, uint32_t size)
  289. {
  290. struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
  291. int i;
  292. if (size != CIRRUS_LUT_SIZE)
  293. return;
  294. for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
  295. cirrus_crtc->lut_r[i] = red[i];
  296. cirrus_crtc->lut_g[i] = green[i];
  297. cirrus_crtc->lut_b[i] = blue[i];
  298. }
  299. cirrus_crtc_load_lut(crtc);
  300. }
  301. /* Simple cleanup function */
  302. static void cirrus_crtc_destroy(struct drm_crtc *crtc)
  303. {
  304. struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
  305. drm_crtc_cleanup(crtc);
  306. kfree(cirrus_crtc);
  307. }
  308. /* These provide the minimum set of functions required to handle a CRTC */
  309. static const struct drm_crtc_funcs cirrus_crtc_funcs = {
  310. .gamma_set = cirrus_crtc_gamma_set,
  311. .set_config = drm_crtc_helper_set_config,
  312. .destroy = cirrus_crtc_destroy,
  313. };
  314. static const struct drm_crtc_helper_funcs cirrus_helper_funcs = {
  315. .dpms = cirrus_crtc_dpms,
  316. .mode_fixup = cirrus_crtc_mode_fixup,
  317. .mode_set = cirrus_crtc_mode_set,
  318. .mode_set_base = cirrus_crtc_mode_set_base,
  319. .prepare = cirrus_crtc_prepare,
  320. .commit = cirrus_crtc_commit,
  321. .load_lut = cirrus_crtc_load_lut,
  322. };
  323. /* CRTC setup */
  324. static void cirrus_crtc_init(struct drm_device *dev)
  325. {
  326. struct cirrus_device *cdev = dev->dev_private;
  327. struct cirrus_crtc *cirrus_crtc;
  328. int i;
  329. cirrus_crtc = kzalloc(sizeof(struct cirrus_crtc) +
  330. (CIRRUSFB_CONN_LIMIT * sizeof(struct drm_connector *)),
  331. GFP_KERNEL);
  332. if (cirrus_crtc == NULL)
  333. return;
  334. drm_crtc_init(dev, &cirrus_crtc->base, &cirrus_crtc_funcs);
  335. drm_mode_crtc_set_gamma_size(&cirrus_crtc->base, CIRRUS_LUT_SIZE);
  336. cdev->mode_info.crtc = cirrus_crtc;
  337. for (i = 0; i < CIRRUS_LUT_SIZE; i++) {
  338. cirrus_crtc->lut_r[i] = i;
  339. cirrus_crtc->lut_g[i] = i;
  340. cirrus_crtc->lut_b[i] = i;
  341. }
  342. drm_crtc_helper_add(&cirrus_crtc->base, &cirrus_helper_funcs);
  343. }
  344. /** Sets the color ramps on behalf of fbcon */
  345. void cirrus_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  346. u16 blue, int regno)
  347. {
  348. struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
  349. cirrus_crtc->lut_r[regno] = red;
  350. cirrus_crtc->lut_g[regno] = green;
  351. cirrus_crtc->lut_b[regno] = blue;
  352. }
  353. /** Gets the color ramps on behalf of fbcon */
  354. void cirrus_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  355. u16 *blue, int regno)
  356. {
  357. struct cirrus_crtc *cirrus_crtc = to_cirrus_crtc(crtc);
  358. *red = cirrus_crtc->lut_r[regno];
  359. *green = cirrus_crtc->lut_g[regno];
  360. *blue = cirrus_crtc->lut_b[regno];
  361. }
  362. static bool cirrus_encoder_mode_fixup(struct drm_encoder *encoder,
  363. const struct drm_display_mode *mode,
  364. struct drm_display_mode *adjusted_mode)
  365. {
  366. return true;
  367. }
  368. static void cirrus_encoder_mode_set(struct drm_encoder *encoder,
  369. struct drm_display_mode *mode,
  370. struct drm_display_mode *adjusted_mode)
  371. {
  372. }
  373. static void cirrus_encoder_dpms(struct drm_encoder *encoder, int state)
  374. {
  375. return;
  376. }
  377. static void cirrus_encoder_prepare(struct drm_encoder *encoder)
  378. {
  379. }
  380. static void cirrus_encoder_commit(struct drm_encoder *encoder)
  381. {
  382. }
  383. void cirrus_encoder_destroy(struct drm_encoder *encoder)
  384. {
  385. struct cirrus_encoder *cirrus_encoder = to_cirrus_encoder(encoder);
  386. drm_encoder_cleanup(encoder);
  387. kfree(cirrus_encoder);
  388. }
  389. static const struct drm_encoder_helper_funcs cirrus_encoder_helper_funcs = {
  390. .dpms = cirrus_encoder_dpms,
  391. .mode_fixup = cirrus_encoder_mode_fixup,
  392. .mode_set = cirrus_encoder_mode_set,
  393. .prepare = cirrus_encoder_prepare,
  394. .commit = cirrus_encoder_commit,
  395. };
  396. static const struct drm_encoder_funcs cirrus_encoder_encoder_funcs = {
  397. .destroy = cirrus_encoder_destroy,
  398. };
  399. static struct drm_encoder *cirrus_encoder_init(struct drm_device *dev)
  400. {
  401. struct drm_encoder *encoder;
  402. struct cirrus_encoder *cirrus_encoder;
  403. cirrus_encoder = kzalloc(sizeof(struct cirrus_encoder), GFP_KERNEL);
  404. if (!cirrus_encoder)
  405. return NULL;
  406. encoder = &cirrus_encoder->base;
  407. encoder->possible_crtcs = 0x1;
  408. drm_encoder_init(dev, encoder, &cirrus_encoder_encoder_funcs,
  409. DRM_MODE_ENCODER_DAC);
  410. drm_encoder_helper_add(encoder, &cirrus_encoder_helper_funcs);
  411. return encoder;
  412. }
  413. int cirrus_vga_get_modes(struct drm_connector *connector)
  414. {
  415. /* Just add a static list of modes */
  416. drm_add_modes_noedid(connector, 640, 480);
  417. drm_add_modes_noedid(connector, 800, 600);
  418. drm_add_modes_noedid(connector, 1024, 768);
  419. drm_add_modes_noedid(connector, 1280, 1024);
  420. return 4;
  421. }
  422. static int cirrus_vga_mode_valid(struct drm_connector *connector,
  423. struct drm_display_mode *mode)
  424. {
  425. /* Any mode we've added is valid */
  426. return MODE_OK;
  427. }
  428. struct drm_encoder *cirrus_connector_best_encoder(struct drm_connector
  429. *connector)
  430. {
  431. int enc_id = connector->encoder_ids[0];
  432. struct drm_mode_object *obj;
  433. struct drm_encoder *encoder;
  434. /* pick the encoder ids */
  435. if (enc_id) {
  436. obj =
  437. drm_mode_object_find(connector->dev, enc_id,
  438. DRM_MODE_OBJECT_ENCODER);
  439. if (!obj)
  440. return NULL;
  441. encoder = obj_to_encoder(obj);
  442. return encoder;
  443. }
  444. return NULL;
  445. }
  446. static enum drm_connector_status cirrus_vga_detect(struct drm_connector
  447. *connector, bool force)
  448. {
  449. return connector_status_connected;
  450. }
  451. static void cirrus_connector_destroy(struct drm_connector *connector)
  452. {
  453. drm_connector_cleanup(connector);
  454. kfree(connector);
  455. }
  456. struct drm_connector_helper_funcs cirrus_vga_connector_helper_funcs = {
  457. .get_modes = cirrus_vga_get_modes,
  458. .mode_valid = cirrus_vga_mode_valid,
  459. .best_encoder = cirrus_connector_best_encoder,
  460. };
  461. struct drm_connector_funcs cirrus_vga_connector_funcs = {
  462. .dpms = drm_helper_connector_dpms,
  463. .detect = cirrus_vga_detect,
  464. .fill_modes = drm_helper_probe_single_connector_modes,
  465. .destroy = cirrus_connector_destroy,
  466. };
  467. static struct drm_connector *cirrus_vga_init(struct drm_device *dev)
  468. {
  469. struct drm_connector *connector;
  470. struct cirrus_connector *cirrus_connector;
  471. cirrus_connector = kzalloc(sizeof(struct cirrus_connector), GFP_KERNEL);
  472. if (!cirrus_connector)
  473. return NULL;
  474. connector = &cirrus_connector->base;
  475. drm_connector_init(dev, connector,
  476. &cirrus_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  477. drm_connector_helper_add(connector, &cirrus_vga_connector_helper_funcs);
  478. return connector;
  479. }
  480. int cirrus_modeset_init(struct cirrus_device *cdev)
  481. {
  482. struct drm_encoder *encoder;
  483. struct drm_connector *connector;
  484. int ret;
  485. drm_mode_config_init(cdev->dev);
  486. cdev->mode_info.mode_config_initialized = true;
  487. cdev->dev->mode_config.max_width = CIRRUS_MAX_FB_WIDTH;
  488. cdev->dev->mode_config.max_height = CIRRUS_MAX_FB_HEIGHT;
  489. cdev->dev->mode_config.fb_base = cdev->mc.vram_base;
  490. cdev->dev->mode_config.preferred_depth = 24;
  491. /* don't prefer a shadow on virt GPU */
  492. cdev->dev->mode_config.prefer_shadow = 0;
  493. cirrus_crtc_init(cdev->dev);
  494. encoder = cirrus_encoder_init(cdev->dev);
  495. if (!encoder) {
  496. DRM_ERROR("cirrus_encoder_init failed\n");
  497. return -1;
  498. }
  499. connector = cirrus_vga_init(cdev->dev);
  500. if (!connector) {
  501. DRM_ERROR("cirrus_vga_init failed\n");
  502. return -1;
  503. }
  504. drm_mode_connector_attach_encoder(connector, encoder);
  505. ret = cirrus_fbdev_init(cdev);
  506. if (ret) {
  507. DRM_ERROR("cirrus_fbdev_init failed\n");
  508. return ret;
  509. }
  510. return 0;
  511. }
  512. void cirrus_modeset_fini(struct cirrus_device *cdev)
  513. {
  514. cirrus_fbdev_fini(cdev);
  515. if (cdev->mode_info.mode_config_initialized) {
  516. drm_mode_config_cleanup(cdev->dev);
  517. cdev->mode_info.mode_config_initialized = false;
  518. }
  519. }