gpio-pca953x.c 20 KB

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  1. /*
  2. * PCA953x 4/8/16 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqdomain.h>
  19. #include <linux/i2c.h>
  20. #include <linux/i2c/pca953x.h>
  21. #include <linux/slab.h>
  22. #ifdef CONFIG_OF_GPIO
  23. #include <linux/of_platform.h>
  24. #endif
  25. #define PCA953X_INPUT 0
  26. #define PCA953X_OUTPUT 1
  27. #define PCA953X_INVERT 2
  28. #define PCA953X_DIRECTION 3
  29. #define REG_ADDR_AI 0x80
  30. #define PCA957X_IN 0
  31. #define PCA957X_INVRT 1
  32. #define PCA957X_BKEN 2
  33. #define PCA957X_PUPD 3
  34. #define PCA957X_CFG 4
  35. #define PCA957X_OUT 5
  36. #define PCA957X_MSK 6
  37. #define PCA957X_INTS 7
  38. #define PCA_GPIO_MASK 0x00FF
  39. #define PCA_INT 0x0100
  40. #define PCA953X_TYPE 0x1000
  41. #define PCA957X_TYPE 0x2000
  42. static const struct i2c_device_id pca953x_id[] = {
  43. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  44. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  45. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  46. { "pca9536", 4 | PCA953X_TYPE, },
  47. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  52. { "pca9556", 8 | PCA953X_TYPE, },
  53. { "pca9557", 8 | PCA953X_TYPE, },
  54. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  55. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  56. { "max7310", 8 | PCA953X_TYPE, },
  57. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  59. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  60. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  61. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  62. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  63. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  64. { }
  65. };
  66. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  67. #define MAX_BANK 5
  68. #define BANK_SZ 8
  69. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  70. struct pca953x_chip {
  71. unsigned gpio_start;
  72. u8 reg_output[MAX_BANK];
  73. u8 reg_direction[MAX_BANK];
  74. struct mutex i2c_lock;
  75. #ifdef CONFIG_GPIO_PCA953X_IRQ
  76. struct mutex irq_lock;
  77. u8 irq_mask[MAX_BANK];
  78. u8 irq_stat[MAX_BANK];
  79. u8 irq_trig_raise[MAX_BANK];
  80. u8 irq_trig_fall[MAX_BANK];
  81. struct irq_domain *domain;
  82. #endif
  83. struct i2c_client *client;
  84. struct gpio_chip gpio_chip;
  85. const char *const *names;
  86. int chip_type;
  87. };
  88. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  89. int off)
  90. {
  91. int ret;
  92. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  93. int offset = off / BANK_SZ;
  94. ret = i2c_smbus_read_byte_data(chip->client,
  95. (reg << bank_shift) + offset);
  96. *val = ret;
  97. if (ret < 0) {
  98. dev_err(&chip->client->dev, "failed reading register\n");
  99. return ret;
  100. }
  101. return 0;
  102. }
  103. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  104. int off)
  105. {
  106. int ret = 0;
  107. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  108. int offset = off / BANK_SZ;
  109. ret = i2c_smbus_write_byte_data(chip->client,
  110. (reg << bank_shift) + offset, val);
  111. if (ret < 0) {
  112. dev_err(&chip->client->dev, "failed writing register\n");
  113. return ret;
  114. }
  115. return 0;
  116. }
  117. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  118. {
  119. int ret = 0;
  120. if (chip->gpio_chip.ngpio <= 8)
  121. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  122. else if (chip->gpio_chip.ngpio >= 24) {
  123. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  124. ret = i2c_smbus_write_i2c_block_data(chip->client,
  125. (reg << bank_shift) | REG_ADDR_AI,
  126. NBANK(chip), val);
  127. }
  128. else {
  129. switch (chip->chip_type) {
  130. case PCA953X_TYPE:
  131. ret = i2c_smbus_write_word_data(chip->client,
  132. reg << 1, (u16) *val);
  133. break;
  134. case PCA957X_TYPE:
  135. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  136. val[0]);
  137. if (ret < 0)
  138. break;
  139. ret = i2c_smbus_write_byte_data(chip->client,
  140. (reg << 1) + 1,
  141. val[1]);
  142. break;
  143. }
  144. }
  145. if (ret < 0) {
  146. dev_err(&chip->client->dev, "failed writing register\n");
  147. return ret;
  148. }
  149. return 0;
  150. }
  151. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  152. {
  153. int ret;
  154. if (chip->gpio_chip.ngpio <= 8) {
  155. ret = i2c_smbus_read_byte_data(chip->client, reg);
  156. *val = ret;
  157. } else if (chip->gpio_chip.ngpio >= 24) {
  158. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  159. ret = i2c_smbus_read_i2c_block_data(chip->client,
  160. (reg << bank_shift) | REG_ADDR_AI,
  161. NBANK(chip), val);
  162. } else {
  163. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  164. val[0] = (u16)ret & 0xFF;
  165. val[1] = (u16)ret >> 8;
  166. }
  167. if (ret < 0) {
  168. dev_err(&chip->client->dev, "failed reading register\n");
  169. return ret;
  170. }
  171. return 0;
  172. }
  173. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  174. {
  175. struct pca953x_chip *chip;
  176. u8 reg_val;
  177. int ret, offset = 0;
  178. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  179. mutex_lock(&chip->i2c_lock);
  180. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  181. switch (chip->chip_type) {
  182. case PCA953X_TYPE:
  183. offset = PCA953X_DIRECTION;
  184. break;
  185. case PCA957X_TYPE:
  186. offset = PCA957X_CFG;
  187. break;
  188. }
  189. ret = pca953x_write_single(chip, offset, reg_val, off);
  190. if (ret)
  191. goto exit;
  192. chip->reg_direction[off / BANK_SZ] = reg_val;
  193. ret = 0;
  194. exit:
  195. mutex_unlock(&chip->i2c_lock);
  196. return ret;
  197. }
  198. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  199. unsigned off, int val)
  200. {
  201. struct pca953x_chip *chip;
  202. u8 reg_val;
  203. int ret, offset = 0;
  204. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  205. mutex_lock(&chip->i2c_lock);
  206. /* set output level */
  207. if (val)
  208. reg_val = chip->reg_output[off / BANK_SZ]
  209. | (1u << (off % BANK_SZ));
  210. else
  211. reg_val = chip->reg_output[off / BANK_SZ]
  212. & ~(1u << (off % BANK_SZ));
  213. switch (chip->chip_type) {
  214. case PCA953X_TYPE:
  215. offset = PCA953X_OUTPUT;
  216. break;
  217. case PCA957X_TYPE:
  218. offset = PCA957X_OUT;
  219. break;
  220. }
  221. ret = pca953x_write_single(chip, offset, reg_val, off);
  222. if (ret)
  223. goto exit;
  224. chip->reg_output[off / BANK_SZ] = reg_val;
  225. /* then direction */
  226. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  227. switch (chip->chip_type) {
  228. case PCA953X_TYPE:
  229. offset = PCA953X_DIRECTION;
  230. break;
  231. case PCA957X_TYPE:
  232. offset = PCA957X_CFG;
  233. break;
  234. }
  235. ret = pca953x_write_single(chip, offset, reg_val, off);
  236. if (ret)
  237. goto exit;
  238. chip->reg_direction[off / BANK_SZ] = reg_val;
  239. ret = 0;
  240. exit:
  241. mutex_unlock(&chip->i2c_lock);
  242. return ret;
  243. }
  244. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  245. {
  246. struct pca953x_chip *chip;
  247. u32 reg_val;
  248. int ret, offset = 0;
  249. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  250. mutex_lock(&chip->i2c_lock);
  251. switch (chip->chip_type) {
  252. case PCA953X_TYPE:
  253. offset = PCA953X_INPUT;
  254. break;
  255. case PCA957X_TYPE:
  256. offset = PCA957X_IN;
  257. break;
  258. }
  259. ret = pca953x_read_single(chip, offset, &reg_val, off);
  260. mutex_unlock(&chip->i2c_lock);
  261. if (ret < 0) {
  262. /* NOTE: diagnostic already emitted; that's all we should
  263. * do unless gpio_*_value_cansleep() calls become different
  264. * from their nonsleeping siblings (and report faults).
  265. */
  266. return 0;
  267. }
  268. return (reg_val & (1u << off)) ? 1 : 0;
  269. }
  270. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  271. {
  272. struct pca953x_chip *chip;
  273. u8 reg_val;
  274. int ret, offset = 0;
  275. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  276. mutex_lock(&chip->i2c_lock);
  277. if (val)
  278. reg_val = chip->reg_output[off / BANK_SZ]
  279. | (1u << (off % BANK_SZ));
  280. else
  281. reg_val = chip->reg_output[off / BANK_SZ]
  282. & ~(1u << (off % BANK_SZ));
  283. switch (chip->chip_type) {
  284. case PCA953X_TYPE:
  285. offset = PCA953X_OUTPUT;
  286. break;
  287. case PCA957X_TYPE:
  288. offset = PCA957X_OUT;
  289. break;
  290. }
  291. ret = pca953x_write_single(chip, offset, reg_val, off);
  292. if (ret)
  293. goto exit;
  294. chip->reg_output[off / BANK_SZ] = reg_val;
  295. exit:
  296. mutex_unlock(&chip->i2c_lock);
  297. }
  298. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  299. {
  300. struct gpio_chip *gc;
  301. gc = &chip->gpio_chip;
  302. gc->direction_input = pca953x_gpio_direction_input;
  303. gc->direction_output = pca953x_gpio_direction_output;
  304. gc->get = pca953x_gpio_get_value;
  305. gc->set = pca953x_gpio_set_value;
  306. gc->can_sleep = 1;
  307. gc->base = chip->gpio_start;
  308. gc->ngpio = gpios;
  309. gc->label = chip->client->name;
  310. gc->dev = &chip->client->dev;
  311. gc->owner = THIS_MODULE;
  312. gc->names = chip->names;
  313. }
  314. #ifdef CONFIG_GPIO_PCA953X_IRQ
  315. static int pca953x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
  316. {
  317. struct pca953x_chip *chip;
  318. chip = container_of(gc, struct pca953x_chip, gpio_chip);
  319. return irq_create_mapping(chip->domain, off);
  320. }
  321. static void pca953x_irq_mask(struct irq_data *d)
  322. {
  323. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  324. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  325. }
  326. static void pca953x_irq_unmask(struct irq_data *d)
  327. {
  328. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  329. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  330. }
  331. static void pca953x_irq_bus_lock(struct irq_data *d)
  332. {
  333. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  334. mutex_lock(&chip->irq_lock);
  335. }
  336. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  337. {
  338. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  339. u8 new_irqs;
  340. int level, i;
  341. /* Look for any newly setup interrupt */
  342. for (i = 0; i < NBANK(chip); i++) {
  343. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  344. new_irqs &= ~chip->reg_direction[i];
  345. while (new_irqs) {
  346. level = __ffs(new_irqs);
  347. pca953x_gpio_direction_input(&chip->gpio_chip,
  348. level + (BANK_SZ * i));
  349. new_irqs &= ~(1 << level);
  350. }
  351. }
  352. mutex_unlock(&chip->irq_lock);
  353. }
  354. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  355. {
  356. struct pca953x_chip *chip = irq_data_get_irq_chip_data(d);
  357. int bank_nb = d->hwirq / BANK_SZ;
  358. u8 mask = 1 << (d->hwirq % BANK_SZ);
  359. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  360. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  361. d->irq, type);
  362. return -EINVAL;
  363. }
  364. if (type & IRQ_TYPE_EDGE_FALLING)
  365. chip->irq_trig_fall[bank_nb] |= mask;
  366. else
  367. chip->irq_trig_fall[bank_nb] &= ~mask;
  368. if (type & IRQ_TYPE_EDGE_RISING)
  369. chip->irq_trig_raise[bank_nb] |= mask;
  370. else
  371. chip->irq_trig_raise[bank_nb] &= ~mask;
  372. return 0;
  373. }
  374. static struct irq_chip pca953x_irq_chip = {
  375. .name = "pca953x",
  376. .irq_mask = pca953x_irq_mask,
  377. .irq_unmask = pca953x_irq_unmask,
  378. .irq_bus_lock = pca953x_irq_bus_lock,
  379. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  380. .irq_set_type = pca953x_irq_set_type,
  381. };
  382. static u8 pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  383. {
  384. u8 cur_stat[MAX_BANK];
  385. u8 old_stat[MAX_BANK];
  386. u8 pendings = 0;
  387. u8 trigger[MAX_BANK], triggers = 0;
  388. int ret, i, offset = 0;
  389. switch (chip->chip_type) {
  390. case PCA953X_TYPE:
  391. offset = PCA953X_INPUT;
  392. break;
  393. case PCA957X_TYPE:
  394. offset = PCA957X_IN;
  395. break;
  396. }
  397. ret = pca953x_read_regs(chip, offset, cur_stat);
  398. if (ret)
  399. return 0;
  400. /* Remove output pins from the equation */
  401. for (i = 0; i < NBANK(chip); i++)
  402. cur_stat[i] &= chip->reg_direction[i];
  403. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  404. for (i = 0; i < NBANK(chip); i++) {
  405. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  406. triggers += trigger[i];
  407. }
  408. if (!triggers)
  409. return 0;
  410. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  411. for (i = 0; i < NBANK(chip); i++) {
  412. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  413. (cur_stat[i] & chip->irq_trig_raise[i]);
  414. pending[i] &= trigger[i];
  415. pendings += pending[i];
  416. }
  417. return pendings;
  418. }
  419. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  420. {
  421. struct pca953x_chip *chip = devid;
  422. u8 pending[MAX_BANK];
  423. u8 level;
  424. int i;
  425. if (!pca953x_irq_pending(chip, pending))
  426. return IRQ_HANDLED;
  427. for (i = 0; i < NBANK(chip); i++) {
  428. while (pending[i]) {
  429. level = __ffs(pending[i]);
  430. handle_nested_irq(irq_find_mapping(chip->domain,
  431. level + (BANK_SZ * i)));
  432. pending[i] &= ~(1 << level);
  433. }
  434. }
  435. return IRQ_HANDLED;
  436. }
  437. static int pca953x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  438. irq_hw_number_t hwirq)
  439. {
  440. irq_clear_status_flags(irq, IRQ_NOREQUEST);
  441. irq_set_chip_data(irq, d->host_data);
  442. irq_set_chip(irq, &pca953x_irq_chip);
  443. irq_set_nested_thread(irq, true);
  444. #ifdef CONFIG_ARM
  445. set_irq_flags(irq, IRQF_VALID);
  446. #else
  447. irq_set_noprobe(irq);
  448. #endif
  449. return 0;
  450. }
  451. static const struct irq_domain_ops pca953x_irq_simple_ops = {
  452. .map = pca953x_gpio_irq_map,
  453. .xlate = irq_domain_xlate_twocell,
  454. };
  455. static int pca953x_irq_setup(struct pca953x_chip *chip,
  456. const struct i2c_device_id *id,
  457. int irq_base)
  458. {
  459. struct i2c_client *client = chip->client;
  460. int ret, i, offset = 0;
  461. if (irq_base != -1
  462. && (id->driver_data & PCA_INT)) {
  463. switch (chip->chip_type) {
  464. case PCA953X_TYPE:
  465. offset = PCA953X_INPUT;
  466. break;
  467. case PCA957X_TYPE:
  468. offset = PCA957X_IN;
  469. break;
  470. }
  471. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  472. if (ret)
  473. return ret;
  474. /*
  475. * There is no way to know which GPIO line generated the
  476. * interrupt. We have to rely on the previous read for
  477. * this purpose.
  478. */
  479. for (i = 0; i < NBANK(chip); i++)
  480. chip->irq_stat[i] &= chip->reg_direction[i];
  481. mutex_init(&chip->irq_lock);
  482. chip->domain = irq_domain_add_simple(client->dev.of_node,
  483. chip->gpio_chip.ngpio,
  484. irq_base,
  485. &pca953x_irq_simple_ops,
  486. NULL);
  487. if (!chip->domain)
  488. return -ENODEV;
  489. ret = devm_request_threaded_irq(&client->dev,
  490. client->irq,
  491. NULL,
  492. pca953x_irq_handler,
  493. IRQF_TRIGGER_LOW | IRQF_ONESHOT,
  494. dev_name(&client->dev), chip);
  495. if (ret) {
  496. dev_err(&client->dev, "failed to request irq %d\n",
  497. client->irq);
  498. return ret;
  499. }
  500. chip->gpio_chip.to_irq = pca953x_gpio_to_irq;
  501. }
  502. return 0;
  503. }
  504. #else /* CONFIG_GPIO_PCA953X_IRQ */
  505. static int pca953x_irq_setup(struct pca953x_chip *chip,
  506. const struct i2c_device_id *id,
  507. int irq_base)
  508. {
  509. struct i2c_client *client = chip->client;
  510. if (irq_base != -1 && (id->driver_data & PCA_INT))
  511. dev_warn(&client->dev, "interrupt support not compiled in\n");
  512. return 0;
  513. }
  514. #endif
  515. /*
  516. * Handlers for alternative sources of platform_data
  517. */
  518. #ifdef CONFIG_OF_GPIO
  519. /*
  520. * Translate OpenFirmware node properties into platform_data
  521. * WARNING: This is DEPRECATED and will be removed eventually!
  522. */
  523. static void
  524. pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
  525. {
  526. struct device_node *node;
  527. const __be32 *val;
  528. int size;
  529. node = client->dev.of_node;
  530. if (node == NULL)
  531. return;
  532. *gpio_base = -1;
  533. val = of_get_property(node, "linux,gpio-base", &size);
  534. WARN(val, "%s: device-tree property 'linux,gpio-base' is deprecated!", __func__);
  535. if (val) {
  536. if (size != sizeof(*val))
  537. dev_warn(&client->dev, "%s: wrong linux,gpio-base\n",
  538. node->full_name);
  539. else
  540. *gpio_base = be32_to_cpup(val);
  541. }
  542. val = of_get_property(node, "polarity", NULL);
  543. WARN(val, "%s: device-tree property 'polarity' is deprecated!", __func__);
  544. if (val)
  545. *invert = *val;
  546. }
  547. #else
  548. static void
  549. pca953x_get_alt_pdata(struct i2c_client *client, int *gpio_base, u32 *invert)
  550. {
  551. *gpio_base = -1;
  552. }
  553. #endif
  554. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  555. {
  556. int ret;
  557. u8 val[MAX_BANK];
  558. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  559. if (ret)
  560. goto out;
  561. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  562. chip->reg_direction);
  563. if (ret)
  564. goto out;
  565. /* set platform specific polarity inversion */
  566. if (invert)
  567. memset(val, 0xFF, NBANK(chip));
  568. else
  569. memset(val, 0, NBANK(chip));
  570. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  571. out:
  572. return ret;
  573. }
  574. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  575. {
  576. int ret;
  577. u8 val[MAX_BANK];
  578. /* Let every port in proper state, that could save power */
  579. memset(val, 0, NBANK(chip));
  580. pca953x_write_regs(chip, PCA957X_PUPD, val);
  581. memset(val, 0xFF, NBANK(chip));
  582. pca953x_write_regs(chip, PCA957X_CFG, val);
  583. memset(val, 0, NBANK(chip));
  584. pca953x_write_regs(chip, PCA957X_OUT, val);
  585. ret = pca953x_read_regs(chip, PCA957X_IN, val);
  586. if (ret)
  587. goto out;
  588. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  589. if (ret)
  590. goto out;
  591. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  592. if (ret)
  593. goto out;
  594. /* set platform specific polarity inversion */
  595. if (invert)
  596. memset(val, 0xFF, NBANK(chip));
  597. else
  598. memset(val, 0, NBANK(chip));
  599. pca953x_write_regs(chip, PCA957X_INVRT, val);
  600. /* To enable register 6, 7 to controll pull up and pull down */
  601. memset(val, 0x02, NBANK(chip));
  602. pca953x_write_regs(chip, PCA957X_BKEN, val);
  603. return 0;
  604. out:
  605. return ret;
  606. }
  607. static int pca953x_probe(struct i2c_client *client,
  608. const struct i2c_device_id *id)
  609. {
  610. struct pca953x_platform_data *pdata;
  611. struct pca953x_chip *chip;
  612. int irq_base = 0;
  613. int ret;
  614. u32 invert = 0;
  615. chip = devm_kzalloc(&client->dev,
  616. sizeof(struct pca953x_chip), GFP_KERNEL);
  617. if (chip == NULL)
  618. return -ENOMEM;
  619. pdata = client->dev.platform_data;
  620. if (pdata) {
  621. irq_base = pdata->irq_base;
  622. chip->gpio_start = pdata->gpio_base;
  623. invert = pdata->invert;
  624. chip->names = pdata->names;
  625. } else {
  626. pca953x_get_alt_pdata(client, &chip->gpio_start, &invert);
  627. #ifdef CONFIG_OF_GPIO
  628. /* If I2C node has no interrupts property, disable GPIO interrupts */
  629. if (of_find_property(client->dev.of_node, "interrupts", NULL) == NULL)
  630. irq_base = -1;
  631. #endif
  632. }
  633. chip->client = client;
  634. chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
  635. mutex_init(&chip->i2c_lock);
  636. /* initialize cached registers from their original values.
  637. * we can't share this chip with another i2c master.
  638. */
  639. pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
  640. if (chip->chip_type == PCA953X_TYPE)
  641. ret = device_pca953x_init(chip, invert);
  642. else
  643. ret = device_pca957x_init(chip, invert);
  644. if (ret)
  645. return ret;
  646. ret = pca953x_irq_setup(chip, id, irq_base);
  647. if (ret)
  648. return ret;
  649. ret = gpiochip_add(&chip->gpio_chip);
  650. if (ret)
  651. return ret;
  652. if (pdata && pdata->setup) {
  653. ret = pdata->setup(client, chip->gpio_chip.base,
  654. chip->gpio_chip.ngpio, pdata->context);
  655. if (ret < 0)
  656. dev_warn(&client->dev, "setup failed, %d\n", ret);
  657. }
  658. i2c_set_clientdata(client, chip);
  659. return 0;
  660. }
  661. static int pca953x_remove(struct i2c_client *client)
  662. {
  663. struct pca953x_platform_data *pdata = client->dev.platform_data;
  664. struct pca953x_chip *chip = i2c_get_clientdata(client);
  665. int ret = 0;
  666. if (pdata && pdata->teardown) {
  667. ret = pdata->teardown(client, chip->gpio_chip.base,
  668. chip->gpio_chip.ngpio, pdata->context);
  669. if (ret < 0) {
  670. dev_err(&client->dev, "%s failed, %d\n",
  671. "teardown", ret);
  672. return ret;
  673. }
  674. }
  675. ret = gpiochip_remove(&chip->gpio_chip);
  676. if (ret) {
  677. dev_err(&client->dev, "%s failed, %d\n",
  678. "gpiochip_remove()", ret);
  679. return ret;
  680. }
  681. return 0;
  682. }
  683. static const struct of_device_id pca953x_dt_ids[] = {
  684. { .compatible = "nxp,pca9505", },
  685. { .compatible = "nxp,pca9534", },
  686. { .compatible = "nxp,pca9535", },
  687. { .compatible = "nxp,pca9536", },
  688. { .compatible = "nxp,pca9537", },
  689. { .compatible = "nxp,pca9538", },
  690. { .compatible = "nxp,pca9539", },
  691. { .compatible = "nxp,pca9554", },
  692. { .compatible = "nxp,pca9555", },
  693. { .compatible = "nxp,pca9556", },
  694. { .compatible = "nxp,pca9557", },
  695. { .compatible = "nxp,pca9574", },
  696. { .compatible = "nxp,pca9575", },
  697. { .compatible = "maxim,max7310", },
  698. { .compatible = "maxim,max7312", },
  699. { .compatible = "maxim,max7313", },
  700. { .compatible = "maxim,max7315", },
  701. { .compatible = "ti,pca6107", },
  702. { .compatible = "ti,tca6408", },
  703. { .compatible = "ti,tca6416", },
  704. { .compatible = "ti,tca6424", },
  705. { }
  706. };
  707. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  708. static struct i2c_driver pca953x_driver = {
  709. .driver = {
  710. .name = "pca953x",
  711. .of_match_table = pca953x_dt_ids,
  712. },
  713. .probe = pca953x_probe,
  714. .remove = pca953x_remove,
  715. .id_table = pca953x_id,
  716. };
  717. static int __init pca953x_init(void)
  718. {
  719. return i2c_add_driver(&pca953x_driver);
  720. }
  721. /* register after i2c postcore initcall and before
  722. * subsys initcalls that may rely on these GPIOs
  723. */
  724. subsys_initcall(pca953x_init);
  725. static void __exit pca953x_exit(void)
  726. {
  727. i2c_del_driver(&pca953x_driver);
  728. }
  729. module_exit(pca953x_exit);
  730. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  731. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  732. MODULE_LICENSE("GPL");