edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012-2013 - Mauro Carvalho Chehab <mchehab@redhat.com>
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = strict_strtol(val, 0, &l);
  52. if (ret == -EINVAL || ((int)l != l))
  53. return -EINVAL;
  54. *((int *)kp->arg) = l;
  55. /* notify edac_mc engine to reset the poll period */
  56. edac_mc_reset_delay_period(l);
  57. return 0;
  58. }
  59. /* Parameter declarations for above */
  60. module_param(edac_mc_panic_on_ue, int, 0644);
  61. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  62. module_param(edac_mc_log_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_log_ue,
  64. "Log uncorrectable error to console: 0=off 1=on");
  65. module_param(edac_mc_log_ce, int, 0644);
  66. MODULE_PARM_DESC(edac_mc_log_ce,
  67. "Log correctable error to console: 0=off 1=on");
  68. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  69. &edac_mc_poll_msec, 0644);
  70. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  71. static struct device *mci_pdev;
  72. /*
  73. * various constants for Memory Controllers
  74. */
  75. static const char *mem_types[] = {
  76. [MEM_EMPTY] = "Empty",
  77. [MEM_RESERVED] = "Reserved",
  78. [MEM_UNKNOWN] = "Unknown",
  79. [MEM_FPM] = "FPM",
  80. [MEM_EDO] = "EDO",
  81. [MEM_BEDO] = "BEDO",
  82. [MEM_SDR] = "Unbuffered-SDR",
  83. [MEM_RDR] = "Registered-SDR",
  84. [MEM_DDR] = "Unbuffered-DDR",
  85. [MEM_RDDR] = "Registered-DDR",
  86. [MEM_RMBS] = "RMBS",
  87. [MEM_DDR2] = "Unbuffered-DDR2",
  88. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  89. [MEM_RDDR2] = "Registered-DDR2",
  90. [MEM_XDR] = "XDR",
  91. [MEM_DDR3] = "Unbuffered-DDR3",
  92. [MEM_RDDR3] = "Registered-DDR3"
  93. };
  94. static const char *dev_types[] = {
  95. [DEV_UNKNOWN] = "Unknown",
  96. [DEV_X1] = "x1",
  97. [DEV_X2] = "x2",
  98. [DEV_X4] = "x4",
  99. [DEV_X8] = "x8",
  100. [DEV_X16] = "x16",
  101. [DEV_X32] = "x32",
  102. [DEV_X64] = "x64"
  103. };
  104. static const char *edac_caps[] = {
  105. [EDAC_UNKNOWN] = "Unknown",
  106. [EDAC_NONE] = "None",
  107. [EDAC_RESERVED] = "Reserved",
  108. [EDAC_PARITY] = "PARITY",
  109. [EDAC_EC] = "EC",
  110. [EDAC_SECDED] = "SECDED",
  111. [EDAC_S2ECD2ED] = "S2ECD2ED",
  112. [EDAC_S4ECD4ED] = "S4ECD4ED",
  113. [EDAC_S8ECD8ED] = "S8ECD8ED",
  114. [EDAC_S16ECD16ED] = "S16ECD16ED"
  115. };
  116. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  117. /*
  118. * EDAC sysfs CSROW data structures and methods
  119. */
  120. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  121. /*
  122. * We need it to avoid namespace conflicts between the legacy API
  123. * and the per-dimm/per-rank one
  124. */
  125. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  126. static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  127. struct dev_ch_attribute {
  128. struct device_attribute attr;
  129. int channel;
  130. };
  131. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  132. struct dev_ch_attribute dev_attr_legacy_##_name = \
  133. { __ATTR(_name, _mode, _show, _store), (_var) }
  134. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  135. /* Set of more default csrow<id> attribute show/store functions */
  136. static ssize_t csrow_ue_count_show(struct device *dev,
  137. struct device_attribute *mattr, char *data)
  138. {
  139. struct csrow_info *csrow = to_csrow(dev);
  140. return sprintf(data, "%u\n", csrow->ue_count);
  141. }
  142. static ssize_t csrow_ce_count_show(struct device *dev,
  143. struct device_attribute *mattr, char *data)
  144. {
  145. struct csrow_info *csrow = to_csrow(dev);
  146. return sprintf(data, "%u\n", csrow->ce_count);
  147. }
  148. static ssize_t csrow_size_show(struct device *dev,
  149. struct device_attribute *mattr, char *data)
  150. {
  151. struct csrow_info *csrow = to_csrow(dev);
  152. int i;
  153. u32 nr_pages = 0;
  154. for (i = 0; i < csrow->nr_channels; i++)
  155. nr_pages += csrow->channels[i]->dimm->nr_pages;
  156. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  157. }
  158. static ssize_t csrow_mem_type_show(struct device *dev,
  159. struct device_attribute *mattr, char *data)
  160. {
  161. struct csrow_info *csrow = to_csrow(dev);
  162. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  163. }
  164. static ssize_t csrow_dev_type_show(struct device *dev,
  165. struct device_attribute *mattr, char *data)
  166. {
  167. struct csrow_info *csrow = to_csrow(dev);
  168. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  169. }
  170. static ssize_t csrow_edac_mode_show(struct device *dev,
  171. struct device_attribute *mattr,
  172. char *data)
  173. {
  174. struct csrow_info *csrow = to_csrow(dev);
  175. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  176. }
  177. /* show/store functions for DIMM Label attributes */
  178. static ssize_t channel_dimm_label_show(struct device *dev,
  179. struct device_attribute *mattr,
  180. char *data)
  181. {
  182. struct csrow_info *csrow = to_csrow(dev);
  183. unsigned chan = to_channel(mattr);
  184. struct rank_info *rank = csrow->channels[chan];
  185. /* if field has not been initialized, there is nothing to send */
  186. if (!rank->dimm->label[0])
  187. return 0;
  188. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  189. rank->dimm->label);
  190. }
  191. static ssize_t channel_dimm_label_store(struct device *dev,
  192. struct device_attribute *mattr,
  193. const char *data, size_t count)
  194. {
  195. struct csrow_info *csrow = to_csrow(dev);
  196. unsigned chan = to_channel(mattr);
  197. struct rank_info *rank = csrow->channels[chan];
  198. ssize_t max_size = 0;
  199. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  200. strncpy(rank->dimm->label, data, max_size);
  201. rank->dimm->label[max_size] = '\0';
  202. return max_size;
  203. }
  204. /* show function for dynamic chX_ce_count attribute */
  205. static ssize_t channel_ce_count_show(struct device *dev,
  206. struct device_attribute *mattr, char *data)
  207. {
  208. struct csrow_info *csrow = to_csrow(dev);
  209. unsigned chan = to_channel(mattr);
  210. struct rank_info *rank = csrow->channels[chan];
  211. return sprintf(data, "%u\n", rank->ce_count);
  212. }
  213. /* cwrow<id>/attribute files */
  214. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  215. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  216. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  217. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  218. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  219. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  220. /* default attributes of the CSROW<id> object */
  221. static struct attribute *csrow_attrs[] = {
  222. &dev_attr_legacy_dev_type.attr,
  223. &dev_attr_legacy_mem_type.attr,
  224. &dev_attr_legacy_edac_mode.attr,
  225. &dev_attr_legacy_size_mb.attr,
  226. &dev_attr_legacy_ue_count.attr,
  227. &dev_attr_legacy_ce_count.attr,
  228. NULL,
  229. };
  230. static struct attribute_group csrow_attr_grp = {
  231. .attrs = csrow_attrs,
  232. };
  233. static const struct attribute_group *csrow_attr_groups[] = {
  234. &csrow_attr_grp,
  235. NULL
  236. };
  237. static void csrow_attr_release(struct device *dev)
  238. {
  239. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  240. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  241. kfree(csrow);
  242. }
  243. static struct device_type csrow_attr_type = {
  244. .groups = csrow_attr_groups,
  245. .release = csrow_attr_release,
  246. };
  247. /*
  248. * possible dynamic channel DIMM Label attribute files
  249. *
  250. */
  251. #define EDAC_NR_CHANNELS 6
  252. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  253. channel_dimm_label_show, channel_dimm_label_store, 0);
  254. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  255. channel_dimm_label_show, channel_dimm_label_store, 1);
  256. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 2);
  258. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 3);
  260. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 4);
  262. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 5);
  264. /* Total possible dynamic DIMM Label attribute file table */
  265. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  266. &dev_attr_legacy_ch0_dimm_label.attr,
  267. &dev_attr_legacy_ch1_dimm_label.attr,
  268. &dev_attr_legacy_ch2_dimm_label.attr,
  269. &dev_attr_legacy_ch3_dimm_label.attr,
  270. &dev_attr_legacy_ch4_dimm_label.attr,
  271. &dev_attr_legacy_ch5_dimm_label.attr
  272. };
  273. /* possible dynamic channel ce_count attribute files */
  274. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
  275. channel_ce_count_show, NULL, 0);
  276. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
  277. channel_ce_count_show, NULL, 1);
  278. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
  279. channel_ce_count_show, NULL, 2);
  280. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
  281. channel_ce_count_show, NULL, 3);
  282. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
  283. channel_ce_count_show, NULL, 4);
  284. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
  285. channel_ce_count_show, NULL, 5);
  286. /* Total possible dynamic ce_count attribute file table */
  287. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  288. &dev_attr_legacy_ch0_ce_count.attr,
  289. &dev_attr_legacy_ch1_ce_count.attr,
  290. &dev_attr_legacy_ch2_ce_count.attr,
  291. &dev_attr_legacy_ch3_ce_count.attr,
  292. &dev_attr_legacy_ch4_ce_count.attr,
  293. &dev_attr_legacy_ch5_ce_count.attr
  294. };
  295. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  296. {
  297. int chan, nr_pages = 0;
  298. for (chan = 0; chan < csrow->nr_channels; chan++)
  299. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  300. return nr_pages;
  301. }
  302. /* Create a CSROW object under specifed edac_mc_device */
  303. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  304. struct csrow_info *csrow, int index)
  305. {
  306. int err, chan;
  307. if (csrow->nr_channels >= EDAC_NR_CHANNELS)
  308. return -ENODEV;
  309. csrow->dev.type = &csrow_attr_type;
  310. csrow->dev.bus = &mci->bus;
  311. device_initialize(&csrow->dev);
  312. csrow->dev.parent = &mci->dev;
  313. csrow->mci = mci;
  314. dev_set_name(&csrow->dev, "csrow%d", index);
  315. dev_set_drvdata(&csrow->dev, csrow);
  316. edac_dbg(0, "creating (virtual) csrow node %s\n",
  317. dev_name(&csrow->dev));
  318. err = device_add(&csrow->dev);
  319. if (err < 0)
  320. return err;
  321. for (chan = 0; chan < csrow->nr_channels; chan++) {
  322. /* Only expose populated DIMMs */
  323. if (!csrow->channels[chan]->dimm->nr_pages)
  324. continue;
  325. err = device_create_file(&csrow->dev,
  326. dynamic_csrow_dimm_attr[chan]);
  327. if (err < 0)
  328. goto error;
  329. err = device_create_file(&csrow->dev,
  330. dynamic_csrow_ce_count_attr[chan]);
  331. if (err < 0) {
  332. device_remove_file(&csrow->dev,
  333. dynamic_csrow_dimm_attr[chan]);
  334. goto error;
  335. }
  336. }
  337. return 0;
  338. error:
  339. for (--chan; chan >= 0; chan--) {
  340. device_remove_file(&csrow->dev,
  341. dynamic_csrow_dimm_attr[chan]);
  342. device_remove_file(&csrow->dev,
  343. dynamic_csrow_ce_count_attr[chan]);
  344. }
  345. put_device(&csrow->dev);
  346. return err;
  347. }
  348. /* Create a CSROW object under specifed edac_mc_device */
  349. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  350. {
  351. int err, i, chan;
  352. struct csrow_info *csrow;
  353. for (i = 0; i < mci->nr_csrows; i++) {
  354. csrow = mci->csrows[i];
  355. if (!nr_pages_per_csrow(csrow))
  356. continue;
  357. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  358. if (err < 0) {
  359. edac_dbg(1,
  360. "failure: create csrow objects for csrow %d\n",
  361. i);
  362. goto error;
  363. }
  364. }
  365. return 0;
  366. error:
  367. for (--i; i >= 0; i--) {
  368. csrow = mci->csrows[i];
  369. if (!nr_pages_per_csrow(csrow))
  370. continue;
  371. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  372. if (!csrow->channels[chan]->dimm->nr_pages)
  373. continue;
  374. device_remove_file(&csrow->dev,
  375. dynamic_csrow_dimm_attr[chan]);
  376. device_remove_file(&csrow->dev,
  377. dynamic_csrow_ce_count_attr[chan]);
  378. }
  379. put_device(&mci->csrows[i]->dev);
  380. }
  381. return err;
  382. }
  383. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  384. {
  385. int i, chan;
  386. struct csrow_info *csrow;
  387. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  388. csrow = mci->csrows[i];
  389. if (!nr_pages_per_csrow(csrow))
  390. continue;
  391. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  392. if (!csrow->channels[chan]->dimm->nr_pages)
  393. continue;
  394. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  395. i, chan);
  396. device_remove_file(&csrow->dev,
  397. dynamic_csrow_dimm_attr[chan]);
  398. device_remove_file(&csrow->dev,
  399. dynamic_csrow_ce_count_attr[chan]);
  400. }
  401. device_unregister(&mci->csrows[i]->dev);
  402. }
  403. }
  404. #endif
  405. /*
  406. * Per-dimm (or per-rank) devices
  407. */
  408. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  409. /* show/store functions for DIMM Label attributes */
  410. static ssize_t dimmdev_location_show(struct device *dev,
  411. struct device_attribute *mattr, char *data)
  412. {
  413. struct dimm_info *dimm = to_dimm(dev);
  414. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  415. }
  416. static ssize_t dimmdev_label_show(struct device *dev,
  417. struct device_attribute *mattr, char *data)
  418. {
  419. struct dimm_info *dimm = to_dimm(dev);
  420. /* if field has not been initialized, there is nothing to send */
  421. if (!dimm->label[0])
  422. return 0;
  423. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  424. }
  425. static ssize_t dimmdev_label_store(struct device *dev,
  426. struct device_attribute *mattr,
  427. const char *data,
  428. size_t count)
  429. {
  430. struct dimm_info *dimm = to_dimm(dev);
  431. ssize_t max_size = 0;
  432. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  433. strncpy(dimm->label, data, max_size);
  434. dimm->label[max_size] = '\0';
  435. return max_size;
  436. }
  437. static ssize_t dimmdev_size_show(struct device *dev,
  438. struct device_attribute *mattr, char *data)
  439. {
  440. struct dimm_info *dimm = to_dimm(dev);
  441. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  442. }
  443. static ssize_t dimmdev_mem_type_show(struct device *dev,
  444. struct device_attribute *mattr, char *data)
  445. {
  446. struct dimm_info *dimm = to_dimm(dev);
  447. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  448. }
  449. static ssize_t dimmdev_dev_type_show(struct device *dev,
  450. struct device_attribute *mattr, char *data)
  451. {
  452. struct dimm_info *dimm = to_dimm(dev);
  453. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  454. }
  455. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  456. struct device_attribute *mattr,
  457. char *data)
  458. {
  459. struct dimm_info *dimm = to_dimm(dev);
  460. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  461. }
  462. /* dimm/rank attribute files */
  463. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  464. dimmdev_label_show, dimmdev_label_store);
  465. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  466. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  467. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  468. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  469. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  470. /* attributes of the dimm<id>/rank<id> object */
  471. static struct attribute *dimm_attrs[] = {
  472. &dev_attr_dimm_label.attr,
  473. &dev_attr_dimm_location.attr,
  474. &dev_attr_size.attr,
  475. &dev_attr_dimm_mem_type.attr,
  476. &dev_attr_dimm_dev_type.attr,
  477. &dev_attr_dimm_edac_mode.attr,
  478. NULL,
  479. };
  480. static struct attribute_group dimm_attr_grp = {
  481. .attrs = dimm_attrs,
  482. };
  483. static const struct attribute_group *dimm_attr_groups[] = {
  484. &dimm_attr_grp,
  485. NULL
  486. };
  487. static void dimm_attr_release(struct device *dev)
  488. {
  489. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  490. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  491. kfree(dimm);
  492. }
  493. static struct device_type dimm_attr_type = {
  494. .groups = dimm_attr_groups,
  495. .release = dimm_attr_release,
  496. };
  497. /* Create a DIMM object under specifed memory controller device */
  498. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  499. struct dimm_info *dimm,
  500. int index)
  501. {
  502. int err;
  503. dimm->mci = mci;
  504. dimm->dev.type = &dimm_attr_type;
  505. dimm->dev.bus = &mci->bus;
  506. device_initialize(&dimm->dev);
  507. dimm->dev.parent = &mci->dev;
  508. if (mci->csbased)
  509. dev_set_name(&dimm->dev, "rank%d", index);
  510. else
  511. dev_set_name(&dimm->dev, "dimm%d", index);
  512. dev_set_drvdata(&dimm->dev, dimm);
  513. pm_runtime_forbid(&mci->dev);
  514. err = device_add(&dimm->dev);
  515. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  516. return err;
  517. }
  518. /*
  519. * Memory controller device
  520. */
  521. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  522. static ssize_t mci_reset_counters_store(struct device *dev,
  523. struct device_attribute *mattr,
  524. const char *data, size_t count)
  525. {
  526. struct mem_ctl_info *mci = to_mci(dev);
  527. int cnt, row, chan, i;
  528. mci->ue_mc = 0;
  529. mci->ce_mc = 0;
  530. mci->ue_noinfo_count = 0;
  531. mci->ce_noinfo_count = 0;
  532. for (row = 0; row < mci->nr_csrows; row++) {
  533. struct csrow_info *ri = mci->csrows[row];
  534. ri->ue_count = 0;
  535. ri->ce_count = 0;
  536. for (chan = 0; chan < ri->nr_channels; chan++)
  537. ri->channels[chan]->ce_count = 0;
  538. }
  539. cnt = 1;
  540. for (i = 0; i < mci->n_layers; i++) {
  541. cnt *= mci->layers[i].size;
  542. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  543. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  544. }
  545. mci->start_time = jiffies;
  546. return count;
  547. }
  548. /* Memory scrubbing interface:
  549. *
  550. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  551. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  552. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  553. *
  554. * Negative value still means that an error has occurred while setting
  555. * the scrub rate.
  556. */
  557. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  558. struct device_attribute *mattr,
  559. const char *data, size_t count)
  560. {
  561. struct mem_ctl_info *mci = to_mci(dev);
  562. unsigned long bandwidth = 0;
  563. int new_bw = 0;
  564. if (strict_strtoul(data, 10, &bandwidth) < 0)
  565. return -EINVAL;
  566. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  567. if (new_bw < 0) {
  568. edac_printk(KERN_WARNING, EDAC_MC,
  569. "Error setting scrub rate to: %lu\n", bandwidth);
  570. return -EINVAL;
  571. }
  572. return count;
  573. }
  574. /*
  575. * ->get_sdram_scrub_rate() return value semantics same as above.
  576. */
  577. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  578. struct device_attribute *mattr,
  579. char *data)
  580. {
  581. struct mem_ctl_info *mci = to_mci(dev);
  582. int bandwidth = 0;
  583. bandwidth = mci->get_sdram_scrub_rate(mci);
  584. if (bandwidth < 0) {
  585. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  586. return bandwidth;
  587. }
  588. return sprintf(data, "%d\n", bandwidth);
  589. }
  590. /* default attribute files for the MCI object */
  591. static ssize_t mci_ue_count_show(struct device *dev,
  592. struct device_attribute *mattr,
  593. char *data)
  594. {
  595. struct mem_ctl_info *mci = to_mci(dev);
  596. return sprintf(data, "%d\n", mci->ue_mc);
  597. }
  598. static ssize_t mci_ce_count_show(struct device *dev,
  599. struct device_attribute *mattr,
  600. char *data)
  601. {
  602. struct mem_ctl_info *mci = to_mci(dev);
  603. return sprintf(data, "%d\n", mci->ce_mc);
  604. }
  605. static ssize_t mci_ce_noinfo_show(struct device *dev,
  606. struct device_attribute *mattr,
  607. char *data)
  608. {
  609. struct mem_ctl_info *mci = to_mci(dev);
  610. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  611. }
  612. static ssize_t mci_ue_noinfo_show(struct device *dev,
  613. struct device_attribute *mattr,
  614. char *data)
  615. {
  616. struct mem_ctl_info *mci = to_mci(dev);
  617. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  618. }
  619. static ssize_t mci_seconds_show(struct device *dev,
  620. struct device_attribute *mattr,
  621. char *data)
  622. {
  623. struct mem_ctl_info *mci = to_mci(dev);
  624. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  625. }
  626. static ssize_t mci_ctl_name_show(struct device *dev,
  627. struct device_attribute *mattr,
  628. char *data)
  629. {
  630. struct mem_ctl_info *mci = to_mci(dev);
  631. return sprintf(data, "%s\n", mci->ctl_name);
  632. }
  633. static ssize_t mci_size_mb_show(struct device *dev,
  634. struct device_attribute *mattr,
  635. char *data)
  636. {
  637. struct mem_ctl_info *mci = to_mci(dev);
  638. int total_pages = 0, csrow_idx, j;
  639. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  640. struct csrow_info *csrow = mci->csrows[csrow_idx];
  641. for (j = 0; j < csrow->nr_channels; j++) {
  642. struct dimm_info *dimm = csrow->channels[j]->dimm;
  643. total_pages += dimm->nr_pages;
  644. }
  645. }
  646. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  647. }
  648. static ssize_t mci_max_location_show(struct device *dev,
  649. struct device_attribute *mattr,
  650. char *data)
  651. {
  652. struct mem_ctl_info *mci = to_mci(dev);
  653. int i;
  654. char *p = data;
  655. for (i = 0; i < mci->n_layers; i++) {
  656. p += sprintf(p, "%s %d ",
  657. edac_layer_name[mci->layers[i].type],
  658. mci->layers[i].size - 1);
  659. }
  660. return p - data;
  661. }
  662. #ifdef CONFIG_EDAC_DEBUG
  663. static ssize_t edac_fake_inject_write(struct file *file,
  664. const char __user *data,
  665. size_t count, loff_t *ppos)
  666. {
  667. struct device *dev = file->private_data;
  668. struct mem_ctl_info *mci = to_mci(dev);
  669. static enum hw_event_mc_err_type type;
  670. u16 errcount = mci->fake_inject_count;
  671. if (!errcount)
  672. errcount = 1;
  673. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  674. : HW_EVENT_ERR_CORRECTED;
  675. printk(KERN_DEBUG
  676. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  677. errcount,
  678. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  679. errcount > 1 ? "s" : "",
  680. mci->fake_inject_layer[0],
  681. mci->fake_inject_layer[1],
  682. mci->fake_inject_layer[2]
  683. );
  684. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  685. mci->fake_inject_layer[0],
  686. mci->fake_inject_layer[1],
  687. mci->fake_inject_layer[2],
  688. "FAKE ERROR", "for EDAC testing only");
  689. return count;
  690. }
  691. static const struct file_operations debug_fake_inject_fops = {
  692. .open = simple_open,
  693. .write = edac_fake_inject_write,
  694. .llseek = generic_file_llseek,
  695. };
  696. #endif
  697. /* default Control file */
  698. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  699. /* default Attribute files */
  700. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  701. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  702. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  703. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  704. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  705. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  706. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  707. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  708. /* memory scrubber attribute file */
  709. DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
  710. static struct attribute *mci_attrs[] = {
  711. &dev_attr_reset_counters.attr,
  712. &dev_attr_mc_name.attr,
  713. &dev_attr_size_mb.attr,
  714. &dev_attr_seconds_since_reset.attr,
  715. &dev_attr_ue_noinfo_count.attr,
  716. &dev_attr_ce_noinfo_count.attr,
  717. &dev_attr_ue_count.attr,
  718. &dev_attr_ce_count.attr,
  719. &dev_attr_max_location.attr,
  720. NULL
  721. };
  722. static struct attribute_group mci_attr_grp = {
  723. .attrs = mci_attrs,
  724. };
  725. static const struct attribute_group *mci_attr_groups[] = {
  726. &mci_attr_grp,
  727. NULL
  728. };
  729. static void mci_attr_release(struct device *dev)
  730. {
  731. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  732. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  733. kfree(mci);
  734. }
  735. static struct device_type mci_attr_type = {
  736. .groups = mci_attr_groups,
  737. .release = mci_attr_release,
  738. };
  739. #ifdef CONFIG_EDAC_DEBUG
  740. static struct dentry *edac_debugfs;
  741. int __init edac_debugfs_init(void)
  742. {
  743. edac_debugfs = debugfs_create_dir("edac", NULL);
  744. if (IS_ERR(edac_debugfs)) {
  745. edac_debugfs = NULL;
  746. return -ENOMEM;
  747. }
  748. return 0;
  749. }
  750. void __exit edac_debugfs_exit(void)
  751. {
  752. debugfs_remove(edac_debugfs);
  753. }
  754. int edac_create_debug_nodes(struct mem_ctl_info *mci)
  755. {
  756. struct dentry *d, *parent;
  757. char name[80];
  758. int i;
  759. if (!edac_debugfs)
  760. return -ENODEV;
  761. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  762. if (!d)
  763. return -ENOMEM;
  764. parent = d;
  765. for (i = 0; i < mci->n_layers; i++) {
  766. sprintf(name, "fake_inject_%s",
  767. edac_layer_name[mci->layers[i].type]);
  768. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  769. &mci->fake_inject_layer[i]);
  770. if (!d)
  771. goto nomem;
  772. }
  773. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  774. &mci->fake_inject_ue);
  775. if (!d)
  776. goto nomem;
  777. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  778. &mci->fake_inject_count);
  779. if (!d)
  780. goto nomem;
  781. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  782. &mci->dev,
  783. &debug_fake_inject_fops);
  784. if (!d)
  785. goto nomem;
  786. mci->debugfs = parent;
  787. return 0;
  788. nomem:
  789. debugfs_remove(mci->debugfs);
  790. return -ENOMEM;
  791. }
  792. #endif
  793. /*
  794. * Create a new Memory Controller kobject instance,
  795. * mc<id> under the 'mc' directory
  796. *
  797. * Return:
  798. * 0 Success
  799. * !0 Failure
  800. */
  801. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  802. {
  803. int i, err;
  804. /*
  805. * The memory controller needs its own bus, in order to avoid
  806. * namespace conflicts at /sys/bus/edac.
  807. */
  808. mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  809. if (!mci->bus.name)
  810. return -ENOMEM;
  811. edac_dbg(0, "creating bus %s\n", mci->bus.name);
  812. err = bus_register(&mci->bus);
  813. if (err < 0)
  814. return err;
  815. /* get the /sys/devices/system/edac subsys reference */
  816. mci->dev.type = &mci_attr_type;
  817. device_initialize(&mci->dev);
  818. mci->dev.parent = mci_pdev;
  819. mci->dev.bus = &mci->bus;
  820. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  821. dev_set_drvdata(&mci->dev, mci);
  822. pm_runtime_forbid(&mci->dev);
  823. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  824. err = device_add(&mci->dev);
  825. if (err < 0) {
  826. edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
  827. bus_unregister(&mci->bus);
  828. kfree(mci->bus.name);
  829. return err;
  830. }
  831. if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
  832. if (mci->get_sdram_scrub_rate) {
  833. dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
  834. dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
  835. }
  836. if (mci->set_sdram_scrub_rate) {
  837. dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
  838. dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
  839. }
  840. err = device_create_file(&mci->dev,
  841. &dev_attr_sdram_scrub_rate);
  842. if (err) {
  843. edac_dbg(1, "failure: create sdram_scrub_rate\n");
  844. goto fail2;
  845. }
  846. }
  847. /*
  848. * Create the dimm/rank devices
  849. */
  850. for (i = 0; i < mci->tot_dimms; i++) {
  851. struct dimm_info *dimm = mci->dimms[i];
  852. /* Only expose populated DIMMs */
  853. if (dimm->nr_pages == 0)
  854. continue;
  855. #ifdef CONFIG_EDAC_DEBUG
  856. edac_dbg(1, "creating dimm%d, located at ", i);
  857. if (edac_debug_level >= 1) {
  858. int lay;
  859. for (lay = 0; lay < mci->n_layers; lay++)
  860. printk(KERN_CONT "%s %d ",
  861. edac_layer_name[mci->layers[lay].type],
  862. dimm->location[lay]);
  863. printk(KERN_CONT "\n");
  864. }
  865. #endif
  866. err = edac_create_dimm_object(mci, dimm, i);
  867. if (err) {
  868. edac_dbg(1, "failure: create dimm %d obj\n", i);
  869. goto fail;
  870. }
  871. }
  872. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  873. err = edac_create_csrow_objects(mci);
  874. if (err < 0)
  875. goto fail;
  876. #endif
  877. #ifdef CONFIG_EDAC_DEBUG
  878. edac_create_debug_nodes(mci);
  879. #endif
  880. return 0;
  881. fail:
  882. for (i--; i >= 0; i--) {
  883. struct dimm_info *dimm = mci->dimms[i];
  884. if (dimm->nr_pages == 0)
  885. continue;
  886. device_unregister(&dimm->dev);
  887. }
  888. fail2:
  889. device_unregister(&mci->dev);
  890. bus_unregister(&mci->bus);
  891. kfree(mci->bus.name);
  892. return err;
  893. }
  894. /*
  895. * remove a Memory Controller instance
  896. */
  897. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  898. {
  899. int i;
  900. edac_dbg(0, "\n");
  901. #ifdef CONFIG_EDAC_DEBUG
  902. debugfs_remove(mci->debugfs);
  903. #endif
  904. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  905. edac_delete_csrow_objects(mci);
  906. #endif
  907. for (i = 0; i < mci->tot_dimms; i++) {
  908. struct dimm_info *dimm = mci->dimms[i];
  909. if (dimm->nr_pages == 0)
  910. continue;
  911. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  912. device_unregister(&dimm->dev);
  913. }
  914. }
  915. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  916. {
  917. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  918. device_unregister(&mci->dev);
  919. bus_unregister(&mci->bus);
  920. kfree(mci->bus.name);
  921. }
  922. static void mc_attr_release(struct device *dev)
  923. {
  924. /*
  925. * There's no container structure here, as this is just the mci
  926. * parent device, used to create the /sys/devices/mc sysfs node.
  927. * So, there are no attributes on it.
  928. */
  929. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  930. kfree(dev);
  931. }
  932. static struct device_type mc_attr_type = {
  933. .release = mc_attr_release,
  934. };
  935. /*
  936. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  937. */
  938. int __init edac_mc_sysfs_init(void)
  939. {
  940. struct bus_type *edac_subsys;
  941. int err;
  942. /* get the /sys/devices/system/edac subsys reference */
  943. edac_subsys = edac_get_sysfs_subsys();
  944. if (edac_subsys == NULL) {
  945. edac_dbg(1, "no edac_subsys\n");
  946. err = -EINVAL;
  947. goto out;
  948. }
  949. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  950. if (!mci_pdev) {
  951. err = -ENOMEM;
  952. goto out_put_sysfs;
  953. }
  954. mci_pdev->bus = edac_subsys;
  955. mci_pdev->type = &mc_attr_type;
  956. device_initialize(mci_pdev);
  957. dev_set_name(mci_pdev, "mc");
  958. err = device_add(mci_pdev);
  959. if (err < 0)
  960. goto out_dev_free;
  961. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  962. return 0;
  963. out_dev_free:
  964. kfree(mci_pdev);
  965. out_put_sysfs:
  966. edac_put_sysfs_subsys();
  967. out:
  968. return err;
  969. }
  970. void __exit edac_mc_sysfs_exit(void)
  971. {
  972. device_unregister(mci_pdev);
  973. edac_put_sysfs_subsys();
  974. }