shdma-base.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940
  1. /*
  2. * Dmaengine driver base library for DMA controllers, found on SH-based SoCs
  3. *
  4. * extracted from shdma.c
  5. *
  6. * Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  7. * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  8. * Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
  9. * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
  10. *
  11. * This is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/shdma-base.h>
  17. #include <linux/dmaengine.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/module.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #include "../dmaengine.h"
  25. /* DMA descriptor control */
  26. enum shdma_desc_status {
  27. DESC_IDLE,
  28. DESC_PREPARED,
  29. DESC_SUBMITTED,
  30. DESC_COMPLETED, /* completed, have to call callback */
  31. DESC_WAITING, /* callback called, waiting for ack / re-submit */
  32. };
  33. #define NR_DESCS_PER_CHANNEL 32
  34. #define to_shdma_chan(c) container_of(c, struct shdma_chan, dma_chan)
  35. #define to_shdma_dev(d) container_of(d, struct shdma_dev, dma_dev)
  36. /*
  37. * For slave DMA we assume, that there is a finite number of DMA slaves in the
  38. * system, and that each such slave can only use a finite number of channels.
  39. * We use slave channel IDs to make sure, that no such slave channel ID is
  40. * allocated more than once.
  41. */
  42. static unsigned int slave_num = 256;
  43. module_param(slave_num, uint, 0444);
  44. /* A bitmask with slave_num bits */
  45. static unsigned long *shdma_slave_used;
  46. /* Called under spin_lock_irq(&schan->chan_lock") */
  47. static void shdma_chan_xfer_ld_queue(struct shdma_chan *schan)
  48. {
  49. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  50. const struct shdma_ops *ops = sdev->ops;
  51. struct shdma_desc *sdesc;
  52. /* DMA work check */
  53. if (ops->channel_busy(schan))
  54. return;
  55. /* Find the first not transferred descriptor */
  56. list_for_each_entry(sdesc, &schan->ld_queue, node)
  57. if (sdesc->mark == DESC_SUBMITTED) {
  58. ops->start_xfer(schan, sdesc);
  59. break;
  60. }
  61. }
  62. static dma_cookie_t shdma_tx_submit(struct dma_async_tx_descriptor *tx)
  63. {
  64. struct shdma_desc *chunk, *c, *desc =
  65. container_of(tx, struct shdma_desc, async_tx),
  66. *last = desc;
  67. struct shdma_chan *schan = to_shdma_chan(tx->chan);
  68. dma_async_tx_callback callback = tx->callback;
  69. dma_cookie_t cookie;
  70. bool power_up;
  71. spin_lock_irq(&schan->chan_lock);
  72. power_up = list_empty(&schan->ld_queue);
  73. cookie = dma_cookie_assign(tx);
  74. /* Mark all chunks of this descriptor as submitted, move to the queue */
  75. list_for_each_entry_safe(chunk, c, desc->node.prev, node) {
  76. /*
  77. * All chunks are on the global ld_free, so, we have to find
  78. * the end of the chain ourselves
  79. */
  80. if (chunk != desc && (chunk->mark == DESC_IDLE ||
  81. chunk->async_tx.cookie > 0 ||
  82. chunk->async_tx.cookie == -EBUSY ||
  83. &chunk->node == &schan->ld_free))
  84. break;
  85. chunk->mark = DESC_SUBMITTED;
  86. /* Callback goes to the last chunk */
  87. chunk->async_tx.callback = NULL;
  88. chunk->cookie = cookie;
  89. list_move_tail(&chunk->node, &schan->ld_queue);
  90. last = chunk;
  91. dev_dbg(schan->dev, "submit #%d@%p on %d\n",
  92. tx->cookie, &last->async_tx, schan->id);
  93. }
  94. last->async_tx.callback = callback;
  95. last->async_tx.callback_param = tx->callback_param;
  96. if (power_up) {
  97. int ret;
  98. schan->pm_state = SHDMA_PM_BUSY;
  99. ret = pm_runtime_get(schan->dev);
  100. spin_unlock_irq(&schan->chan_lock);
  101. if (ret < 0)
  102. dev_err(schan->dev, "%s(): GET = %d\n", __func__, ret);
  103. pm_runtime_barrier(schan->dev);
  104. spin_lock_irq(&schan->chan_lock);
  105. /* Have we been reset, while waiting? */
  106. if (schan->pm_state != SHDMA_PM_ESTABLISHED) {
  107. struct shdma_dev *sdev =
  108. to_shdma_dev(schan->dma_chan.device);
  109. const struct shdma_ops *ops = sdev->ops;
  110. dev_dbg(schan->dev, "Bring up channel %d\n",
  111. schan->id);
  112. /*
  113. * TODO: .xfer_setup() might fail on some platforms.
  114. * Make it int then, on error remove chunks from the
  115. * queue again
  116. */
  117. ops->setup_xfer(schan, schan->slave_id);
  118. if (schan->pm_state == SHDMA_PM_PENDING)
  119. shdma_chan_xfer_ld_queue(schan);
  120. schan->pm_state = SHDMA_PM_ESTABLISHED;
  121. }
  122. } else {
  123. /*
  124. * Tell .device_issue_pending() not to run the queue, interrupts
  125. * will do it anyway
  126. */
  127. schan->pm_state = SHDMA_PM_PENDING;
  128. }
  129. spin_unlock_irq(&schan->chan_lock);
  130. return cookie;
  131. }
  132. /* Called with desc_lock held */
  133. static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan)
  134. {
  135. struct shdma_desc *sdesc;
  136. list_for_each_entry(sdesc, &schan->ld_free, node)
  137. if (sdesc->mark != DESC_PREPARED) {
  138. BUG_ON(sdesc->mark != DESC_IDLE);
  139. list_del(&sdesc->node);
  140. return sdesc;
  141. }
  142. return NULL;
  143. }
  144. static int shdma_setup_slave(struct shdma_chan *schan, int slave_id)
  145. {
  146. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  147. const struct shdma_ops *ops = sdev->ops;
  148. int ret;
  149. if (slave_id < 0 || slave_id >= slave_num)
  150. return -EINVAL;
  151. if (test_and_set_bit(slave_id, shdma_slave_used))
  152. return -EBUSY;
  153. ret = ops->set_slave(schan, slave_id, false);
  154. if (ret < 0) {
  155. clear_bit(slave_id, shdma_slave_used);
  156. return ret;
  157. }
  158. schan->slave_id = slave_id;
  159. return 0;
  160. }
  161. /*
  162. * This is the standard shdma filter function to be used as a replacement to the
  163. * "old" method, using the .private pointer. If for some reason you allocate a
  164. * channel without slave data, use something like ERR_PTR(-EINVAL) as a filter
  165. * parameter. If this filter is used, the slave driver, after calling
  166. * dma_request_channel(), will also have to call dmaengine_slave_config() with
  167. * .slave_id, .direction, and either .src_addr or .dst_addr set.
  168. * NOTE: this filter doesn't support multiple DMAC drivers with the DMA_SLAVE
  169. * capability! If this becomes a requirement, hardware glue drivers, using this
  170. * services would have to provide their own filters, which first would check
  171. * the device driver, similar to how other DMAC drivers, e.g., sa11x0-dma.c, do
  172. * this, and only then, in case of a match, call this common filter.
  173. */
  174. bool shdma_chan_filter(struct dma_chan *chan, void *arg)
  175. {
  176. struct shdma_chan *schan = to_shdma_chan(chan);
  177. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  178. const struct shdma_ops *ops = sdev->ops;
  179. int slave_id = (int)arg;
  180. int ret;
  181. if (slave_id < 0)
  182. /* No slave requested - arbitrary channel */
  183. return true;
  184. if (slave_id >= slave_num)
  185. return false;
  186. ret = ops->set_slave(schan, slave_id, true);
  187. if (ret < 0)
  188. return false;
  189. return true;
  190. }
  191. EXPORT_SYMBOL(shdma_chan_filter);
  192. static int shdma_alloc_chan_resources(struct dma_chan *chan)
  193. {
  194. struct shdma_chan *schan = to_shdma_chan(chan);
  195. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  196. const struct shdma_ops *ops = sdev->ops;
  197. struct shdma_desc *desc;
  198. struct shdma_slave *slave = chan->private;
  199. int ret, i;
  200. /*
  201. * This relies on the guarantee from dmaengine that alloc_chan_resources
  202. * never runs concurrently with itself or free_chan_resources.
  203. */
  204. if (slave) {
  205. /* Legacy mode: .private is set in filter */
  206. ret = shdma_setup_slave(schan, slave->slave_id);
  207. if (ret < 0)
  208. goto esetslave;
  209. } else {
  210. schan->slave_id = -EINVAL;
  211. }
  212. schan->desc = kcalloc(NR_DESCS_PER_CHANNEL,
  213. sdev->desc_size, GFP_KERNEL);
  214. if (!schan->desc) {
  215. ret = -ENOMEM;
  216. goto edescalloc;
  217. }
  218. schan->desc_num = NR_DESCS_PER_CHANNEL;
  219. for (i = 0; i < NR_DESCS_PER_CHANNEL; i++) {
  220. desc = ops->embedded_desc(schan->desc, i);
  221. dma_async_tx_descriptor_init(&desc->async_tx,
  222. &schan->dma_chan);
  223. desc->async_tx.tx_submit = shdma_tx_submit;
  224. desc->mark = DESC_IDLE;
  225. list_add(&desc->node, &schan->ld_free);
  226. }
  227. return NR_DESCS_PER_CHANNEL;
  228. edescalloc:
  229. if (slave)
  230. esetslave:
  231. clear_bit(slave->slave_id, shdma_slave_used);
  232. chan->private = NULL;
  233. return ret;
  234. }
  235. static dma_async_tx_callback __ld_cleanup(struct shdma_chan *schan, bool all)
  236. {
  237. struct shdma_desc *desc, *_desc;
  238. /* Is the "exposed" head of a chain acked? */
  239. bool head_acked = false;
  240. dma_cookie_t cookie = 0;
  241. dma_async_tx_callback callback = NULL;
  242. void *param = NULL;
  243. unsigned long flags;
  244. spin_lock_irqsave(&schan->chan_lock, flags);
  245. list_for_each_entry_safe(desc, _desc, &schan->ld_queue, node) {
  246. struct dma_async_tx_descriptor *tx = &desc->async_tx;
  247. BUG_ON(tx->cookie > 0 && tx->cookie != desc->cookie);
  248. BUG_ON(desc->mark != DESC_SUBMITTED &&
  249. desc->mark != DESC_COMPLETED &&
  250. desc->mark != DESC_WAITING);
  251. /*
  252. * queue is ordered, and we use this loop to (1) clean up all
  253. * completed descriptors, and to (2) update descriptor flags of
  254. * any chunks in a (partially) completed chain
  255. */
  256. if (!all && desc->mark == DESC_SUBMITTED &&
  257. desc->cookie != cookie)
  258. break;
  259. if (tx->cookie > 0)
  260. cookie = tx->cookie;
  261. if (desc->mark == DESC_COMPLETED && desc->chunks == 1) {
  262. if (schan->dma_chan.completed_cookie != desc->cookie - 1)
  263. dev_dbg(schan->dev,
  264. "Completing cookie %d, expected %d\n",
  265. desc->cookie,
  266. schan->dma_chan.completed_cookie + 1);
  267. schan->dma_chan.completed_cookie = desc->cookie;
  268. }
  269. /* Call callback on the last chunk */
  270. if (desc->mark == DESC_COMPLETED && tx->callback) {
  271. desc->mark = DESC_WAITING;
  272. callback = tx->callback;
  273. param = tx->callback_param;
  274. dev_dbg(schan->dev, "descriptor #%d@%p on %d callback\n",
  275. tx->cookie, tx, schan->id);
  276. BUG_ON(desc->chunks != 1);
  277. break;
  278. }
  279. if (tx->cookie > 0 || tx->cookie == -EBUSY) {
  280. if (desc->mark == DESC_COMPLETED) {
  281. BUG_ON(tx->cookie < 0);
  282. desc->mark = DESC_WAITING;
  283. }
  284. head_acked = async_tx_test_ack(tx);
  285. } else {
  286. switch (desc->mark) {
  287. case DESC_COMPLETED:
  288. desc->mark = DESC_WAITING;
  289. /* Fall through */
  290. case DESC_WAITING:
  291. if (head_acked)
  292. async_tx_ack(&desc->async_tx);
  293. }
  294. }
  295. dev_dbg(schan->dev, "descriptor %p #%d completed.\n",
  296. tx, tx->cookie);
  297. if (((desc->mark == DESC_COMPLETED ||
  298. desc->mark == DESC_WAITING) &&
  299. async_tx_test_ack(&desc->async_tx)) || all) {
  300. /* Remove from ld_queue list */
  301. desc->mark = DESC_IDLE;
  302. list_move(&desc->node, &schan->ld_free);
  303. if (list_empty(&schan->ld_queue)) {
  304. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  305. pm_runtime_put(schan->dev);
  306. schan->pm_state = SHDMA_PM_ESTABLISHED;
  307. }
  308. }
  309. }
  310. if (all && !callback)
  311. /*
  312. * Terminating and the loop completed normally: forgive
  313. * uncompleted cookies
  314. */
  315. schan->dma_chan.completed_cookie = schan->dma_chan.cookie;
  316. spin_unlock_irqrestore(&schan->chan_lock, flags);
  317. if (callback)
  318. callback(param);
  319. return callback;
  320. }
  321. /*
  322. * shdma_chan_ld_cleanup - Clean up link descriptors
  323. *
  324. * Clean up the ld_queue of DMA channel.
  325. */
  326. static void shdma_chan_ld_cleanup(struct shdma_chan *schan, bool all)
  327. {
  328. while (__ld_cleanup(schan, all))
  329. ;
  330. }
  331. /*
  332. * shdma_free_chan_resources - Free all resources of the channel.
  333. */
  334. static void shdma_free_chan_resources(struct dma_chan *chan)
  335. {
  336. struct shdma_chan *schan = to_shdma_chan(chan);
  337. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  338. const struct shdma_ops *ops = sdev->ops;
  339. LIST_HEAD(list);
  340. /* Protect against ISR */
  341. spin_lock_irq(&schan->chan_lock);
  342. ops->halt_channel(schan);
  343. spin_unlock_irq(&schan->chan_lock);
  344. /* Now no new interrupts will occur */
  345. /* Prepared and not submitted descriptors can still be on the queue */
  346. if (!list_empty(&schan->ld_queue))
  347. shdma_chan_ld_cleanup(schan, true);
  348. if (schan->slave_id >= 0) {
  349. /* The caller is holding dma_list_mutex */
  350. clear_bit(schan->slave_id, shdma_slave_used);
  351. chan->private = NULL;
  352. }
  353. spin_lock_irq(&schan->chan_lock);
  354. list_splice_init(&schan->ld_free, &list);
  355. schan->desc_num = 0;
  356. spin_unlock_irq(&schan->chan_lock);
  357. kfree(schan->desc);
  358. }
  359. /**
  360. * shdma_add_desc - get, set up and return one transfer descriptor
  361. * @schan: DMA channel
  362. * @flags: DMA transfer flags
  363. * @dst: destination DMA address, incremented when direction equals
  364. * DMA_DEV_TO_MEM or DMA_MEM_TO_MEM
  365. * @src: source DMA address, incremented when direction equals
  366. * DMA_MEM_TO_DEV or DMA_MEM_TO_MEM
  367. * @len: DMA transfer length
  368. * @first: if NULL, set to the current descriptor and cookie set to -EBUSY
  369. * @direction: needed for slave DMA to decide which address to keep constant,
  370. * equals DMA_MEM_TO_MEM for MEMCPY
  371. * Returns 0 or an error
  372. * Locks: called with desc_lock held
  373. */
  374. static struct shdma_desc *shdma_add_desc(struct shdma_chan *schan,
  375. unsigned long flags, dma_addr_t *dst, dma_addr_t *src, size_t *len,
  376. struct shdma_desc **first, enum dma_transfer_direction direction)
  377. {
  378. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  379. const struct shdma_ops *ops = sdev->ops;
  380. struct shdma_desc *new;
  381. size_t copy_size = *len;
  382. if (!copy_size)
  383. return NULL;
  384. /* Allocate the link descriptor from the free list */
  385. new = shdma_get_desc(schan);
  386. if (!new) {
  387. dev_err(schan->dev, "No free link descriptor available\n");
  388. return NULL;
  389. }
  390. ops->desc_setup(schan, new, *src, *dst, &copy_size);
  391. if (!*first) {
  392. /* First desc */
  393. new->async_tx.cookie = -EBUSY;
  394. *first = new;
  395. } else {
  396. /* Other desc - invisible to the user */
  397. new->async_tx.cookie = -EINVAL;
  398. }
  399. dev_dbg(schan->dev,
  400. "chaining (%u/%u)@%x -> %x with %p, cookie %d\n",
  401. copy_size, *len, *src, *dst, &new->async_tx,
  402. new->async_tx.cookie);
  403. new->mark = DESC_PREPARED;
  404. new->async_tx.flags = flags;
  405. new->direction = direction;
  406. new->partial = 0;
  407. *len -= copy_size;
  408. if (direction == DMA_MEM_TO_MEM || direction == DMA_MEM_TO_DEV)
  409. *src += copy_size;
  410. if (direction == DMA_MEM_TO_MEM || direction == DMA_DEV_TO_MEM)
  411. *dst += copy_size;
  412. return new;
  413. }
  414. /*
  415. * shdma_prep_sg - prepare transfer descriptors from an SG list
  416. *
  417. * Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
  418. * converted to scatter-gather to guarantee consistent locking and a correct
  419. * list manipulation. For slave DMA direction carries the usual meaning, and,
  420. * logically, the SG list is RAM and the addr variable contains slave address,
  421. * e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
  422. * and the SG list contains only one element and points at the source buffer.
  423. */
  424. static struct dma_async_tx_descriptor *shdma_prep_sg(struct shdma_chan *schan,
  425. struct scatterlist *sgl, unsigned int sg_len, dma_addr_t *addr,
  426. enum dma_transfer_direction direction, unsigned long flags)
  427. {
  428. struct scatterlist *sg;
  429. struct shdma_desc *first = NULL, *new = NULL /* compiler... */;
  430. LIST_HEAD(tx_list);
  431. int chunks = 0;
  432. unsigned long irq_flags;
  433. int i;
  434. for_each_sg(sgl, sg, sg_len, i)
  435. chunks += DIV_ROUND_UP(sg_dma_len(sg), schan->max_xfer_len);
  436. /* Have to lock the whole loop to protect against concurrent release */
  437. spin_lock_irqsave(&schan->chan_lock, irq_flags);
  438. /*
  439. * Chaining:
  440. * first descriptor is what user is dealing with in all API calls, its
  441. * cookie is at first set to -EBUSY, at tx-submit to a positive
  442. * number
  443. * if more than one chunk is needed further chunks have cookie = -EINVAL
  444. * the last chunk, if not equal to the first, has cookie = -ENOSPC
  445. * all chunks are linked onto the tx_list head with their .node heads
  446. * only during this function, then they are immediately spliced
  447. * back onto the free list in form of a chain
  448. */
  449. for_each_sg(sgl, sg, sg_len, i) {
  450. dma_addr_t sg_addr = sg_dma_address(sg);
  451. size_t len = sg_dma_len(sg);
  452. if (!len)
  453. goto err_get_desc;
  454. do {
  455. dev_dbg(schan->dev, "Add SG #%d@%p[%d], dma %llx\n",
  456. i, sg, len, (unsigned long long)sg_addr);
  457. if (direction == DMA_DEV_TO_MEM)
  458. new = shdma_add_desc(schan, flags,
  459. &sg_addr, addr, &len, &first,
  460. direction);
  461. else
  462. new = shdma_add_desc(schan, flags,
  463. addr, &sg_addr, &len, &first,
  464. direction);
  465. if (!new)
  466. goto err_get_desc;
  467. new->chunks = chunks--;
  468. list_add_tail(&new->node, &tx_list);
  469. } while (len);
  470. }
  471. if (new != first)
  472. new->async_tx.cookie = -ENOSPC;
  473. /* Put them back on the free list, so, they don't get lost */
  474. list_splice_tail(&tx_list, &schan->ld_free);
  475. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  476. return &first->async_tx;
  477. err_get_desc:
  478. list_for_each_entry(new, &tx_list, node)
  479. new->mark = DESC_IDLE;
  480. list_splice(&tx_list, &schan->ld_free);
  481. spin_unlock_irqrestore(&schan->chan_lock, irq_flags);
  482. return NULL;
  483. }
  484. static struct dma_async_tx_descriptor *shdma_prep_memcpy(
  485. struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src,
  486. size_t len, unsigned long flags)
  487. {
  488. struct shdma_chan *schan = to_shdma_chan(chan);
  489. struct scatterlist sg;
  490. if (!chan || !len)
  491. return NULL;
  492. BUG_ON(!schan->desc_num);
  493. sg_init_table(&sg, 1);
  494. sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_src)), len,
  495. offset_in_page(dma_src));
  496. sg_dma_address(&sg) = dma_src;
  497. sg_dma_len(&sg) = len;
  498. return shdma_prep_sg(schan, &sg, 1, &dma_dest, DMA_MEM_TO_MEM, flags);
  499. }
  500. static struct dma_async_tx_descriptor *shdma_prep_slave_sg(
  501. struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
  502. enum dma_transfer_direction direction, unsigned long flags, void *context)
  503. {
  504. struct shdma_chan *schan = to_shdma_chan(chan);
  505. struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
  506. const struct shdma_ops *ops = sdev->ops;
  507. int slave_id = schan->slave_id;
  508. dma_addr_t slave_addr;
  509. if (!chan)
  510. return NULL;
  511. BUG_ON(!schan->desc_num);
  512. /* Someone calling slave DMA on a generic channel? */
  513. if (slave_id < 0 || !sg_len) {
  514. dev_warn(schan->dev, "%s: bad parameter: len=%d, id=%d\n",
  515. __func__, sg_len, slave_id);
  516. return NULL;
  517. }
  518. slave_addr = ops->slave_addr(schan);
  519. return shdma_prep_sg(schan, sgl, sg_len, &slave_addr,
  520. direction, flags);
  521. }
  522. static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
  523. unsigned long arg)
  524. {
  525. struct shdma_chan *schan = to_shdma_chan(chan);
  526. struct shdma_dev *sdev = to_shdma_dev(chan->device);
  527. const struct shdma_ops *ops = sdev->ops;
  528. struct dma_slave_config *config;
  529. unsigned long flags;
  530. int ret;
  531. switch (cmd) {
  532. case DMA_TERMINATE_ALL:
  533. spin_lock_irqsave(&schan->chan_lock, flags);
  534. ops->halt_channel(schan);
  535. if (ops->get_partial && !list_empty(&schan->ld_queue)) {
  536. /* Record partial transfer */
  537. struct shdma_desc *desc = list_first_entry(&schan->ld_queue,
  538. struct shdma_desc, node);
  539. desc->partial = ops->get_partial(schan, desc);
  540. }
  541. spin_unlock_irqrestore(&schan->chan_lock, flags);
  542. shdma_chan_ld_cleanup(schan, true);
  543. break;
  544. case DMA_SLAVE_CONFIG:
  545. /*
  546. * So far only .slave_id is used, but the slave drivers are
  547. * encouraged to also set a transfer direction and an address.
  548. */
  549. if (!arg)
  550. return -EINVAL;
  551. /*
  552. * We could lock this, but you shouldn't be configuring the
  553. * channel, while using it...
  554. */
  555. config = (struct dma_slave_config *)arg;
  556. ret = shdma_setup_slave(schan, config->slave_id);
  557. if (ret < 0)
  558. return ret;
  559. break;
  560. default:
  561. return -ENXIO;
  562. }
  563. return 0;
  564. }
  565. static void shdma_issue_pending(struct dma_chan *chan)
  566. {
  567. struct shdma_chan *schan = to_shdma_chan(chan);
  568. spin_lock_irq(&schan->chan_lock);
  569. if (schan->pm_state == SHDMA_PM_ESTABLISHED)
  570. shdma_chan_xfer_ld_queue(schan);
  571. else
  572. schan->pm_state = SHDMA_PM_PENDING;
  573. spin_unlock_irq(&schan->chan_lock);
  574. }
  575. static enum dma_status shdma_tx_status(struct dma_chan *chan,
  576. dma_cookie_t cookie,
  577. struct dma_tx_state *txstate)
  578. {
  579. struct shdma_chan *schan = to_shdma_chan(chan);
  580. enum dma_status status;
  581. unsigned long flags;
  582. shdma_chan_ld_cleanup(schan, false);
  583. spin_lock_irqsave(&schan->chan_lock, flags);
  584. status = dma_cookie_status(chan, cookie, txstate);
  585. /*
  586. * If we don't find cookie on the queue, it has been aborted and we have
  587. * to report error
  588. */
  589. if (status != DMA_SUCCESS) {
  590. struct shdma_desc *sdesc;
  591. status = DMA_ERROR;
  592. list_for_each_entry(sdesc, &schan->ld_queue, node)
  593. if (sdesc->cookie == cookie) {
  594. status = DMA_IN_PROGRESS;
  595. break;
  596. }
  597. }
  598. spin_unlock_irqrestore(&schan->chan_lock, flags);
  599. return status;
  600. }
  601. /* Called from error IRQ or NMI */
  602. bool shdma_reset(struct shdma_dev *sdev)
  603. {
  604. const struct shdma_ops *ops = sdev->ops;
  605. struct shdma_chan *schan;
  606. unsigned int handled = 0;
  607. int i;
  608. /* Reset all channels */
  609. shdma_for_each_chan(schan, sdev, i) {
  610. struct shdma_desc *sdesc;
  611. LIST_HEAD(dl);
  612. if (!schan)
  613. continue;
  614. spin_lock(&schan->chan_lock);
  615. /* Stop the channel */
  616. ops->halt_channel(schan);
  617. list_splice_init(&schan->ld_queue, &dl);
  618. if (!list_empty(&dl)) {
  619. dev_dbg(schan->dev, "Bring down channel %d\n", schan->id);
  620. pm_runtime_put(schan->dev);
  621. }
  622. schan->pm_state = SHDMA_PM_ESTABLISHED;
  623. spin_unlock(&schan->chan_lock);
  624. /* Complete all */
  625. list_for_each_entry(sdesc, &dl, node) {
  626. struct dma_async_tx_descriptor *tx = &sdesc->async_tx;
  627. sdesc->mark = DESC_IDLE;
  628. if (tx->callback)
  629. tx->callback(tx->callback_param);
  630. }
  631. spin_lock(&schan->chan_lock);
  632. list_splice(&dl, &schan->ld_free);
  633. spin_unlock(&schan->chan_lock);
  634. handled++;
  635. }
  636. return !!handled;
  637. }
  638. EXPORT_SYMBOL(shdma_reset);
  639. static irqreturn_t chan_irq(int irq, void *dev)
  640. {
  641. struct shdma_chan *schan = dev;
  642. const struct shdma_ops *ops =
  643. to_shdma_dev(schan->dma_chan.device)->ops;
  644. irqreturn_t ret;
  645. spin_lock(&schan->chan_lock);
  646. ret = ops->chan_irq(schan, irq) ? IRQ_WAKE_THREAD : IRQ_NONE;
  647. spin_unlock(&schan->chan_lock);
  648. return ret;
  649. }
  650. static irqreturn_t chan_irqt(int irq, void *dev)
  651. {
  652. struct shdma_chan *schan = dev;
  653. const struct shdma_ops *ops =
  654. to_shdma_dev(schan->dma_chan.device)->ops;
  655. struct shdma_desc *sdesc;
  656. spin_lock_irq(&schan->chan_lock);
  657. list_for_each_entry(sdesc, &schan->ld_queue, node) {
  658. if (sdesc->mark == DESC_SUBMITTED &&
  659. ops->desc_completed(schan, sdesc)) {
  660. dev_dbg(schan->dev, "done #%d@%p\n",
  661. sdesc->async_tx.cookie, &sdesc->async_tx);
  662. sdesc->mark = DESC_COMPLETED;
  663. break;
  664. }
  665. }
  666. /* Next desc */
  667. shdma_chan_xfer_ld_queue(schan);
  668. spin_unlock_irq(&schan->chan_lock);
  669. shdma_chan_ld_cleanup(schan, false);
  670. return IRQ_HANDLED;
  671. }
  672. int shdma_request_irq(struct shdma_chan *schan, int irq,
  673. unsigned long flags, const char *name)
  674. {
  675. int ret = request_threaded_irq(irq, chan_irq, chan_irqt,
  676. flags, name, schan);
  677. schan->irq = ret < 0 ? ret : irq;
  678. return ret;
  679. }
  680. EXPORT_SYMBOL(shdma_request_irq);
  681. void shdma_free_irq(struct shdma_chan *schan)
  682. {
  683. if (schan->irq >= 0)
  684. free_irq(schan->irq, schan);
  685. }
  686. EXPORT_SYMBOL(shdma_free_irq);
  687. void shdma_chan_probe(struct shdma_dev *sdev,
  688. struct shdma_chan *schan, int id)
  689. {
  690. schan->pm_state = SHDMA_PM_ESTABLISHED;
  691. /* reference struct dma_device */
  692. schan->dma_chan.device = &sdev->dma_dev;
  693. dma_cookie_init(&schan->dma_chan);
  694. schan->dev = sdev->dma_dev.dev;
  695. schan->id = id;
  696. if (!schan->max_xfer_len)
  697. schan->max_xfer_len = PAGE_SIZE;
  698. spin_lock_init(&schan->chan_lock);
  699. /* Init descripter manage list */
  700. INIT_LIST_HEAD(&schan->ld_queue);
  701. INIT_LIST_HEAD(&schan->ld_free);
  702. /* Add the channel to DMA device channel list */
  703. list_add_tail(&schan->dma_chan.device_node,
  704. &sdev->dma_dev.channels);
  705. sdev->schan[sdev->dma_dev.chancnt++] = schan;
  706. }
  707. EXPORT_SYMBOL(shdma_chan_probe);
  708. void shdma_chan_remove(struct shdma_chan *schan)
  709. {
  710. list_del(&schan->dma_chan.device_node);
  711. }
  712. EXPORT_SYMBOL(shdma_chan_remove);
  713. int shdma_init(struct device *dev, struct shdma_dev *sdev,
  714. int chan_num)
  715. {
  716. struct dma_device *dma_dev = &sdev->dma_dev;
  717. /*
  718. * Require all call-backs for now, they can trivially be made optional
  719. * later as required
  720. */
  721. if (!sdev->ops ||
  722. !sdev->desc_size ||
  723. !sdev->ops->embedded_desc ||
  724. !sdev->ops->start_xfer ||
  725. !sdev->ops->setup_xfer ||
  726. !sdev->ops->set_slave ||
  727. !sdev->ops->desc_setup ||
  728. !sdev->ops->slave_addr ||
  729. !sdev->ops->channel_busy ||
  730. !sdev->ops->halt_channel ||
  731. !sdev->ops->desc_completed)
  732. return -EINVAL;
  733. sdev->schan = kcalloc(chan_num, sizeof(*sdev->schan), GFP_KERNEL);
  734. if (!sdev->schan)
  735. return -ENOMEM;
  736. INIT_LIST_HEAD(&dma_dev->channels);
  737. /* Common and MEMCPY operations */
  738. dma_dev->device_alloc_chan_resources
  739. = shdma_alloc_chan_resources;
  740. dma_dev->device_free_chan_resources = shdma_free_chan_resources;
  741. dma_dev->device_prep_dma_memcpy = shdma_prep_memcpy;
  742. dma_dev->device_tx_status = shdma_tx_status;
  743. dma_dev->device_issue_pending = shdma_issue_pending;
  744. /* Compulsory for DMA_SLAVE fields */
  745. dma_dev->device_prep_slave_sg = shdma_prep_slave_sg;
  746. dma_dev->device_control = shdma_control;
  747. dma_dev->dev = dev;
  748. return 0;
  749. }
  750. EXPORT_SYMBOL(shdma_init);
  751. void shdma_cleanup(struct shdma_dev *sdev)
  752. {
  753. kfree(sdev->schan);
  754. }
  755. EXPORT_SYMBOL(shdma_cleanup);
  756. static int __init shdma_enter(void)
  757. {
  758. shdma_slave_used = kzalloc(DIV_ROUND_UP(slave_num, BITS_PER_LONG) *
  759. sizeof(long), GFP_KERNEL);
  760. if (!shdma_slave_used)
  761. return -ENOMEM;
  762. return 0;
  763. }
  764. module_init(shdma_enter);
  765. static void __exit shdma_exit(void)
  766. {
  767. kfree(shdma_slave_used);
  768. }
  769. module_exit(shdma_exit);
  770. MODULE_LICENSE("GPL v2");
  771. MODULE_DESCRIPTION("SH-DMA driver base library");
  772. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");