dmaengine.c 29 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/of_dma.h>
  63. static DEFINE_MUTEX(dma_list_mutex);
  64. static DEFINE_IDR(dma_idr);
  65. static LIST_HEAD(dma_device_list);
  66. static long dmaengine_ref_count;
  67. /* --- sysfs implementation --- */
  68. /**
  69. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  70. * @dev - device node
  71. *
  72. * Must be called under dma_list_mutex
  73. */
  74. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  75. {
  76. struct dma_chan_dev *chan_dev;
  77. chan_dev = container_of(dev, typeof(*chan_dev), device);
  78. return chan_dev->chan;
  79. }
  80. static ssize_t show_memcpy_count(struct device *dev, struct device_attribute *attr, char *buf)
  81. {
  82. struct dma_chan *chan;
  83. unsigned long count = 0;
  84. int i;
  85. int err;
  86. mutex_lock(&dma_list_mutex);
  87. chan = dev_to_dma_chan(dev);
  88. if (chan) {
  89. for_each_possible_cpu(i)
  90. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  91. err = sprintf(buf, "%lu\n", count);
  92. } else
  93. err = -ENODEV;
  94. mutex_unlock(&dma_list_mutex);
  95. return err;
  96. }
  97. static ssize_t show_bytes_transferred(struct device *dev, struct device_attribute *attr,
  98. char *buf)
  99. {
  100. struct dma_chan *chan;
  101. unsigned long count = 0;
  102. int i;
  103. int err;
  104. mutex_lock(&dma_list_mutex);
  105. chan = dev_to_dma_chan(dev);
  106. if (chan) {
  107. for_each_possible_cpu(i)
  108. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  109. err = sprintf(buf, "%lu\n", count);
  110. } else
  111. err = -ENODEV;
  112. mutex_unlock(&dma_list_mutex);
  113. return err;
  114. }
  115. static ssize_t show_in_use(struct device *dev, struct device_attribute *attr, char *buf)
  116. {
  117. struct dma_chan *chan;
  118. int err;
  119. mutex_lock(&dma_list_mutex);
  120. chan = dev_to_dma_chan(dev);
  121. if (chan)
  122. err = sprintf(buf, "%d\n", chan->client_count);
  123. else
  124. err = -ENODEV;
  125. mutex_unlock(&dma_list_mutex);
  126. return err;
  127. }
  128. static struct device_attribute dma_attrs[] = {
  129. __ATTR(memcpy_count, S_IRUGO, show_memcpy_count, NULL),
  130. __ATTR(bytes_transferred, S_IRUGO, show_bytes_transferred, NULL),
  131. __ATTR(in_use, S_IRUGO, show_in_use, NULL),
  132. __ATTR_NULL
  133. };
  134. static void chan_dev_release(struct device *dev)
  135. {
  136. struct dma_chan_dev *chan_dev;
  137. chan_dev = container_of(dev, typeof(*chan_dev), device);
  138. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  139. mutex_lock(&dma_list_mutex);
  140. idr_remove(&dma_idr, chan_dev->dev_id);
  141. mutex_unlock(&dma_list_mutex);
  142. kfree(chan_dev->idr_ref);
  143. }
  144. kfree(chan_dev);
  145. }
  146. static struct class dma_devclass = {
  147. .name = "dma",
  148. .dev_attrs = dma_attrs,
  149. .dev_release = chan_dev_release,
  150. };
  151. /* --- client and device registration --- */
  152. #define dma_device_satisfies_mask(device, mask) \
  153. __dma_device_satisfies_mask((device), &(mask))
  154. static int
  155. __dma_device_satisfies_mask(struct dma_device *device, dma_cap_mask_t *want)
  156. {
  157. dma_cap_mask_t has;
  158. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  159. DMA_TX_TYPE_END);
  160. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  161. }
  162. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  163. {
  164. return chan->device->dev->driver->owner;
  165. }
  166. /**
  167. * balance_ref_count - catch up the channel reference count
  168. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  169. *
  170. * balance_ref_count must be called under dma_list_mutex
  171. */
  172. static void balance_ref_count(struct dma_chan *chan)
  173. {
  174. struct module *owner = dma_chan_to_owner(chan);
  175. while (chan->client_count < dmaengine_ref_count) {
  176. __module_get(owner);
  177. chan->client_count++;
  178. }
  179. }
  180. /**
  181. * dma_chan_get - try to grab a dma channel's parent driver module
  182. * @chan - channel to grab
  183. *
  184. * Must be called under dma_list_mutex
  185. */
  186. static int dma_chan_get(struct dma_chan *chan)
  187. {
  188. int err = -ENODEV;
  189. struct module *owner = dma_chan_to_owner(chan);
  190. if (chan->client_count) {
  191. __module_get(owner);
  192. err = 0;
  193. } else if (try_module_get(owner))
  194. err = 0;
  195. if (err == 0)
  196. chan->client_count++;
  197. /* allocate upon first client reference */
  198. if (chan->client_count == 1 && err == 0) {
  199. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  200. if (desc_cnt < 0) {
  201. err = desc_cnt;
  202. chan->client_count = 0;
  203. module_put(owner);
  204. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  205. balance_ref_count(chan);
  206. }
  207. return err;
  208. }
  209. /**
  210. * dma_chan_put - drop a reference to a dma channel's parent driver module
  211. * @chan - channel to release
  212. *
  213. * Must be called under dma_list_mutex
  214. */
  215. static void dma_chan_put(struct dma_chan *chan)
  216. {
  217. if (!chan->client_count)
  218. return; /* this channel failed alloc_chan_resources */
  219. chan->client_count--;
  220. module_put(dma_chan_to_owner(chan));
  221. if (chan->client_count == 0)
  222. chan->device->device_free_chan_resources(chan);
  223. }
  224. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  225. {
  226. enum dma_status status;
  227. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  228. dma_async_issue_pending(chan);
  229. do {
  230. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  231. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  232. pr_err("%s: timeout!\n", __func__);
  233. return DMA_ERROR;
  234. }
  235. if (status != DMA_IN_PROGRESS)
  236. break;
  237. cpu_relax();
  238. } while (1);
  239. return status;
  240. }
  241. EXPORT_SYMBOL(dma_sync_wait);
  242. /**
  243. * dma_cap_mask_all - enable iteration over all operation types
  244. */
  245. static dma_cap_mask_t dma_cap_mask_all;
  246. /**
  247. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  248. * @chan - associated channel for this entry
  249. */
  250. struct dma_chan_tbl_ent {
  251. struct dma_chan *chan;
  252. };
  253. /**
  254. * channel_table - percpu lookup table for memory-to-memory offload providers
  255. */
  256. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  257. static int __init dma_channel_table_init(void)
  258. {
  259. enum dma_transaction_type cap;
  260. int err = 0;
  261. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  262. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  263. * but are not associated with an operation so they do not need
  264. * an entry in the channel_table
  265. */
  266. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  267. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  268. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  269. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  270. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  271. if (!channel_table[cap]) {
  272. err = -ENOMEM;
  273. break;
  274. }
  275. }
  276. if (err) {
  277. pr_err("initialization failure\n");
  278. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  279. if (channel_table[cap])
  280. free_percpu(channel_table[cap]);
  281. }
  282. return err;
  283. }
  284. arch_initcall(dma_channel_table_init);
  285. /**
  286. * dma_find_channel - find a channel to carry out the operation
  287. * @tx_type: transaction type
  288. */
  289. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  290. {
  291. return this_cpu_read(channel_table[tx_type]->chan);
  292. }
  293. EXPORT_SYMBOL(dma_find_channel);
  294. /*
  295. * net_dma_find_channel - find a channel for net_dma
  296. * net_dma has alignment requirements
  297. */
  298. struct dma_chan *net_dma_find_channel(void)
  299. {
  300. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  301. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  302. return NULL;
  303. return chan;
  304. }
  305. EXPORT_SYMBOL(net_dma_find_channel);
  306. /**
  307. * dma_issue_pending_all - flush all pending operations across all channels
  308. */
  309. void dma_issue_pending_all(void)
  310. {
  311. struct dma_device *device;
  312. struct dma_chan *chan;
  313. rcu_read_lock();
  314. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  315. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  316. continue;
  317. list_for_each_entry(chan, &device->channels, device_node)
  318. if (chan->client_count)
  319. device->device_issue_pending(chan);
  320. }
  321. rcu_read_unlock();
  322. }
  323. EXPORT_SYMBOL(dma_issue_pending_all);
  324. /**
  325. * nth_chan - returns the nth channel of the given capability
  326. * @cap: capability to match
  327. * @n: nth channel desired
  328. *
  329. * Defaults to returning the channel with the desired capability and the
  330. * lowest reference count when 'n' cannot be satisfied. Must be called
  331. * under dma_list_mutex.
  332. */
  333. static struct dma_chan *nth_chan(enum dma_transaction_type cap, int n)
  334. {
  335. struct dma_device *device;
  336. struct dma_chan *chan;
  337. struct dma_chan *ret = NULL;
  338. struct dma_chan *min = NULL;
  339. list_for_each_entry(device, &dma_device_list, global_node) {
  340. if (!dma_has_cap(cap, device->cap_mask) ||
  341. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  342. continue;
  343. list_for_each_entry(chan, &device->channels, device_node) {
  344. if (!chan->client_count)
  345. continue;
  346. if (!min)
  347. min = chan;
  348. else if (chan->table_count < min->table_count)
  349. min = chan;
  350. if (n-- == 0) {
  351. ret = chan;
  352. break; /* done */
  353. }
  354. }
  355. if (ret)
  356. break; /* done */
  357. }
  358. if (!ret)
  359. ret = min;
  360. if (ret)
  361. ret->table_count++;
  362. return ret;
  363. }
  364. /**
  365. * dma_channel_rebalance - redistribute the available channels
  366. *
  367. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  368. * operation type) in the SMP case, and operation isolation (avoid
  369. * multi-tasking channels) in the non-SMP case. Must be called under
  370. * dma_list_mutex.
  371. */
  372. static void dma_channel_rebalance(void)
  373. {
  374. struct dma_chan *chan;
  375. struct dma_device *device;
  376. int cpu;
  377. int cap;
  378. int n;
  379. /* undo the last distribution */
  380. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  381. for_each_possible_cpu(cpu)
  382. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  383. list_for_each_entry(device, &dma_device_list, global_node) {
  384. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  385. continue;
  386. list_for_each_entry(chan, &device->channels, device_node)
  387. chan->table_count = 0;
  388. }
  389. /* don't populate the channel_table if no clients are available */
  390. if (!dmaengine_ref_count)
  391. return;
  392. /* redistribute available channels */
  393. n = 0;
  394. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  395. for_each_online_cpu(cpu) {
  396. if (num_possible_cpus() > 1)
  397. chan = nth_chan(cap, n++);
  398. else
  399. chan = nth_chan(cap, -1);
  400. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  401. }
  402. }
  403. static struct dma_chan *private_candidate(dma_cap_mask_t *mask, struct dma_device *dev,
  404. dma_filter_fn fn, void *fn_param)
  405. {
  406. struct dma_chan *chan;
  407. if (!__dma_device_satisfies_mask(dev, mask)) {
  408. pr_debug("%s: wrong capabilities\n", __func__);
  409. return NULL;
  410. }
  411. /* devices with multiple channels need special handling as we need to
  412. * ensure that all channels are either private or public.
  413. */
  414. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  415. list_for_each_entry(chan, &dev->channels, device_node) {
  416. /* some channels are already publicly allocated */
  417. if (chan->client_count)
  418. return NULL;
  419. }
  420. list_for_each_entry(chan, &dev->channels, device_node) {
  421. if (chan->client_count) {
  422. pr_debug("%s: %s busy\n",
  423. __func__, dma_chan_name(chan));
  424. continue;
  425. }
  426. if (fn && !fn(chan, fn_param)) {
  427. pr_debug("%s: %s filter said false\n",
  428. __func__, dma_chan_name(chan));
  429. continue;
  430. }
  431. return chan;
  432. }
  433. return NULL;
  434. }
  435. /**
  436. * dma_request_channel - try to allocate an exclusive channel
  437. * @mask: capabilities that the channel must satisfy
  438. * @fn: optional callback to disposition available channels
  439. * @fn_param: opaque parameter to pass to dma_filter_fn
  440. */
  441. struct dma_chan *__dma_request_channel(dma_cap_mask_t *mask, dma_filter_fn fn, void *fn_param)
  442. {
  443. struct dma_device *device, *_d;
  444. struct dma_chan *chan = NULL;
  445. int err;
  446. /* Find a channel */
  447. mutex_lock(&dma_list_mutex);
  448. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  449. chan = private_candidate(mask, device, fn, fn_param);
  450. if (chan) {
  451. /* Found a suitable channel, try to grab, prep, and
  452. * return it. We first set DMA_PRIVATE to disable
  453. * balance_ref_count as this channel will not be
  454. * published in the general-purpose allocator
  455. */
  456. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  457. device->privatecnt++;
  458. err = dma_chan_get(chan);
  459. if (err == -ENODEV) {
  460. pr_debug("%s: %s module removed\n",
  461. __func__, dma_chan_name(chan));
  462. list_del_rcu(&device->global_node);
  463. } else if (err)
  464. pr_debug("%s: failed to get %s: (%d)\n",
  465. __func__, dma_chan_name(chan), err);
  466. else
  467. break;
  468. if (--device->privatecnt == 0)
  469. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  470. chan = NULL;
  471. }
  472. }
  473. mutex_unlock(&dma_list_mutex);
  474. pr_debug("%s: %s (%s)\n",
  475. __func__,
  476. chan ? "success" : "fail",
  477. chan ? dma_chan_name(chan) : NULL);
  478. return chan;
  479. }
  480. EXPORT_SYMBOL_GPL(__dma_request_channel);
  481. /**
  482. * dma_request_slave_channel - try to allocate an exclusive slave channel
  483. * @dev: pointer to client device structure
  484. * @name: slave channel name
  485. */
  486. struct dma_chan *dma_request_slave_channel(struct device *dev, char *name)
  487. {
  488. /* If device-tree is present get slave info from here */
  489. if (dev->of_node)
  490. return of_dma_request_slave_channel(dev->of_node, name);
  491. return NULL;
  492. }
  493. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  494. void dma_release_channel(struct dma_chan *chan)
  495. {
  496. mutex_lock(&dma_list_mutex);
  497. WARN_ONCE(chan->client_count != 1,
  498. "chan reference count %d != 1\n", chan->client_count);
  499. dma_chan_put(chan);
  500. /* drop PRIVATE cap enabled by __dma_request_channel() */
  501. if (--chan->device->privatecnt == 0)
  502. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  503. mutex_unlock(&dma_list_mutex);
  504. }
  505. EXPORT_SYMBOL_GPL(dma_release_channel);
  506. /**
  507. * dmaengine_get - register interest in dma_channels
  508. */
  509. void dmaengine_get(void)
  510. {
  511. struct dma_device *device, *_d;
  512. struct dma_chan *chan;
  513. int err;
  514. mutex_lock(&dma_list_mutex);
  515. dmaengine_ref_count++;
  516. /* try to grab channels */
  517. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  518. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  519. continue;
  520. list_for_each_entry(chan, &device->channels, device_node) {
  521. err = dma_chan_get(chan);
  522. if (err == -ENODEV) {
  523. /* module removed before we could use it */
  524. list_del_rcu(&device->global_node);
  525. break;
  526. } else if (err)
  527. pr_debug("%s: failed to get %s: (%d)\n",
  528. __func__, dma_chan_name(chan), err);
  529. }
  530. }
  531. /* if this is the first reference and there were channels
  532. * waiting we need to rebalance to get those channels
  533. * incorporated into the channel table
  534. */
  535. if (dmaengine_ref_count == 1)
  536. dma_channel_rebalance();
  537. mutex_unlock(&dma_list_mutex);
  538. }
  539. EXPORT_SYMBOL(dmaengine_get);
  540. /**
  541. * dmaengine_put - let dma drivers be removed when ref_count == 0
  542. */
  543. void dmaengine_put(void)
  544. {
  545. struct dma_device *device;
  546. struct dma_chan *chan;
  547. mutex_lock(&dma_list_mutex);
  548. dmaengine_ref_count--;
  549. BUG_ON(dmaengine_ref_count < 0);
  550. /* drop channel references */
  551. list_for_each_entry(device, &dma_device_list, global_node) {
  552. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  553. continue;
  554. list_for_each_entry(chan, &device->channels, device_node)
  555. dma_chan_put(chan);
  556. }
  557. mutex_unlock(&dma_list_mutex);
  558. }
  559. EXPORT_SYMBOL(dmaengine_put);
  560. static bool device_has_all_tx_types(struct dma_device *device)
  561. {
  562. /* A device that satisfies this test has channels that will never cause
  563. * an async_tx channel switch event as all possible operation types can
  564. * be handled.
  565. */
  566. #ifdef CONFIG_ASYNC_TX_DMA
  567. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  568. return false;
  569. #endif
  570. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  571. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  572. return false;
  573. #endif
  574. #if defined(CONFIG_ASYNC_MEMSET) || defined(CONFIG_ASYNC_MEMSET_MODULE)
  575. if (!dma_has_cap(DMA_MEMSET, device->cap_mask))
  576. return false;
  577. #endif
  578. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  579. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  580. return false;
  581. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  582. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  583. return false;
  584. #endif
  585. #endif
  586. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  587. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  588. return false;
  589. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  590. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  591. return false;
  592. #endif
  593. #endif
  594. return true;
  595. }
  596. static int get_dma_id(struct dma_device *device)
  597. {
  598. int rc;
  599. mutex_lock(&dma_list_mutex);
  600. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  601. if (rc >= 0)
  602. device->dev_id = rc;
  603. mutex_unlock(&dma_list_mutex);
  604. return rc < 0 ? rc : 0;
  605. }
  606. /**
  607. * dma_async_device_register - registers DMA devices found
  608. * @device: &dma_device
  609. */
  610. int dma_async_device_register(struct dma_device *device)
  611. {
  612. int chancnt = 0, rc;
  613. struct dma_chan* chan;
  614. atomic_t *idr_ref;
  615. if (!device)
  616. return -ENODEV;
  617. /* validate device routines */
  618. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  619. !device->device_prep_dma_memcpy);
  620. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  621. !device->device_prep_dma_xor);
  622. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  623. !device->device_prep_dma_xor_val);
  624. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  625. !device->device_prep_dma_pq);
  626. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  627. !device->device_prep_dma_pq_val);
  628. BUG_ON(dma_has_cap(DMA_MEMSET, device->cap_mask) &&
  629. !device->device_prep_dma_memset);
  630. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  631. !device->device_prep_dma_interrupt);
  632. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  633. !device->device_prep_dma_sg);
  634. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  635. !device->device_prep_dma_cyclic);
  636. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  637. !device->device_control);
  638. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  639. !device->device_prep_interleaved_dma);
  640. BUG_ON(!device->device_alloc_chan_resources);
  641. BUG_ON(!device->device_free_chan_resources);
  642. BUG_ON(!device->device_tx_status);
  643. BUG_ON(!device->device_issue_pending);
  644. BUG_ON(!device->dev);
  645. /* note: this only matters in the
  646. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  647. */
  648. if (device_has_all_tx_types(device))
  649. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  650. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  651. if (!idr_ref)
  652. return -ENOMEM;
  653. rc = get_dma_id(device);
  654. if (rc != 0) {
  655. kfree(idr_ref);
  656. return rc;
  657. }
  658. atomic_set(idr_ref, 0);
  659. /* represent channels in sysfs. Probably want devs too */
  660. list_for_each_entry(chan, &device->channels, device_node) {
  661. rc = -ENOMEM;
  662. chan->local = alloc_percpu(typeof(*chan->local));
  663. if (chan->local == NULL)
  664. goto err_out;
  665. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  666. if (chan->dev == NULL) {
  667. free_percpu(chan->local);
  668. chan->local = NULL;
  669. goto err_out;
  670. }
  671. chan->chan_id = chancnt++;
  672. chan->dev->device.class = &dma_devclass;
  673. chan->dev->device.parent = device->dev;
  674. chan->dev->chan = chan;
  675. chan->dev->idr_ref = idr_ref;
  676. chan->dev->dev_id = device->dev_id;
  677. atomic_inc(idr_ref);
  678. dev_set_name(&chan->dev->device, "dma%dchan%d",
  679. device->dev_id, chan->chan_id);
  680. rc = device_register(&chan->dev->device);
  681. if (rc) {
  682. free_percpu(chan->local);
  683. chan->local = NULL;
  684. kfree(chan->dev);
  685. atomic_dec(idr_ref);
  686. goto err_out;
  687. }
  688. chan->client_count = 0;
  689. }
  690. device->chancnt = chancnt;
  691. mutex_lock(&dma_list_mutex);
  692. /* take references on public channels */
  693. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  694. list_for_each_entry(chan, &device->channels, device_node) {
  695. /* if clients are already waiting for channels we need
  696. * to take references on their behalf
  697. */
  698. if (dma_chan_get(chan) == -ENODEV) {
  699. /* note we can only get here for the first
  700. * channel as the remaining channels are
  701. * guaranteed to get a reference
  702. */
  703. rc = -ENODEV;
  704. mutex_unlock(&dma_list_mutex);
  705. goto err_out;
  706. }
  707. }
  708. list_add_tail_rcu(&device->global_node, &dma_device_list);
  709. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  710. device->privatecnt++; /* Always private */
  711. dma_channel_rebalance();
  712. mutex_unlock(&dma_list_mutex);
  713. return 0;
  714. err_out:
  715. /* if we never registered a channel just release the idr */
  716. if (atomic_read(idr_ref) == 0) {
  717. mutex_lock(&dma_list_mutex);
  718. idr_remove(&dma_idr, device->dev_id);
  719. mutex_unlock(&dma_list_mutex);
  720. kfree(idr_ref);
  721. return rc;
  722. }
  723. list_for_each_entry(chan, &device->channels, device_node) {
  724. if (chan->local == NULL)
  725. continue;
  726. mutex_lock(&dma_list_mutex);
  727. chan->dev->chan = NULL;
  728. mutex_unlock(&dma_list_mutex);
  729. device_unregister(&chan->dev->device);
  730. free_percpu(chan->local);
  731. }
  732. return rc;
  733. }
  734. EXPORT_SYMBOL(dma_async_device_register);
  735. /**
  736. * dma_async_device_unregister - unregister a DMA device
  737. * @device: &dma_device
  738. *
  739. * This routine is called by dma driver exit routines, dmaengine holds module
  740. * references to prevent it being called while channels are in use.
  741. */
  742. void dma_async_device_unregister(struct dma_device *device)
  743. {
  744. struct dma_chan *chan;
  745. mutex_lock(&dma_list_mutex);
  746. list_del_rcu(&device->global_node);
  747. dma_channel_rebalance();
  748. mutex_unlock(&dma_list_mutex);
  749. list_for_each_entry(chan, &device->channels, device_node) {
  750. WARN_ONCE(chan->client_count,
  751. "%s called while %d clients hold a reference\n",
  752. __func__, chan->client_count);
  753. mutex_lock(&dma_list_mutex);
  754. chan->dev->chan = NULL;
  755. mutex_unlock(&dma_list_mutex);
  756. device_unregister(&chan->dev->device);
  757. free_percpu(chan->local);
  758. }
  759. }
  760. EXPORT_SYMBOL(dma_async_device_unregister);
  761. /**
  762. * dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
  763. * @chan: DMA channel to offload copy to
  764. * @dest: destination address (virtual)
  765. * @src: source address (virtual)
  766. * @len: length
  767. *
  768. * Both @dest and @src must be mappable to a bus address according to the
  769. * DMA mapping API rules for streaming mappings.
  770. * Both @dest and @src must stay memory resident (kernel memory or locked
  771. * user space pages).
  772. */
  773. dma_cookie_t
  774. dma_async_memcpy_buf_to_buf(struct dma_chan *chan, void *dest,
  775. void *src, size_t len)
  776. {
  777. struct dma_device *dev = chan->device;
  778. struct dma_async_tx_descriptor *tx;
  779. dma_addr_t dma_dest, dma_src;
  780. dma_cookie_t cookie;
  781. unsigned long flags;
  782. dma_src = dma_map_single(dev->dev, src, len, DMA_TO_DEVICE);
  783. dma_dest = dma_map_single(dev->dev, dest, len, DMA_FROM_DEVICE);
  784. flags = DMA_CTRL_ACK |
  785. DMA_COMPL_SRC_UNMAP_SINGLE |
  786. DMA_COMPL_DEST_UNMAP_SINGLE;
  787. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  788. if (!tx) {
  789. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  790. dma_unmap_single(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  791. return -ENOMEM;
  792. }
  793. tx->callback = NULL;
  794. cookie = tx->tx_submit(tx);
  795. preempt_disable();
  796. __this_cpu_add(chan->local->bytes_transferred, len);
  797. __this_cpu_inc(chan->local->memcpy_count);
  798. preempt_enable();
  799. return cookie;
  800. }
  801. EXPORT_SYMBOL(dma_async_memcpy_buf_to_buf);
  802. /**
  803. * dma_async_memcpy_buf_to_pg - offloaded copy from address to page
  804. * @chan: DMA channel to offload copy to
  805. * @page: destination page
  806. * @offset: offset in page to copy to
  807. * @kdata: source address (virtual)
  808. * @len: length
  809. *
  810. * Both @page/@offset and @kdata must be mappable to a bus address according
  811. * to the DMA mapping API rules for streaming mappings.
  812. * Both @page/@offset and @kdata must stay memory resident (kernel memory or
  813. * locked user space pages)
  814. */
  815. dma_cookie_t
  816. dma_async_memcpy_buf_to_pg(struct dma_chan *chan, struct page *page,
  817. unsigned int offset, void *kdata, size_t len)
  818. {
  819. struct dma_device *dev = chan->device;
  820. struct dma_async_tx_descriptor *tx;
  821. dma_addr_t dma_dest, dma_src;
  822. dma_cookie_t cookie;
  823. unsigned long flags;
  824. dma_src = dma_map_single(dev->dev, kdata, len, DMA_TO_DEVICE);
  825. dma_dest = dma_map_page(dev->dev, page, offset, len, DMA_FROM_DEVICE);
  826. flags = DMA_CTRL_ACK | DMA_COMPL_SRC_UNMAP_SINGLE;
  827. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  828. if (!tx) {
  829. dma_unmap_single(dev->dev, dma_src, len, DMA_TO_DEVICE);
  830. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  831. return -ENOMEM;
  832. }
  833. tx->callback = NULL;
  834. cookie = tx->tx_submit(tx);
  835. preempt_disable();
  836. __this_cpu_add(chan->local->bytes_transferred, len);
  837. __this_cpu_inc(chan->local->memcpy_count);
  838. preempt_enable();
  839. return cookie;
  840. }
  841. EXPORT_SYMBOL(dma_async_memcpy_buf_to_pg);
  842. /**
  843. * dma_async_memcpy_pg_to_pg - offloaded copy from page to page
  844. * @chan: DMA channel to offload copy to
  845. * @dest_pg: destination page
  846. * @dest_off: offset in page to copy to
  847. * @src_pg: source page
  848. * @src_off: offset in page to copy from
  849. * @len: length
  850. *
  851. * Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
  852. * address according to the DMA mapping API rules for streaming mappings.
  853. * Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
  854. * (kernel memory or locked user space pages).
  855. */
  856. dma_cookie_t
  857. dma_async_memcpy_pg_to_pg(struct dma_chan *chan, struct page *dest_pg,
  858. unsigned int dest_off, struct page *src_pg, unsigned int src_off,
  859. size_t len)
  860. {
  861. struct dma_device *dev = chan->device;
  862. struct dma_async_tx_descriptor *tx;
  863. dma_addr_t dma_dest, dma_src;
  864. dma_cookie_t cookie;
  865. unsigned long flags;
  866. dma_src = dma_map_page(dev->dev, src_pg, src_off, len, DMA_TO_DEVICE);
  867. dma_dest = dma_map_page(dev->dev, dest_pg, dest_off, len,
  868. DMA_FROM_DEVICE);
  869. flags = DMA_CTRL_ACK;
  870. tx = dev->device_prep_dma_memcpy(chan, dma_dest, dma_src, len, flags);
  871. if (!tx) {
  872. dma_unmap_page(dev->dev, dma_src, len, DMA_TO_DEVICE);
  873. dma_unmap_page(dev->dev, dma_dest, len, DMA_FROM_DEVICE);
  874. return -ENOMEM;
  875. }
  876. tx->callback = NULL;
  877. cookie = tx->tx_submit(tx);
  878. preempt_disable();
  879. __this_cpu_add(chan->local->bytes_transferred, len);
  880. __this_cpu_inc(chan->local->memcpy_count);
  881. preempt_enable();
  882. return cookie;
  883. }
  884. EXPORT_SYMBOL(dma_async_memcpy_pg_to_pg);
  885. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  886. struct dma_chan *chan)
  887. {
  888. tx->chan = chan;
  889. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  890. spin_lock_init(&tx->lock);
  891. #endif
  892. }
  893. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  894. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  895. * @tx: in-flight transaction to wait on
  896. */
  897. enum dma_status
  898. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  899. {
  900. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  901. if (!tx)
  902. return DMA_SUCCESS;
  903. while (tx->cookie == -EBUSY) {
  904. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  905. pr_err("%s timeout waiting for descriptor submission\n",
  906. __func__);
  907. return DMA_ERROR;
  908. }
  909. cpu_relax();
  910. }
  911. return dma_sync_wait(tx->chan, tx->cookie);
  912. }
  913. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  914. /* dma_run_dependencies - helper routine for dma drivers to process
  915. * (start) dependent operations on their target channel
  916. * @tx: transaction with dependencies
  917. */
  918. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  919. {
  920. struct dma_async_tx_descriptor *dep = txd_next(tx);
  921. struct dma_async_tx_descriptor *dep_next;
  922. struct dma_chan *chan;
  923. if (!dep)
  924. return;
  925. /* we'll submit tx->next now, so clear the link */
  926. txd_clear_next(tx);
  927. chan = dep->chan;
  928. /* keep submitting up until a channel switch is detected
  929. * in that case we will be called again as a result of
  930. * processing the interrupt from async_tx_channel_switch
  931. */
  932. for (; dep; dep = dep_next) {
  933. txd_lock(dep);
  934. txd_clear_parent(dep);
  935. dep_next = txd_next(dep);
  936. if (dep_next && dep_next->chan == chan)
  937. txd_clear_next(dep); /* ->next will be submitted */
  938. else
  939. dep_next = NULL; /* submit current dep and terminate */
  940. txd_unlock(dep);
  941. dep->tx_submit(dep);
  942. }
  943. chan->device->device_issue_pending(chan);
  944. }
  945. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  946. static int __init dma_bus_init(void)
  947. {
  948. return class_register(&dma_devclass);
  949. }
  950. arch_initcall(dma_bus_init);