atmel-tdes.c 30 KB

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  1. /*
  2. * Cryptographic API.
  3. *
  4. * Support for ATMEL DES/TDES HW acceleration.
  5. *
  6. * Copyright (c) 2012 Eukréa Electromatique - ATMEL
  7. * Author: Nicolas Royer <nicolas@eukrea.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. *
  13. * Some ideas are from omap-aes.c drivers.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/slab.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/io.h>
  21. #include <linux/hw_random.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/device.h>
  24. #include <linux/init.h>
  25. #include <linux/errno.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/irq.h>
  28. #include <linux/scatterlist.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/delay.h>
  31. #include <linux/crypto.h>
  32. #include <linux/cryptohash.h>
  33. #include <crypto/scatterwalk.h>
  34. #include <crypto/algapi.h>
  35. #include <crypto/des.h>
  36. #include <crypto/hash.h>
  37. #include <crypto/internal/hash.h>
  38. #include "atmel-tdes-regs.h"
  39. /* TDES flags */
  40. #define TDES_FLAGS_MODE_MASK 0x007f
  41. #define TDES_FLAGS_ENCRYPT BIT(0)
  42. #define TDES_FLAGS_CBC BIT(1)
  43. #define TDES_FLAGS_CFB BIT(2)
  44. #define TDES_FLAGS_CFB8 BIT(3)
  45. #define TDES_FLAGS_CFB16 BIT(4)
  46. #define TDES_FLAGS_CFB32 BIT(5)
  47. #define TDES_FLAGS_OFB BIT(6)
  48. #define TDES_FLAGS_INIT BIT(16)
  49. #define TDES_FLAGS_FAST BIT(17)
  50. #define TDES_FLAGS_BUSY BIT(18)
  51. #define ATMEL_TDES_QUEUE_LENGTH 1
  52. #define CFB8_BLOCK_SIZE 1
  53. #define CFB16_BLOCK_SIZE 2
  54. #define CFB32_BLOCK_SIZE 4
  55. #define CFB64_BLOCK_SIZE 8
  56. struct atmel_tdes_dev;
  57. struct atmel_tdes_ctx {
  58. struct atmel_tdes_dev *dd;
  59. int keylen;
  60. u32 key[3*DES_KEY_SIZE / sizeof(u32)];
  61. unsigned long flags;
  62. };
  63. struct atmel_tdes_reqctx {
  64. unsigned long mode;
  65. };
  66. struct atmel_tdes_dev {
  67. struct list_head list;
  68. unsigned long phys_base;
  69. void __iomem *io_base;
  70. struct atmel_tdes_ctx *ctx;
  71. struct device *dev;
  72. struct clk *iclk;
  73. int irq;
  74. unsigned long flags;
  75. int err;
  76. spinlock_t lock;
  77. struct crypto_queue queue;
  78. struct tasklet_struct done_task;
  79. struct tasklet_struct queue_task;
  80. struct ablkcipher_request *req;
  81. size_t total;
  82. struct scatterlist *in_sg;
  83. size_t in_offset;
  84. struct scatterlist *out_sg;
  85. size_t out_offset;
  86. size_t buflen;
  87. size_t dma_size;
  88. void *buf_in;
  89. int dma_in;
  90. dma_addr_t dma_addr_in;
  91. void *buf_out;
  92. int dma_out;
  93. dma_addr_t dma_addr_out;
  94. };
  95. struct atmel_tdes_drv {
  96. struct list_head dev_list;
  97. spinlock_t lock;
  98. };
  99. static struct atmel_tdes_drv atmel_tdes = {
  100. .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list),
  101. .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock),
  102. };
  103. static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset,
  104. void *buf, size_t buflen, size_t total, int out)
  105. {
  106. unsigned int count, off = 0;
  107. while (buflen && total) {
  108. count = min((*sg)->length - *offset, total);
  109. count = min(count, buflen);
  110. if (!count)
  111. return off;
  112. scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
  113. off += count;
  114. buflen -= count;
  115. *offset += count;
  116. total -= count;
  117. if (*offset == (*sg)->length) {
  118. *sg = sg_next(*sg);
  119. if (*sg)
  120. *offset = 0;
  121. else
  122. total = 0;
  123. }
  124. }
  125. return off;
  126. }
  127. static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset)
  128. {
  129. return readl_relaxed(dd->io_base + offset);
  130. }
  131. static inline void atmel_tdes_write(struct atmel_tdes_dev *dd,
  132. u32 offset, u32 value)
  133. {
  134. writel_relaxed(value, dd->io_base + offset);
  135. }
  136. static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset,
  137. u32 *value, int count)
  138. {
  139. for (; count--; value++, offset += 4)
  140. atmel_tdes_write(dd, offset, *value);
  141. }
  142. static struct atmel_tdes_dev *atmel_tdes_find_dev(struct atmel_tdes_ctx *ctx)
  143. {
  144. struct atmel_tdes_dev *tdes_dd = NULL;
  145. struct atmel_tdes_dev *tmp;
  146. spin_lock_bh(&atmel_tdes.lock);
  147. if (!ctx->dd) {
  148. list_for_each_entry(tmp, &atmel_tdes.dev_list, list) {
  149. tdes_dd = tmp;
  150. break;
  151. }
  152. ctx->dd = tdes_dd;
  153. } else {
  154. tdes_dd = ctx->dd;
  155. }
  156. spin_unlock_bh(&atmel_tdes.lock);
  157. return tdes_dd;
  158. }
  159. static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd)
  160. {
  161. clk_prepare_enable(dd->iclk);
  162. if (!(dd->flags & TDES_FLAGS_INIT)) {
  163. atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST);
  164. dd->flags |= TDES_FLAGS_INIT;
  165. dd->err = 0;
  166. }
  167. return 0;
  168. }
  169. static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd)
  170. {
  171. int err;
  172. u32 valcr = 0, valmr = TDES_MR_SMOD_PDC;
  173. err = atmel_tdes_hw_init(dd);
  174. if (err)
  175. return err;
  176. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  177. /* MR register must be set before IV registers */
  178. if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) {
  179. valmr |= TDES_MR_KEYMOD_3KEY;
  180. valmr |= TDES_MR_TDESMOD_TDES;
  181. } else if (dd->ctx->keylen > DES_KEY_SIZE) {
  182. valmr |= TDES_MR_KEYMOD_2KEY;
  183. valmr |= TDES_MR_TDESMOD_TDES;
  184. } else {
  185. valmr |= TDES_MR_TDESMOD_DES;
  186. }
  187. if (dd->flags & TDES_FLAGS_CBC) {
  188. valmr |= TDES_MR_OPMOD_CBC;
  189. } else if (dd->flags & TDES_FLAGS_CFB) {
  190. valmr |= TDES_MR_OPMOD_CFB;
  191. if (dd->flags & TDES_FLAGS_CFB8)
  192. valmr |= TDES_MR_CFBS_8b;
  193. else if (dd->flags & TDES_FLAGS_CFB16)
  194. valmr |= TDES_MR_CFBS_16b;
  195. else if (dd->flags & TDES_FLAGS_CFB32)
  196. valmr |= TDES_MR_CFBS_32b;
  197. } else if (dd->flags & TDES_FLAGS_OFB) {
  198. valmr |= TDES_MR_OPMOD_OFB;
  199. }
  200. if ((dd->flags & TDES_FLAGS_ENCRYPT) || (dd->flags & TDES_FLAGS_OFB))
  201. valmr |= TDES_MR_CYPHER_ENC;
  202. atmel_tdes_write(dd, TDES_CR, valcr);
  203. atmel_tdes_write(dd, TDES_MR, valmr);
  204. atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key,
  205. dd->ctx->keylen >> 2);
  206. if (((dd->flags & TDES_FLAGS_CBC) || (dd->flags & TDES_FLAGS_CFB) ||
  207. (dd->flags & TDES_FLAGS_OFB)) && dd->req->info) {
  208. atmel_tdes_write_n(dd, TDES_IV1R, dd->req->info, 2);
  209. }
  210. return 0;
  211. }
  212. static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd)
  213. {
  214. int err = 0;
  215. size_t count;
  216. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  217. if (dd->flags & TDES_FLAGS_FAST) {
  218. dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
  219. dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  220. } else {
  221. dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
  222. dd->dma_size, DMA_FROM_DEVICE);
  223. /* copy data */
  224. count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
  225. dd->buf_out, dd->buflen, dd->dma_size, 1);
  226. if (count != dd->dma_size) {
  227. err = -EINVAL;
  228. pr_err("not all data converted: %u\n", count);
  229. }
  230. }
  231. return err;
  232. }
  233. static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
  234. {
  235. int err = -ENOMEM;
  236. dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
  237. dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
  238. dd->buflen = PAGE_SIZE;
  239. dd->buflen &= ~(DES_BLOCK_SIZE - 1);
  240. if (!dd->buf_in || !dd->buf_out) {
  241. dev_err(dd->dev, "unable to alloc pages.\n");
  242. goto err_alloc;
  243. }
  244. /* MAP here */
  245. dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
  246. dd->buflen, DMA_TO_DEVICE);
  247. if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
  248. dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
  249. err = -EINVAL;
  250. goto err_map_in;
  251. }
  252. dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
  253. dd->buflen, DMA_FROM_DEVICE);
  254. if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
  255. dev_err(dd->dev, "dma %d bytes error\n", dd->buflen);
  256. err = -EINVAL;
  257. goto err_map_out;
  258. }
  259. return 0;
  260. err_map_out:
  261. dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
  262. DMA_TO_DEVICE);
  263. err_map_in:
  264. free_page((unsigned long)dd->buf_out);
  265. free_page((unsigned long)dd->buf_in);
  266. err_alloc:
  267. if (err)
  268. pr_err("error: %d\n", err);
  269. return err;
  270. }
  271. static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd)
  272. {
  273. dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
  274. DMA_FROM_DEVICE);
  275. dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
  276. DMA_TO_DEVICE);
  277. free_page((unsigned long)dd->buf_out);
  278. free_page((unsigned long)dd->buf_in);
  279. }
  280. static int atmel_tdes_crypt_dma(struct crypto_tfm *tfm, dma_addr_t dma_addr_in,
  281. dma_addr_t dma_addr_out, int length)
  282. {
  283. struct atmel_tdes_ctx *ctx = crypto_tfm_ctx(tfm);
  284. struct atmel_tdes_dev *dd = ctx->dd;
  285. int len32;
  286. dd->dma_size = length;
  287. if (!(dd->flags & TDES_FLAGS_FAST)) {
  288. dma_sync_single_for_device(dd->dev, dma_addr_in, length,
  289. DMA_TO_DEVICE);
  290. }
  291. if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB8))
  292. len32 = DIV_ROUND_UP(length, sizeof(u8));
  293. else if ((dd->flags & TDES_FLAGS_CFB) && (dd->flags & TDES_FLAGS_CFB16))
  294. len32 = DIV_ROUND_UP(length, sizeof(u16));
  295. else
  296. len32 = DIV_ROUND_UP(length, sizeof(u32));
  297. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
  298. atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
  299. atmel_tdes_write(dd, TDES_TCR, len32);
  300. atmel_tdes_write(dd, TDES_RPR, dma_addr_out);
  301. atmel_tdes_write(dd, TDES_RCR, len32);
  302. /* Enable Interrupt */
  303. atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX);
  304. /* Start DMA transfer */
  305. atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN);
  306. return 0;
  307. }
  308. static int atmel_tdes_crypt_dma_start(struct atmel_tdes_dev *dd)
  309. {
  310. struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
  311. crypto_ablkcipher_reqtfm(dd->req));
  312. int err, fast = 0, in, out;
  313. size_t count;
  314. dma_addr_t addr_in, addr_out;
  315. if (sg_is_last(dd->in_sg) && sg_is_last(dd->out_sg)) {
  316. /* check for alignment */
  317. in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32));
  318. out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32));
  319. fast = in && out;
  320. }
  321. if (fast) {
  322. count = min(dd->total, sg_dma_len(dd->in_sg));
  323. count = min(count, sg_dma_len(dd->out_sg));
  324. if (count != dd->total) {
  325. pr_err("request length != buffer length\n");
  326. return -EINVAL;
  327. }
  328. err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  329. if (!err) {
  330. dev_err(dd->dev, "dma_map_sg() error\n");
  331. return -EINVAL;
  332. }
  333. err = dma_map_sg(dd->dev, dd->out_sg, 1,
  334. DMA_FROM_DEVICE);
  335. if (!err) {
  336. dev_err(dd->dev, "dma_map_sg() error\n");
  337. dma_unmap_sg(dd->dev, dd->in_sg, 1,
  338. DMA_TO_DEVICE);
  339. return -EINVAL;
  340. }
  341. addr_in = sg_dma_address(dd->in_sg);
  342. addr_out = sg_dma_address(dd->out_sg);
  343. dd->flags |= TDES_FLAGS_FAST;
  344. } else {
  345. /* use cache buffers */
  346. count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset,
  347. dd->buf_in, dd->buflen, dd->total, 0);
  348. addr_in = dd->dma_addr_in;
  349. addr_out = dd->dma_addr_out;
  350. dd->flags &= ~TDES_FLAGS_FAST;
  351. }
  352. dd->total -= count;
  353. err = atmel_tdes_crypt_dma(tfm, addr_in, addr_out, count);
  354. if (err) {
  355. dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
  356. dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
  357. }
  358. return err;
  359. }
  360. static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err)
  361. {
  362. struct ablkcipher_request *req = dd->req;
  363. clk_disable_unprepare(dd->iclk);
  364. dd->flags &= ~TDES_FLAGS_BUSY;
  365. req->base.complete(&req->base, err);
  366. }
  367. static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd,
  368. struct ablkcipher_request *req)
  369. {
  370. struct crypto_async_request *async_req, *backlog;
  371. struct atmel_tdes_ctx *ctx;
  372. struct atmel_tdes_reqctx *rctx;
  373. unsigned long flags;
  374. int err, ret = 0;
  375. spin_lock_irqsave(&dd->lock, flags);
  376. if (req)
  377. ret = ablkcipher_enqueue_request(&dd->queue, req);
  378. if (dd->flags & TDES_FLAGS_BUSY) {
  379. spin_unlock_irqrestore(&dd->lock, flags);
  380. return ret;
  381. }
  382. backlog = crypto_get_backlog(&dd->queue);
  383. async_req = crypto_dequeue_request(&dd->queue);
  384. if (async_req)
  385. dd->flags |= TDES_FLAGS_BUSY;
  386. spin_unlock_irqrestore(&dd->lock, flags);
  387. if (!async_req)
  388. return ret;
  389. if (backlog)
  390. backlog->complete(backlog, -EINPROGRESS);
  391. req = ablkcipher_request_cast(async_req);
  392. /* assign new request to device */
  393. dd->req = req;
  394. dd->total = req->nbytes;
  395. dd->in_offset = 0;
  396. dd->in_sg = req->src;
  397. dd->out_offset = 0;
  398. dd->out_sg = req->dst;
  399. rctx = ablkcipher_request_ctx(req);
  400. ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
  401. rctx->mode &= TDES_FLAGS_MODE_MASK;
  402. dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode;
  403. dd->ctx = ctx;
  404. ctx->dd = dd;
  405. err = atmel_tdes_write_ctrl(dd);
  406. if (!err)
  407. err = atmel_tdes_crypt_dma_start(dd);
  408. if (err) {
  409. /* des_task will not finish it, so do it here */
  410. atmel_tdes_finish_req(dd, err);
  411. tasklet_schedule(&dd->queue_task);
  412. }
  413. return ret;
  414. }
  415. static int atmel_tdes_crypt(struct ablkcipher_request *req, unsigned long mode)
  416. {
  417. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(
  418. crypto_ablkcipher_reqtfm(req));
  419. struct atmel_tdes_reqctx *rctx = ablkcipher_request_ctx(req);
  420. struct atmel_tdes_dev *dd;
  421. if (mode & TDES_FLAGS_CFB8) {
  422. if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) {
  423. pr_err("request size is not exact amount of CFB8 blocks\n");
  424. return -EINVAL;
  425. }
  426. } else if (mode & TDES_FLAGS_CFB16) {
  427. if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) {
  428. pr_err("request size is not exact amount of CFB16 blocks\n");
  429. return -EINVAL;
  430. }
  431. } else if (mode & TDES_FLAGS_CFB32) {
  432. if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) {
  433. pr_err("request size is not exact amount of CFB32 blocks\n");
  434. return -EINVAL;
  435. }
  436. } else if (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE)) {
  437. pr_err("request size is not exact amount of DES blocks\n");
  438. return -EINVAL;
  439. }
  440. dd = atmel_tdes_find_dev(ctx);
  441. if (!dd)
  442. return -ENODEV;
  443. rctx->mode = mode;
  444. return atmel_tdes_handle_queue(dd, req);
  445. }
  446. static int atmel_des_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
  447. unsigned int keylen)
  448. {
  449. u32 tmp[DES_EXPKEY_WORDS];
  450. int err;
  451. struct crypto_tfm *ctfm = crypto_ablkcipher_tfm(tfm);
  452. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
  453. if (keylen != DES_KEY_SIZE) {
  454. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  455. return -EINVAL;
  456. }
  457. err = des_ekey(tmp, key);
  458. if (err == 0 && (ctfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
  459. ctfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
  460. return -EINVAL;
  461. }
  462. memcpy(ctx->key, key, keylen);
  463. ctx->keylen = keylen;
  464. return 0;
  465. }
  466. static int atmel_tdes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
  467. unsigned int keylen)
  468. {
  469. struct atmel_tdes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
  470. const char *alg_name;
  471. alg_name = crypto_tfm_alg_name(crypto_ablkcipher_tfm(tfm));
  472. /*
  473. * HW bug in cfb 3-keys mode.
  474. */
  475. if (strstr(alg_name, "cfb") && (keylen != 2*DES_KEY_SIZE)) {
  476. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  477. return -EINVAL;
  478. } else if ((keylen != 2*DES_KEY_SIZE) && (keylen != 3*DES_KEY_SIZE)) {
  479. crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
  480. return -EINVAL;
  481. }
  482. memcpy(ctx->key, key, keylen);
  483. ctx->keylen = keylen;
  484. return 0;
  485. }
  486. static int atmel_tdes_ecb_encrypt(struct ablkcipher_request *req)
  487. {
  488. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT);
  489. }
  490. static int atmel_tdes_ecb_decrypt(struct ablkcipher_request *req)
  491. {
  492. return atmel_tdes_crypt(req, 0);
  493. }
  494. static int atmel_tdes_cbc_encrypt(struct ablkcipher_request *req)
  495. {
  496. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CBC);
  497. }
  498. static int atmel_tdes_cbc_decrypt(struct ablkcipher_request *req)
  499. {
  500. return atmel_tdes_crypt(req, TDES_FLAGS_CBC);
  501. }
  502. static int atmel_tdes_cfb_encrypt(struct ablkcipher_request *req)
  503. {
  504. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB);
  505. }
  506. static int atmel_tdes_cfb_decrypt(struct ablkcipher_request *req)
  507. {
  508. return atmel_tdes_crypt(req, TDES_FLAGS_CFB);
  509. }
  510. static int atmel_tdes_cfb8_encrypt(struct ablkcipher_request *req)
  511. {
  512. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  513. TDES_FLAGS_CFB8);
  514. }
  515. static int atmel_tdes_cfb8_decrypt(struct ablkcipher_request *req)
  516. {
  517. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB8);
  518. }
  519. static int atmel_tdes_cfb16_encrypt(struct ablkcipher_request *req)
  520. {
  521. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  522. TDES_FLAGS_CFB16);
  523. }
  524. static int atmel_tdes_cfb16_decrypt(struct ablkcipher_request *req)
  525. {
  526. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB16);
  527. }
  528. static int atmel_tdes_cfb32_encrypt(struct ablkcipher_request *req)
  529. {
  530. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_CFB |
  531. TDES_FLAGS_CFB32);
  532. }
  533. static int atmel_tdes_cfb32_decrypt(struct ablkcipher_request *req)
  534. {
  535. return atmel_tdes_crypt(req, TDES_FLAGS_CFB | TDES_FLAGS_CFB32);
  536. }
  537. static int atmel_tdes_ofb_encrypt(struct ablkcipher_request *req)
  538. {
  539. return atmel_tdes_crypt(req, TDES_FLAGS_ENCRYPT | TDES_FLAGS_OFB);
  540. }
  541. static int atmel_tdes_ofb_decrypt(struct ablkcipher_request *req)
  542. {
  543. return atmel_tdes_crypt(req, TDES_FLAGS_OFB);
  544. }
  545. static int atmel_tdes_cra_init(struct crypto_tfm *tfm)
  546. {
  547. tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_tdes_reqctx);
  548. return 0;
  549. }
  550. static void atmel_tdes_cra_exit(struct crypto_tfm *tfm)
  551. {
  552. }
  553. static struct crypto_alg tdes_algs[] = {
  554. {
  555. .cra_name = "ecb(des)",
  556. .cra_driver_name = "atmel-ecb-des",
  557. .cra_priority = 100,
  558. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  559. .cra_blocksize = DES_BLOCK_SIZE,
  560. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  561. .cra_alignmask = 0,
  562. .cra_type = &crypto_ablkcipher_type,
  563. .cra_module = THIS_MODULE,
  564. .cra_init = atmel_tdes_cra_init,
  565. .cra_exit = atmel_tdes_cra_exit,
  566. .cra_u.ablkcipher = {
  567. .min_keysize = DES_KEY_SIZE,
  568. .max_keysize = DES_KEY_SIZE,
  569. .setkey = atmel_des_setkey,
  570. .encrypt = atmel_tdes_ecb_encrypt,
  571. .decrypt = atmel_tdes_ecb_decrypt,
  572. }
  573. },
  574. {
  575. .cra_name = "cbc(des)",
  576. .cra_driver_name = "atmel-cbc-des",
  577. .cra_priority = 100,
  578. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  579. .cra_blocksize = DES_BLOCK_SIZE,
  580. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  581. .cra_alignmask = 0,
  582. .cra_type = &crypto_ablkcipher_type,
  583. .cra_module = THIS_MODULE,
  584. .cra_init = atmel_tdes_cra_init,
  585. .cra_exit = atmel_tdes_cra_exit,
  586. .cra_u.ablkcipher = {
  587. .min_keysize = DES_KEY_SIZE,
  588. .max_keysize = DES_KEY_SIZE,
  589. .ivsize = DES_BLOCK_SIZE,
  590. .setkey = atmel_des_setkey,
  591. .encrypt = atmel_tdes_cbc_encrypt,
  592. .decrypt = atmel_tdes_cbc_decrypt,
  593. }
  594. },
  595. {
  596. .cra_name = "cfb(des)",
  597. .cra_driver_name = "atmel-cfb-des",
  598. .cra_priority = 100,
  599. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  600. .cra_blocksize = DES_BLOCK_SIZE,
  601. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  602. .cra_alignmask = 0,
  603. .cra_type = &crypto_ablkcipher_type,
  604. .cra_module = THIS_MODULE,
  605. .cra_init = atmel_tdes_cra_init,
  606. .cra_exit = atmel_tdes_cra_exit,
  607. .cra_u.ablkcipher = {
  608. .min_keysize = DES_KEY_SIZE,
  609. .max_keysize = DES_KEY_SIZE,
  610. .ivsize = DES_BLOCK_SIZE,
  611. .setkey = atmel_des_setkey,
  612. .encrypt = atmel_tdes_cfb_encrypt,
  613. .decrypt = atmel_tdes_cfb_decrypt,
  614. }
  615. },
  616. {
  617. .cra_name = "cfb8(des)",
  618. .cra_driver_name = "atmel-cfb8-des",
  619. .cra_priority = 100,
  620. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  621. .cra_blocksize = CFB8_BLOCK_SIZE,
  622. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  623. .cra_alignmask = 0,
  624. .cra_type = &crypto_ablkcipher_type,
  625. .cra_module = THIS_MODULE,
  626. .cra_init = atmel_tdes_cra_init,
  627. .cra_exit = atmel_tdes_cra_exit,
  628. .cra_u.ablkcipher = {
  629. .min_keysize = DES_KEY_SIZE,
  630. .max_keysize = DES_KEY_SIZE,
  631. .ivsize = DES_BLOCK_SIZE,
  632. .setkey = atmel_des_setkey,
  633. .encrypt = atmel_tdes_cfb8_encrypt,
  634. .decrypt = atmel_tdes_cfb8_decrypt,
  635. }
  636. },
  637. {
  638. .cra_name = "cfb16(des)",
  639. .cra_driver_name = "atmel-cfb16-des",
  640. .cra_priority = 100,
  641. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  642. .cra_blocksize = CFB16_BLOCK_SIZE,
  643. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  644. .cra_alignmask = 0,
  645. .cra_type = &crypto_ablkcipher_type,
  646. .cra_module = THIS_MODULE,
  647. .cra_init = atmel_tdes_cra_init,
  648. .cra_exit = atmel_tdes_cra_exit,
  649. .cra_u.ablkcipher = {
  650. .min_keysize = DES_KEY_SIZE,
  651. .max_keysize = DES_KEY_SIZE,
  652. .ivsize = DES_BLOCK_SIZE,
  653. .setkey = atmel_des_setkey,
  654. .encrypt = atmel_tdes_cfb16_encrypt,
  655. .decrypt = atmel_tdes_cfb16_decrypt,
  656. }
  657. },
  658. {
  659. .cra_name = "cfb32(des)",
  660. .cra_driver_name = "atmel-cfb32-des",
  661. .cra_priority = 100,
  662. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  663. .cra_blocksize = CFB32_BLOCK_SIZE,
  664. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  665. .cra_alignmask = 0,
  666. .cra_type = &crypto_ablkcipher_type,
  667. .cra_module = THIS_MODULE,
  668. .cra_init = atmel_tdes_cra_init,
  669. .cra_exit = atmel_tdes_cra_exit,
  670. .cra_u.ablkcipher = {
  671. .min_keysize = DES_KEY_SIZE,
  672. .max_keysize = DES_KEY_SIZE,
  673. .ivsize = DES_BLOCK_SIZE,
  674. .setkey = atmel_des_setkey,
  675. .encrypt = atmel_tdes_cfb32_encrypt,
  676. .decrypt = atmel_tdes_cfb32_decrypt,
  677. }
  678. },
  679. {
  680. .cra_name = "ofb(des)",
  681. .cra_driver_name = "atmel-ofb-des",
  682. .cra_priority = 100,
  683. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  684. .cra_blocksize = DES_BLOCK_SIZE,
  685. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  686. .cra_alignmask = 0,
  687. .cra_type = &crypto_ablkcipher_type,
  688. .cra_module = THIS_MODULE,
  689. .cra_init = atmel_tdes_cra_init,
  690. .cra_exit = atmel_tdes_cra_exit,
  691. .cra_u.ablkcipher = {
  692. .min_keysize = DES_KEY_SIZE,
  693. .max_keysize = DES_KEY_SIZE,
  694. .ivsize = DES_BLOCK_SIZE,
  695. .setkey = atmel_des_setkey,
  696. .encrypt = atmel_tdes_ofb_encrypt,
  697. .decrypt = atmel_tdes_ofb_decrypt,
  698. }
  699. },
  700. {
  701. .cra_name = "ecb(des3_ede)",
  702. .cra_driver_name = "atmel-ecb-tdes",
  703. .cra_priority = 100,
  704. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  705. .cra_blocksize = DES_BLOCK_SIZE,
  706. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  707. .cra_alignmask = 0,
  708. .cra_type = &crypto_ablkcipher_type,
  709. .cra_module = THIS_MODULE,
  710. .cra_init = atmel_tdes_cra_init,
  711. .cra_exit = atmel_tdes_cra_exit,
  712. .cra_u.ablkcipher = {
  713. .min_keysize = 2 * DES_KEY_SIZE,
  714. .max_keysize = 3 * DES_KEY_SIZE,
  715. .setkey = atmel_tdes_setkey,
  716. .encrypt = atmel_tdes_ecb_encrypt,
  717. .decrypt = atmel_tdes_ecb_decrypt,
  718. }
  719. },
  720. {
  721. .cra_name = "cbc(des3_ede)",
  722. .cra_driver_name = "atmel-cbc-tdes",
  723. .cra_priority = 100,
  724. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  725. .cra_blocksize = DES_BLOCK_SIZE,
  726. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  727. .cra_alignmask = 0,
  728. .cra_type = &crypto_ablkcipher_type,
  729. .cra_module = THIS_MODULE,
  730. .cra_init = atmel_tdes_cra_init,
  731. .cra_exit = atmel_tdes_cra_exit,
  732. .cra_u.ablkcipher = {
  733. .min_keysize = 2*DES_KEY_SIZE,
  734. .max_keysize = 3*DES_KEY_SIZE,
  735. .ivsize = DES_BLOCK_SIZE,
  736. .setkey = atmel_tdes_setkey,
  737. .encrypt = atmel_tdes_cbc_encrypt,
  738. .decrypt = atmel_tdes_cbc_decrypt,
  739. }
  740. },
  741. {
  742. .cra_name = "cfb(des3_ede)",
  743. .cra_driver_name = "atmel-cfb-tdes",
  744. .cra_priority = 100,
  745. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  746. .cra_blocksize = DES_BLOCK_SIZE,
  747. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  748. .cra_alignmask = 0,
  749. .cra_type = &crypto_ablkcipher_type,
  750. .cra_module = THIS_MODULE,
  751. .cra_init = atmel_tdes_cra_init,
  752. .cra_exit = atmel_tdes_cra_exit,
  753. .cra_u.ablkcipher = {
  754. .min_keysize = 2*DES_KEY_SIZE,
  755. .max_keysize = 2*DES_KEY_SIZE,
  756. .ivsize = DES_BLOCK_SIZE,
  757. .setkey = atmel_tdes_setkey,
  758. .encrypt = atmel_tdes_cfb_encrypt,
  759. .decrypt = atmel_tdes_cfb_decrypt,
  760. }
  761. },
  762. {
  763. .cra_name = "cfb8(des3_ede)",
  764. .cra_driver_name = "atmel-cfb8-tdes",
  765. .cra_priority = 100,
  766. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  767. .cra_blocksize = CFB8_BLOCK_SIZE,
  768. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  769. .cra_alignmask = 0,
  770. .cra_type = &crypto_ablkcipher_type,
  771. .cra_module = THIS_MODULE,
  772. .cra_init = atmel_tdes_cra_init,
  773. .cra_exit = atmel_tdes_cra_exit,
  774. .cra_u.ablkcipher = {
  775. .min_keysize = 2*DES_KEY_SIZE,
  776. .max_keysize = 2*DES_KEY_SIZE,
  777. .ivsize = DES_BLOCK_SIZE,
  778. .setkey = atmel_tdes_setkey,
  779. .encrypt = atmel_tdes_cfb8_encrypt,
  780. .decrypt = atmel_tdes_cfb8_decrypt,
  781. }
  782. },
  783. {
  784. .cra_name = "cfb16(des3_ede)",
  785. .cra_driver_name = "atmel-cfb16-tdes",
  786. .cra_priority = 100,
  787. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  788. .cra_blocksize = CFB16_BLOCK_SIZE,
  789. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  790. .cra_alignmask = 0,
  791. .cra_type = &crypto_ablkcipher_type,
  792. .cra_module = THIS_MODULE,
  793. .cra_init = atmel_tdes_cra_init,
  794. .cra_exit = atmel_tdes_cra_exit,
  795. .cra_u.ablkcipher = {
  796. .min_keysize = 2*DES_KEY_SIZE,
  797. .max_keysize = 2*DES_KEY_SIZE,
  798. .ivsize = DES_BLOCK_SIZE,
  799. .setkey = atmel_tdes_setkey,
  800. .encrypt = atmel_tdes_cfb16_encrypt,
  801. .decrypt = atmel_tdes_cfb16_decrypt,
  802. }
  803. },
  804. {
  805. .cra_name = "cfb32(des3_ede)",
  806. .cra_driver_name = "atmel-cfb32-tdes",
  807. .cra_priority = 100,
  808. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  809. .cra_blocksize = CFB32_BLOCK_SIZE,
  810. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  811. .cra_alignmask = 0,
  812. .cra_type = &crypto_ablkcipher_type,
  813. .cra_module = THIS_MODULE,
  814. .cra_init = atmel_tdes_cra_init,
  815. .cra_exit = atmel_tdes_cra_exit,
  816. .cra_u.ablkcipher = {
  817. .min_keysize = 2*DES_KEY_SIZE,
  818. .max_keysize = 2*DES_KEY_SIZE,
  819. .ivsize = DES_BLOCK_SIZE,
  820. .setkey = atmel_tdes_setkey,
  821. .encrypt = atmel_tdes_cfb32_encrypt,
  822. .decrypt = atmel_tdes_cfb32_decrypt,
  823. }
  824. },
  825. {
  826. .cra_name = "ofb(des3_ede)",
  827. .cra_driver_name = "atmel-ofb-tdes",
  828. .cra_priority = 100,
  829. .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
  830. .cra_blocksize = DES_BLOCK_SIZE,
  831. .cra_ctxsize = sizeof(struct atmel_tdes_ctx),
  832. .cra_alignmask = 0,
  833. .cra_type = &crypto_ablkcipher_type,
  834. .cra_module = THIS_MODULE,
  835. .cra_init = atmel_tdes_cra_init,
  836. .cra_exit = atmel_tdes_cra_exit,
  837. .cra_u.ablkcipher = {
  838. .min_keysize = 2*DES_KEY_SIZE,
  839. .max_keysize = 3*DES_KEY_SIZE,
  840. .ivsize = DES_BLOCK_SIZE,
  841. .setkey = atmel_tdes_setkey,
  842. .encrypt = atmel_tdes_ofb_encrypt,
  843. .decrypt = atmel_tdes_ofb_decrypt,
  844. }
  845. },
  846. };
  847. static void atmel_tdes_queue_task(unsigned long data)
  848. {
  849. struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data;
  850. atmel_tdes_handle_queue(dd, NULL);
  851. }
  852. static void atmel_tdes_done_task(unsigned long data)
  853. {
  854. struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data;
  855. int err;
  856. err = atmel_tdes_crypt_dma_stop(dd);
  857. err = dd->err ? : err;
  858. if (dd->total && !err) {
  859. err = atmel_tdes_crypt_dma_start(dd);
  860. if (!err)
  861. return;
  862. }
  863. atmel_tdes_finish_req(dd, err);
  864. atmel_tdes_handle_queue(dd, NULL);
  865. }
  866. static irqreturn_t atmel_tdes_irq(int irq, void *dev_id)
  867. {
  868. struct atmel_tdes_dev *tdes_dd = dev_id;
  869. u32 reg;
  870. reg = atmel_tdes_read(tdes_dd, TDES_ISR);
  871. if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) {
  872. atmel_tdes_write(tdes_dd, TDES_IDR, reg);
  873. if (TDES_FLAGS_BUSY & tdes_dd->flags)
  874. tasklet_schedule(&tdes_dd->done_task);
  875. else
  876. dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n");
  877. return IRQ_HANDLED;
  878. }
  879. return IRQ_NONE;
  880. }
  881. static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd)
  882. {
  883. int i;
  884. for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
  885. crypto_unregister_alg(&tdes_algs[i]);
  886. }
  887. static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd)
  888. {
  889. int err, i, j;
  890. for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
  891. err = crypto_register_alg(&tdes_algs[i]);
  892. if (err)
  893. goto err_tdes_algs;
  894. }
  895. return 0;
  896. err_tdes_algs:
  897. for (j = 0; j < i; j++)
  898. crypto_unregister_alg(&tdes_algs[j]);
  899. return err;
  900. }
  901. static int atmel_tdes_probe(struct platform_device *pdev)
  902. {
  903. struct atmel_tdes_dev *tdes_dd;
  904. struct device *dev = &pdev->dev;
  905. struct resource *tdes_res;
  906. unsigned long tdes_phys_size;
  907. int err;
  908. tdes_dd = kzalloc(sizeof(struct atmel_tdes_dev), GFP_KERNEL);
  909. if (tdes_dd == NULL) {
  910. dev_err(dev, "unable to alloc data struct.\n");
  911. err = -ENOMEM;
  912. goto tdes_dd_err;
  913. }
  914. tdes_dd->dev = dev;
  915. platform_set_drvdata(pdev, tdes_dd);
  916. INIT_LIST_HEAD(&tdes_dd->list);
  917. tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task,
  918. (unsigned long)tdes_dd);
  919. tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task,
  920. (unsigned long)tdes_dd);
  921. crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH);
  922. tdes_dd->irq = -1;
  923. /* Get the base address */
  924. tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  925. if (!tdes_res) {
  926. dev_err(dev, "no MEM resource info\n");
  927. err = -ENODEV;
  928. goto res_err;
  929. }
  930. tdes_dd->phys_base = tdes_res->start;
  931. tdes_phys_size = resource_size(tdes_res);
  932. /* Get the IRQ */
  933. tdes_dd->irq = platform_get_irq(pdev, 0);
  934. if (tdes_dd->irq < 0) {
  935. dev_err(dev, "no IRQ resource info\n");
  936. err = tdes_dd->irq;
  937. goto res_err;
  938. }
  939. err = request_irq(tdes_dd->irq, atmel_tdes_irq, IRQF_SHARED,
  940. "atmel-tdes", tdes_dd);
  941. if (err) {
  942. dev_err(dev, "unable to request tdes irq.\n");
  943. goto tdes_irq_err;
  944. }
  945. /* Initializing the clock */
  946. tdes_dd->iclk = clk_get(&pdev->dev, NULL);
  947. if (IS_ERR(tdes_dd->iclk)) {
  948. dev_err(dev, "clock intialization failed.\n");
  949. err = PTR_ERR(tdes_dd->iclk);
  950. goto clk_err;
  951. }
  952. tdes_dd->io_base = ioremap(tdes_dd->phys_base, tdes_phys_size);
  953. if (!tdes_dd->io_base) {
  954. dev_err(dev, "can't ioremap\n");
  955. err = -ENOMEM;
  956. goto tdes_io_err;
  957. }
  958. err = atmel_tdes_dma_init(tdes_dd);
  959. if (err)
  960. goto err_tdes_dma;
  961. spin_lock(&atmel_tdes.lock);
  962. list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list);
  963. spin_unlock(&atmel_tdes.lock);
  964. err = atmel_tdes_register_algs(tdes_dd);
  965. if (err)
  966. goto err_algs;
  967. dev_info(dev, "Atmel DES/TDES\n");
  968. return 0;
  969. err_algs:
  970. spin_lock(&atmel_tdes.lock);
  971. list_del(&tdes_dd->list);
  972. spin_unlock(&atmel_tdes.lock);
  973. atmel_tdes_dma_cleanup(tdes_dd);
  974. err_tdes_dma:
  975. iounmap(tdes_dd->io_base);
  976. tdes_io_err:
  977. clk_put(tdes_dd->iclk);
  978. clk_err:
  979. free_irq(tdes_dd->irq, tdes_dd);
  980. tdes_irq_err:
  981. res_err:
  982. tasklet_kill(&tdes_dd->done_task);
  983. tasklet_kill(&tdes_dd->queue_task);
  984. kfree(tdes_dd);
  985. tdes_dd = NULL;
  986. tdes_dd_err:
  987. dev_err(dev, "initialization failed.\n");
  988. return err;
  989. }
  990. static int atmel_tdes_remove(struct platform_device *pdev)
  991. {
  992. static struct atmel_tdes_dev *tdes_dd;
  993. tdes_dd = platform_get_drvdata(pdev);
  994. if (!tdes_dd)
  995. return -ENODEV;
  996. spin_lock(&atmel_tdes.lock);
  997. list_del(&tdes_dd->list);
  998. spin_unlock(&atmel_tdes.lock);
  999. atmel_tdes_unregister_algs(tdes_dd);
  1000. tasklet_kill(&tdes_dd->done_task);
  1001. tasklet_kill(&tdes_dd->queue_task);
  1002. atmel_tdes_dma_cleanup(tdes_dd);
  1003. iounmap(tdes_dd->io_base);
  1004. clk_put(tdes_dd->iclk);
  1005. if (tdes_dd->irq >= 0)
  1006. free_irq(tdes_dd->irq, tdes_dd);
  1007. kfree(tdes_dd);
  1008. tdes_dd = NULL;
  1009. return 0;
  1010. }
  1011. static struct platform_driver atmel_tdes_driver = {
  1012. .probe = atmel_tdes_probe,
  1013. .remove = atmel_tdes_remove,
  1014. .driver = {
  1015. .name = "atmel_tdes",
  1016. .owner = THIS_MODULE,
  1017. },
  1018. };
  1019. module_platform_driver(atmel_tdes_driver);
  1020. MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support.");
  1021. MODULE_LICENSE("GPL v2");
  1022. MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");