clk.c 2.0 KB

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/clkdev.h>
  19. #include <linux/clk-provider.h>
  20. #define SOCFPGA_OSC1_CLK 10000000
  21. #define SOCFPGA_MPU_CLK 800000000
  22. #define SOCFPGA_MAIN_QSPI_CLK 432000000
  23. #define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
  24. #define SOCFPGA_S2F_USR_CLK 125000000
  25. void __init socfpga_init_clocks(void)
  26. {
  27. struct clk *clk;
  28. clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
  29. clk_register_clkdev(clk, "osc1_clk", NULL);
  30. clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
  31. clk_register_clkdev(clk, "mpu_clk", NULL);
  32. clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
  33. clk_register_clkdev(clk, "main_clk", NULL);
  34. clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
  35. clk_register_clkdev(clk, "dbg_base_clk", NULL);
  36. clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
  37. clk_register_clkdev(clk, "main_qspi_clk", NULL);
  38. clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
  39. clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
  40. clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
  41. clk_register_clkdev(clk, "s2f_usr_clk", NULL);
  42. }