processor_64.h 7.6 KB

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  1. /*
  2. * include/asm/processor.h
  3. *
  4. * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
  5. */
  6. #ifndef __ASM_SPARC64_PROCESSOR_H
  7. #define __ASM_SPARC64_PROCESSOR_H
  8. /*
  9. * Sparc64 implementation of macro that returns current
  10. * instruction pointer ("program counter").
  11. */
  12. #define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
  13. #include <asm/asi.h>
  14. #include <asm/pstate.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/page.h>
  17. /* Don't hold the runqueue lock over context switch */
  18. #define __ARCH_WANT_UNLOCKED_CTXSW
  19. /* The sparc has no problems with write protection */
  20. #define wp_works_ok 1
  21. #define wp_works_ok__is_a_macro /* for versions in ksyms.c */
  22. /*
  23. * User lives in his very own context, and cannot reference us. Note
  24. * that TASK_SIZE is a misnomer, it really gives maximum user virtual
  25. * address that the kernel will allocate out.
  26. *
  27. * XXX No longer using virtual page tables, kill this upper limit...
  28. */
  29. #define VA_BITS 44
  30. #ifndef __ASSEMBLY__
  31. #define VPTE_SIZE (1UL << (VA_BITS - PAGE_SHIFT + 3))
  32. #else
  33. #define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
  34. #endif
  35. #define TASK_SIZE_OF(tsk) \
  36. (test_tsk_thread_flag(tsk,TIF_32BIT) ? \
  37. (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
  38. #define TASK_SIZE \
  39. (test_thread_flag(TIF_32BIT) ? \
  40. (1UL << 32UL) : ((unsigned long)-VPTE_SIZE))
  41. #ifdef __KERNEL__
  42. #define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
  43. #define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
  44. #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
  45. STACK_TOP32 : STACK_TOP64)
  46. #define STACK_TOP_MAX STACK_TOP64
  47. #endif
  48. #ifndef __ASSEMBLY__
  49. typedef struct {
  50. unsigned char seg;
  51. } mm_segment_t;
  52. /* The Sparc processor specific thread struct. */
  53. /* XXX This should die, everything can go into thread_info now. */
  54. struct thread_struct {
  55. #ifdef CONFIG_DEBUG_SPINLOCK
  56. /* How many spinlocks held by this thread.
  57. * Used with spin lock debugging to catch tasks
  58. * sleeping illegally with locks held.
  59. */
  60. int smp_lock_count;
  61. unsigned int smp_lock_pc;
  62. #else
  63. int dummy; /* f'in gcc bug... */
  64. #endif
  65. };
  66. #endif /* !(__ASSEMBLY__) */
  67. #ifndef CONFIG_DEBUG_SPINLOCK
  68. #define INIT_THREAD { \
  69. 0, \
  70. }
  71. #else /* CONFIG_DEBUG_SPINLOCK */
  72. #define INIT_THREAD { \
  73. /* smp_lock_count, smp_lock_pc, */ \
  74. 0, 0, \
  75. }
  76. #endif /* !(CONFIG_DEBUG_SPINLOCK) */
  77. #ifndef __ASSEMBLY__
  78. #include <linux/types.h>
  79. #include <asm/fpumacro.h>
  80. /* Return saved PC of a blocked thread. */
  81. struct task_struct;
  82. extern unsigned long thread_saved_pc(struct task_struct *);
  83. /* On Uniprocessor, even in RMO processes see TSO semantics */
  84. #ifdef CONFIG_SMP
  85. #define TSTATE_INITIAL_MM TSTATE_TSO
  86. #else
  87. #define TSTATE_INITIAL_MM TSTATE_RMO
  88. #endif
  89. /* Do necessary setup to start up a newly executed thread. */
  90. #define start_thread(regs, pc, sp) \
  91. do { \
  92. unsigned long __asi = ASI_PNF; \
  93. regs->tstate = (regs->tstate & (TSTATE_CWP)) | (TSTATE_INITIAL_MM|TSTATE_IE) | (__asi << 24UL); \
  94. regs->tpc = ((pc & (~3)) - 4); \
  95. regs->tnpc = regs->tpc + 4; \
  96. regs->y = 0; \
  97. set_thread_wstate(1 << 3); \
  98. if (current_thread_info()->utraps) { \
  99. if (*(current_thread_info()->utraps) < 2) \
  100. kfree(current_thread_info()->utraps); \
  101. else \
  102. (*(current_thread_info()->utraps))--; \
  103. current_thread_info()->utraps = NULL; \
  104. } \
  105. __asm__ __volatile__( \
  106. "stx %%g0, [%0 + %2 + 0x00]\n\t" \
  107. "stx %%g0, [%0 + %2 + 0x08]\n\t" \
  108. "stx %%g0, [%0 + %2 + 0x10]\n\t" \
  109. "stx %%g0, [%0 + %2 + 0x18]\n\t" \
  110. "stx %%g0, [%0 + %2 + 0x20]\n\t" \
  111. "stx %%g0, [%0 + %2 + 0x28]\n\t" \
  112. "stx %%g0, [%0 + %2 + 0x30]\n\t" \
  113. "stx %%g0, [%0 + %2 + 0x38]\n\t" \
  114. "stx %%g0, [%0 + %2 + 0x40]\n\t" \
  115. "stx %%g0, [%0 + %2 + 0x48]\n\t" \
  116. "stx %%g0, [%0 + %2 + 0x50]\n\t" \
  117. "stx %%g0, [%0 + %2 + 0x58]\n\t" \
  118. "stx %%g0, [%0 + %2 + 0x60]\n\t" \
  119. "stx %%g0, [%0 + %2 + 0x68]\n\t" \
  120. "stx %1, [%0 + %2 + 0x70]\n\t" \
  121. "stx %%g0, [%0 + %2 + 0x78]\n\t" \
  122. "wrpr %%g0, (1 << 3), %%wstate\n\t" \
  123. : \
  124. : "r" (regs), "r" (sp - sizeof(struct reg_window) - STACK_BIAS), \
  125. "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
  126. fprs_write(0); \
  127. current_thread_info()->xfsr[0] = 0; \
  128. current_thread_info()->fpsaved[0] = 0; \
  129. regs->tstate &= ~TSTATE_PEF; \
  130. } while (0)
  131. #define start_thread32(regs, pc, sp) \
  132. do { \
  133. unsigned long __asi = ASI_PNF; \
  134. pc &= 0x00000000ffffffffUL; \
  135. sp &= 0x00000000ffffffffUL; \
  136. regs->tstate = (regs->tstate & (TSTATE_CWP))|(TSTATE_INITIAL_MM|TSTATE_IE|TSTATE_AM) | (__asi << 24UL); \
  137. regs->tpc = ((pc & (~3)) - 4); \
  138. regs->tnpc = regs->tpc + 4; \
  139. regs->y = 0; \
  140. set_thread_wstate(2 << 3); \
  141. if (current_thread_info()->utraps) { \
  142. if (*(current_thread_info()->utraps) < 2) \
  143. kfree(current_thread_info()->utraps); \
  144. else \
  145. (*(current_thread_info()->utraps))--; \
  146. current_thread_info()->utraps = NULL; \
  147. } \
  148. __asm__ __volatile__( \
  149. "stx %%g0, [%0 + %2 + 0x00]\n\t" \
  150. "stx %%g0, [%0 + %2 + 0x08]\n\t" \
  151. "stx %%g0, [%0 + %2 + 0x10]\n\t" \
  152. "stx %%g0, [%0 + %2 + 0x18]\n\t" \
  153. "stx %%g0, [%0 + %2 + 0x20]\n\t" \
  154. "stx %%g0, [%0 + %2 + 0x28]\n\t" \
  155. "stx %%g0, [%0 + %2 + 0x30]\n\t" \
  156. "stx %%g0, [%0 + %2 + 0x38]\n\t" \
  157. "stx %%g0, [%0 + %2 + 0x40]\n\t" \
  158. "stx %%g0, [%0 + %2 + 0x48]\n\t" \
  159. "stx %%g0, [%0 + %2 + 0x50]\n\t" \
  160. "stx %%g0, [%0 + %2 + 0x58]\n\t" \
  161. "stx %%g0, [%0 + %2 + 0x60]\n\t" \
  162. "stx %%g0, [%0 + %2 + 0x68]\n\t" \
  163. "stx %1, [%0 + %2 + 0x70]\n\t" \
  164. "stx %%g0, [%0 + %2 + 0x78]\n\t" \
  165. "wrpr %%g0, (2 << 3), %%wstate\n\t" \
  166. : \
  167. : "r" (regs), "r" (sp - sizeof(struct reg_window32)), \
  168. "i" ((const unsigned long)(&((struct pt_regs *)0)->u_regs[0]))); \
  169. fprs_write(0); \
  170. current_thread_info()->xfsr[0] = 0; \
  171. current_thread_info()->fpsaved[0] = 0; \
  172. regs->tstate &= ~TSTATE_PEF; \
  173. } while (0)
  174. /* Free all resources held by a thread. */
  175. #define release_thread(tsk) do { } while (0)
  176. extern unsigned long get_wchan(struct task_struct *task);
  177. #define task_pt_regs(tsk) (task_thread_info(tsk)->kregs)
  178. #define KSTK_EIP(tsk) (task_pt_regs(tsk)->tpc)
  179. #define KSTK_ESP(tsk) (task_pt_regs(tsk)->u_regs[UREG_FP])
  180. /* Please see the commentary in asm/backoff.h for a description of
  181. * what these instructions are doing and how they have been choosen.
  182. * To make a long story short, we are trying to yield the current cpu
  183. * strand during busy loops.
  184. */
  185. #define cpu_relax() asm volatile("\n99:\n\t" \
  186. "rd %%ccr, %%g0\n\t" \
  187. "rd %%ccr, %%g0\n\t" \
  188. "rd %%ccr, %%g0\n\t" \
  189. ".section .pause_3insn_patch,\"ax\"\n\t"\
  190. ".word 99b\n\t" \
  191. "wr %%g0, 128, %%asr27\n\t" \
  192. "nop\n\t" \
  193. "nop\n\t" \
  194. ".previous" \
  195. ::: "memory")
  196. /* Prefetch support. This is tuned for UltraSPARC-III and later.
  197. * UltraSPARC-I will treat these as nops, and UltraSPARC-II has
  198. * a shallower prefetch queue than later chips.
  199. */
  200. #define ARCH_HAS_PREFETCH
  201. #define ARCH_HAS_PREFETCHW
  202. #define ARCH_HAS_SPINLOCK_PREFETCH
  203. static inline void prefetch(const void *x)
  204. {
  205. /* We do not use the read prefetch mnemonic because that
  206. * prefetches into the prefetch-cache which only is accessible
  207. * by floating point operations in UltraSPARC-III and later.
  208. * By contrast, "#one_write" prefetches into the L2 cache
  209. * in shared state.
  210. */
  211. __asm__ __volatile__("prefetch [%0], #one_write"
  212. : /* no outputs */
  213. : "r" (x));
  214. }
  215. static inline void prefetchw(const void *x)
  216. {
  217. /* The most optimal prefetch to use for writes is
  218. * "#n_writes". This brings the cacheline into the
  219. * L2 cache in "owned" state.
  220. */
  221. __asm__ __volatile__("prefetch [%0], #n_writes"
  222. : /* no outputs */
  223. : "r" (x));
  224. }
  225. #define spin_lock_prefetch(x) prefetchw(x)
  226. #define HAVE_ARCH_PICK_MMAP_LAYOUT
  227. #endif /* !(__ASSEMBLY__) */
  228. #endif /* !(__ASM_SPARC64_PROCESSOR_H) */