barrier.h 918 B

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  1. /*
  2. * Copyright IBM Corp. 1999, 2009
  3. *
  4. * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  5. */
  6. #ifndef __ASM_BARRIER_H
  7. #define __ASM_BARRIER_H
  8. /*
  9. * Force strict CPU ordering.
  10. * And yes, this is required on UP too when we're talking
  11. * to devices.
  12. */
  13. #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
  14. /* Fast-BCR without checkpoint synchronization */
  15. #define mb() do { asm volatile("bcr 14,0" : : : "memory"); } while (0)
  16. #else
  17. #define mb() do { asm volatile("bcr 15,0" : : : "memory"); } while (0)
  18. #endif
  19. #define rmb() mb()
  20. #define wmb() mb()
  21. #define read_barrier_depends() do { } while(0)
  22. #define smp_mb() mb()
  23. #define smp_rmb() rmb()
  24. #define smp_wmb() wmb()
  25. #define smp_read_barrier_depends() read_barrier_depends()
  26. #define smp_mb__before_clear_bit() smp_mb()
  27. #define smp_mb__after_clear_bit() smp_mb()
  28. #define set_mb(var, value) do { var = value; mb(); } while (0)
  29. #endif /* __ASM_BARRIER_H */