smp.c 4.3 KB

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  1. /*
  2. * SMP support for PowerNV machines.
  3. *
  4. * Copyright 2011 IBM Corp.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/sched.h>
  14. #include <linux/smp.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/init.h>
  18. #include <linux/spinlock.h>
  19. #include <linux/cpu.h>
  20. #include <asm/irq.h>
  21. #include <asm/smp.h>
  22. #include <asm/paca.h>
  23. #include <asm/machdep.h>
  24. #include <asm/cputable.h>
  25. #include <asm/firmware.h>
  26. #include <asm/rtas.h>
  27. #include <asm/vdso_datapage.h>
  28. #include <asm/cputhreads.h>
  29. #include <asm/xics.h>
  30. #include <asm/opal.h>
  31. #include "powernv.h"
  32. #ifdef DEBUG
  33. #include <asm/udbg.h>
  34. #define DBG(fmt...) udbg_printf(fmt)
  35. #else
  36. #define DBG(fmt...)
  37. #endif
  38. static void __cpuinit pnv_smp_setup_cpu(int cpu)
  39. {
  40. if (cpu != boot_cpuid)
  41. xics_setup_cpu();
  42. }
  43. static int pnv_smp_cpu_bootable(unsigned int nr)
  44. {
  45. /* Special case - we inhibit secondary thread startup
  46. * during boot if the user requests it.
  47. */
  48. if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
  49. if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
  50. return 0;
  51. if (smt_enabled_at_boot
  52. && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
  53. return 0;
  54. }
  55. return 1;
  56. }
  57. int pnv_smp_kick_cpu(int nr)
  58. {
  59. unsigned int pcpu = get_hard_smp_processor_id(nr);
  60. unsigned long start_here = __pa(*((unsigned long *)
  61. generic_secondary_smp_init));
  62. long rc;
  63. BUG_ON(nr < 0 || nr >= NR_CPUS);
  64. /* On OPAL v2 the CPU are still spinning inside OPAL itself,
  65. * get them back now
  66. */
  67. if (!paca[nr].cpu_start && firmware_has_feature(FW_FEATURE_OPALv2)) {
  68. pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
  69. rc = opal_start_cpu(pcpu, start_here);
  70. if (rc != OPAL_SUCCESS)
  71. pr_warn("OPAL Error %ld starting CPU %d\n",
  72. rc, nr);
  73. }
  74. return smp_generic_kick_cpu(nr);
  75. }
  76. #ifdef CONFIG_HOTPLUG_CPU
  77. static int pnv_smp_cpu_disable(void)
  78. {
  79. int cpu = smp_processor_id();
  80. /* This is identical to pSeries... might consolidate by
  81. * moving migrate_irqs_away to a ppc_md with default to
  82. * the generic fixup_irqs. --BenH.
  83. */
  84. set_cpu_online(cpu, false);
  85. vdso_data->processorCount--;
  86. if (cpu == boot_cpuid)
  87. boot_cpuid = cpumask_any(cpu_online_mask);
  88. xics_migrate_irqs_away();
  89. return 0;
  90. }
  91. static void pnv_smp_cpu_kill_self(void)
  92. {
  93. unsigned int cpu;
  94. /* Standard hot unplug procedure */
  95. local_irq_disable();
  96. idle_task_exit();
  97. current->active_mm = NULL; /* for sanity */
  98. cpu = smp_processor_id();
  99. DBG("CPU%d offline\n", cpu);
  100. generic_set_cpu_dead(cpu);
  101. smp_wmb();
  102. /* We don't want to take decrementer interrupts while we are offline,
  103. * so clear LPCR:PECE1. We keep PECE2 enabled.
  104. */
  105. mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1);
  106. while (!generic_check_cpu_restart(cpu)) {
  107. power7_nap();
  108. if (!generic_check_cpu_restart(cpu)) {
  109. DBG("CPU%d Unexpected exit while offline !\n", cpu);
  110. /* We may be getting an IPI, so we re-enable
  111. * interrupts to process it, it will be ignored
  112. * since we aren't online (hopefully)
  113. */
  114. local_irq_enable();
  115. local_irq_disable();
  116. }
  117. }
  118. mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) | LPCR_PECE1);
  119. DBG("CPU%d coming online...\n", cpu);
  120. }
  121. #endif /* CONFIG_HOTPLUG_CPU */
  122. static struct smp_ops_t pnv_smp_ops = {
  123. .message_pass = smp_muxed_ipi_message_pass,
  124. .cause_ipi = NULL, /* Filled at runtime by xics_smp_probe() */
  125. .probe = xics_smp_probe,
  126. .kick_cpu = pnv_smp_kick_cpu,
  127. .setup_cpu = pnv_smp_setup_cpu,
  128. .cpu_bootable = pnv_smp_cpu_bootable,
  129. #ifdef CONFIG_HOTPLUG_CPU
  130. .cpu_disable = pnv_smp_cpu_disable,
  131. .cpu_die = generic_cpu_die,
  132. #endif /* CONFIG_HOTPLUG_CPU */
  133. };
  134. /* This is called very early during platform setup_arch */
  135. void __init pnv_smp_init(void)
  136. {
  137. smp_ops = &pnv_smp_ops;
  138. /* XXX We don't yet have a proper entry point from HAL, for
  139. * now we rely on kexec-style entry from BML
  140. */
  141. #ifdef CONFIG_PPC_RTAS
  142. /* Non-lpar has additional take/give timebase */
  143. if (rtas_token("freeze-time-base") != RTAS_UNKNOWN_SERVICE) {
  144. smp_ops->give_timebase = rtas_give_timebase;
  145. smp_ops->take_timebase = rtas_take_timebase;
  146. }
  147. #endif /* CONFIG_PPC_RTAS */
  148. #ifdef CONFIG_HOTPLUG_CPU
  149. ppc_md.cpu_die = pnv_smp_cpu_kill_self;
  150. #endif
  151. }