book3s_hv_ras.c 4.0 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * Copyright 2012 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  7. */
  8. #include <linux/types.h>
  9. #include <linux/string.h>
  10. #include <linux/kvm.h>
  11. #include <linux/kvm_host.h>
  12. #include <linux/kernel.h>
  13. #include <asm/opal.h>
  14. /* SRR1 bits for machine check on POWER7 */
  15. #define SRR1_MC_LDSTERR (1ul << (63-42))
  16. #define SRR1_MC_IFETCH_SH (63-45)
  17. #define SRR1_MC_IFETCH_MASK 0x7
  18. #define SRR1_MC_IFETCH_SLBPAR 2 /* SLB parity error */
  19. #define SRR1_MC_IFETCH_SLBMULTI 3 /* SLB multi-hit */
  20. #define SRR1_MC_IFETCH_SLBPARMULTI 4 /* SLB parity + multi-hit */
  21. #define SRR1_MC_IFETCH_TLBMULTI 5 /* I-TLB multi-hit */
  22. /* DSISR bits for machine check on POWER7 */
  23. #define DSISR_MC_DERAT_MULTI 0x800 /* D-ERAT multi-hit */
  24. #define DSISR_MC_TLB_MULTI 0x400 /* D-TLB multi-hit */
  25. #define DSISR_MC_SLB_PARITY 0x100 /* SLB parity error */
  26. #define DSISR_MC_SLB_MULTI 0x080 /* SLB multi-hit */
  27. #define DSISR_MC_SLB_PARMULTI 0x040 /* SLB parity + multi-hit */
  28. /* POWER7 SLB flush and reload */
  29. static void reload_slb(struct kvm_vcpu *vcpu)
  30. {
  31. struct slb_shadow *slb;
  32. unsigned long i, n;
  33. /* First clear out SLB */
  34. asm volatile("slbmte %0,%0; slbia" : : "r" (0));
  35. /* Do they have an SLB shadow buffer registered? */
  36. slb = vcpu->arch.slb_shadow.pinned_addr;
  37. if (!slb)
  38. return;
  39. /* Sanity check */
  40. n = min_t(u32, slb->persistent, SLB_MIN_SIZE);
  41. if ((void *) &slb->save_area[n] > vcpu->arch.slb_shadow.pinned_end)
  42. return;
  43. /* Load up the SLB from that */
  44. for (i = 0; i < n; ++i) {
  45. unsigned long rb = slb->save_area[i].esid;
  46. unsigned long rs = slb->save_area[i].vsid;
  47. rb = (rb & ~0xFFFul) | i; /* insert entry number */
  48. asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
  49. }
  50. }
  51. /* POWER7 TLB flush */
  52. static void flush_tlb_power7(struct kvm_vcpu *vcpu)
  53. {
  54. unsigned long i, rb;
  55. rb = TLBIEL_INVAL_SET_LPID;
  56. for (i = 0; i < POWER7_TLB_SETS; ++i) {
  57. asm volatile("tlbiel %0" : : "r" (rb));
  58. rb += 1 << TLBIEL_INVAL_SET_SHIFT;
  59. }
  60. }
  61. /*
  62. * On POWER7, see if we can handle a machine check that occurred inside
  63. * the guest in real mode, without switching to the host partition.
  64. *
  65. * Returns: 0 => exit guest, 1 => deliver machine check to guest
  66. */
  67. static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
  68. {
  69. unsigned long srr1 = vcpu->arch.shregs.msr;
  70. #ifdef CONFIG_PPC_POWERNV
  71. struct opal_machine_check_event *opal_evt;
  72. #endif
  73. long handled = 1;
  74. if (srr1 & SRR1_MC_LDSTERR) {
  75. /* error on load/store */
  76. unsigned long dsisr = vcpu->arch.shregs.dsisr;
  77. if (dsisr & (DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI |
  78. DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI)) {
  79. /* flush and reload SLB; flushes D-ERAT too */
  80. reload_slb(vcpu);
  81. dsisr &= ~(DSISR_MC_SLB_PARMULTI | DSISR_MC_SLB_MULTI |
  82. DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI);
  83. }
  84. if (dsisr & DSISR_MC_TLB_MULTI) {
  85. flush_tlb_power7(vcpu);
  86. dsisr &= ~DSISR_MC_TLB_MULTI;
  87. }
  88. /* Any other errors we don't understand? */
  89. if (dsisr & 0xffffffffUL)
  90. handled = 0;
  91. }
  92. switch ((srr1 >> SRR1_MC_IFETCH_SH) & SRR1_MC_IFETCH_MASK) {
  93. case 0:
  94. break;
  95. case SRR1_MC_IFETCH_SLBPAR:
  96. case SRR1_MC_IFETCH_SLBMULTI:
  97. case SRR1_MC_IFETCH_SLBPARMULTI:
  98. reload_slb(vcpu);
  99. break;
  100. case SRR1_MC_IFETCH_TLBMULTI:
  101. flush_tlb_power7(vcpu);
  102. break;
  103. default:
  104. handled = 0;
  105. }
  106. #ifdef CONFIG_PPC_POWERNV
  107. /*
  108. * See if OPAL has already handled the condition.
  109. * We assume that if the condition is recovered then OPAL
  110. * will have generated an error log event that we will pick
  111. * up and log later.
  112. */
  113. opal_evt = local_paca->opal_mc_evt;
  114. if (opal_evt->version == OpalMCE_V1 &&
  115. (opal_evt->severity == OpalMCE_SEV_NO_ERROR ||
  116. opal_evt->disposition == OpalMCE_DISPOSITION_RECOVERED))
  117. handled = 1;
  118. if (handled)
  119. opal_evt->in_use = 0;
  120. #endif
  121. return handled;
  122. }
  123. long kvmppc_realmode_machine_check(struct kvm_vcpu *vcpu)
  124. {
  125. if (cpu_has_feature(CPU_FTR_ARCH_206))
  126. return kvmppc_realmode_mc_power7(vcpu);
  127. return 0;
  128. }