cputable.c 66 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/export.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. #include <asm/mmu.h>
  21. #include <asm/setup.h>
  22. struct cpu_spec* cur_cpu_spec = NULL;
  23. EXPORT_SYMBOL(cur_cpu_spec);
  24. /* The platform string corresponding to the real PVR */
  25. const char *powerpc_base_platform;
  26. /* NOTE:
  27. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  28. * the responsibility of the appropriate CPU save/restore functions to
  29. * eventually copy these settings over. Those save/restore aren't yet
  30. * part of the cputable though. That has to be fixed for both ppc32
  31. * and ppc64
  32. */
  33. #ifdef CONFIG_PPC32
  34. extern void __setup_cpu_e200(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_e500v1(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_e500v2(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_e500mc(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_440ep(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_440epx(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_440gx(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_440grx(unsigned long offset, struct cpu_spec* spec);
  42. extern void __setup_cpu_440spe(unsigned long offset, struct cpu_spec* spec);
  43. extern void __setup_cpu_440x5(unsigned long offset, struct cpu_spec* spec);
  44. extern void __setup_cpu_460ex(unsigned long offset, struct cpu_spec* spec);
  45. extern void __setup_cpu_460gt(unsigned long offset, struct cpu_spec* spec);
  46. extern void __setup_cpu_460sx(unsigned long offset, struct cpu_spec *spec);
  47. extern void __setup_cpu_apm821xx(unsigned long offset, struct cpu_spec *spec);
  48. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  49. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  50. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  51. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  52. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  53. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  54. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  55. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  56. #endif /* CONFIG_PPC32 */
  57. #ifdef CONFIG_PPC64
  58. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  59. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  60. extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
  61. extern void __setup_cpu_a2(unsigned long offset, struct cpu_spec* spec);
  62. extern void __restore_cpu_pa6t(void);
  63. extern void __restore_cpu_ppc970(void);
  64. extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
  65. extern void __restore_cpu_power7(void);
  66. extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
  67. extern void __restore_cpu_power8(void);
  68. extern void __restore_cpu_a2(void);
  69. #endif /* CONFIG_PPC64 */
  70. #if defined(CONFIG_E500)
  71. extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
  72. extern void __restore_cpu_e5500(void);
  73. #endif /* CONFIG_E500 */
  74. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  75. * ones as well...
  76. */
  77. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  78. PPC_FEATURE_HAS_MMU)
  79. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  80. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  81. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  82. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  83. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  84. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  85. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  86. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  87. PPC_FEATURE_TRUE_LE | \
  88. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  89. #define COMMON_USER_POWER7 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  90. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  91. PPC_FEATURE_TRUE_LE | \
  92. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  93. #define COMMON_USER_POWER8 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_06 |\
  94. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  95. PPC_FEATURE_TRUE_LE | \
  96. PPC_FEATURE_PSERIES_PERFMON_COMPAT)
  97. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  98. PPC_FEATURE_TRUE_LE | \
  99. PPC_FEATURE_HAS_ALTIVEC_COMP)
  100. #ifdef CONFIG_PPC_BOOK3E_64
  101. #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
  102. #else
  103. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  104. PPC_FEATURE_BOOKE)
  105. #endif
  106. static struct cpu_spec __initdata cpu_specs[] = {
  107. #ifdef CONFIG_PPC_BOOK3S_64
  108. { /* Power3 */
  109. .pvr_mask = 0xffff0000,
  110. .pvr_value = 0x00400000,
  111. .cpu_name = "POWER3 (630)",
  112. .cpu_features = CPU_FTRS_POWER3,
  113. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  114. .mmu_features = MMU_FTR_HPTE_TABLE,
  115. .icache_bsize = 128,
  116. .dcache_bsize = 128,
  117. .num_pmcs = 8,
  118. .pmc_type = PPC_PMC_IBM,
  119. .oprofile_cpu_type = "ppc64/power3",
  120. .oprofile_type = PPC_OPROFILE_RS64,
  121. .platform = "power3",
  122. },
  123. { /* Power3+ */
  124. .pvr_mask = 0xffff0000,
  125. .pvr_value = 0x00410000,
  126. .cpu_name = "POWER3 (630+)",
  127. .cpu_features = CPU_FTRS_POWER3,
  128. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  129. .mmu_features = MMU_FTR_HPTE_TABLE,
  130. .icache_bsize = 128,
  131. .dcache_bsize = 128,
  132. .num_pmcs = 8,
  133. .pmc_type = PPC_PMC_IBM,
  134. .oprofile_cpu_type = "ppc64/power3",
  135. .oprofile_type = PPC_OPROFILE_RS64,
  136. .platform = "power3",
  137. },
  138. { /* Northstar */
  139. .pvr_mask = 0xffff0000,
  140. .pvr_value = 0x00330000,
  141. .cpu_name = "RS64-II (northstar)",
  142. .cpu_features = CPU_FTRS_RS64,
  143. .cpu_user_features = COMMON_USER_PPC64,
  144. .mmu_features = MMU_FTR_HPTE_TABLE,
  145. .icache_bsize = 128,
  146. .dcache_bsize = 128,
  147. .num_pmcs = 8,
  148. .pmc_type = PPC_PMC_IBM,
  149. .oprofile_cpu_type = "ppc64/rs64",
  150. .oprofile_type = PPC_OPROFILE_RS64,
  151. .platform = "rs64",
  152. },
  153. { /* Pulsar */
  154. .pvr_mask = 0xffff0000,
  155. .pvr_value = 0x00340000,
  156. .cpu_name = "RS64-III (pulsar)",
  157. .cpu_features = CPU_FTRS_RS64,
  158. .cpu_user_features = COMMON_USER_PPC64,
  159. .mmu_features = MMU_FTR_HPTE_TABLE,
  160. .icache_bsize = 128,
  161. .dcache_bsize = 128,
  162. .num_pmcs = 8,
  163. .pmc_type = PPC_PMC_IBM,
  164. .oprofile_cpu_type = "ppc64/rs64",
  165. .oprofile_type = PPC_OPROFILE_RS64,
  166. .platform = "rs64",
  167. },
  168. { /* I-star */
  169. .pvr_mask = 0xffff0000,
  170. .pvr_value = 0x00360000,
  171. .cpu_name = "RS64-III (icestar)",
  172. .cpu_features = CPU_FTRS_RS64,
  173. .cpu_user_features = COMMON_USER_PPC64,
  174. .mmu_features = MMU_FTR_HPTE_TABLE,
  175. .icache_bsize = 128,
  176. .dcache_bsize = 128,
  177. .num_pmcs = 8,
  178. .pmc_type = PPC_PMC_IBM,
  179. .oprofile_cpu_type = "ppc64/rs64",
  180. .oprofile_type = PPC_OPROFILE_RS64,
  181. .platform = "rs64",
  182. },
  183. { /* S-star */
  184. .pvr_mask = 0xffff0000,
  185. .pvr_value = 0x00370000,
  186. .cpu_name = "RS64-IV (sstar)",
  187. .cpu_features = CPU_FTRS_RS64,
  188. .cpu_user_features = COMMON_USER_PPC64,
  189. .mmu_features = MMU_FTR_HPTE_TABLE,
  190. .icache_bsize = 128,
  191. .dcache_bsize = 128,
  192. .num_pmcs = 8,
  193. .pmc_type = PPC_PMC_IBM,
  194. .oprofile_cpu_type = "ppc64/rs64",
  195. .oprofile_type = PPC_OPROFILE_RS64,
  196. .platform = "rs64",
  197. },
  198. { /* Power4 */
  199. .pvr_mask = 0xffff0000,
  200. .pvr_value = 0x00350000,
  201. .cpu_name = "POWER4 (gp)",
  202. .cpu_features = CPU_FTRS_POWER4,
  203. .cpu_user_features = COMMON_USER_POWER4,
  204. .mmu_features = MMU_FTRS_POWER4,
  205. .icache_bsize = 128,
  206. .dcache_bsize = 128,
  207. .num_pmcs = 8,
  208. .pmc_type = PPC_PMC_IBM,
  209. .oprofile_cpu_type = "ppc64/power4",
  210. .oprofile_type = PPC_OPROFILE_POWER4,
  211. .platform = "power4",
  212. },
  213. { /* Power4+ */
  214. .pvr_mask = 0xffff0000,
  215. .pvr_value = 0x00380000,
  216. .cpu_name = "POWER4+ (gq)",
  217. .cpu_features = CPU_FTRS_POWER4,
  218. .cpu_user_features = COMMON_USER_POWER4,
  219. .mmu_features = MMU_FTRS_POWER4,
  220. .icache_bsize = 128,
  221. .dcache_bsize = 128,
  222. .num_pmcs = 8,
  223. .pmc_type = PPC_PMC_IBM,
  224. .oprofile_cpu_type = "ppc64/power4",
  225. .oprofile_type = PPC_OPROFILE_POWER4,
  226. .platform = "power4",
  227. },
  228. { /* PPC970 */
  229. .pvr_mask = 0xffff0000,
  230. .pvr_value = 0x00390000,
  231. .cpu_name = "PPC970",
  232. .cpu_features = CPU_FTRS_PPC970,
  233. .cpu_user_features = COMMON_USER_POWER4 |
  234. PPC_FEATURE_HAS_ALTIVEC_COMP,
  235. .mmu_features = MMU_FTRS_PPC970,
  236. .icache_bsize = 128,
  237. .dcache_bsize = 128,
  238. .num_pmcs = 8,
  239. .pmc_type = PPC_PMC_IBM,
  240. .cpu_setup = __setup_cpu_ppc970,
  241. .cpu_restore = __restore_cpu_ppc970,
  242. .oprofile_cpu_type = "ppc64/970",
  243. .oprofile_type = PPC_OPROFILE_POWER4,
  244. .platform = "ppc970",
  245. },
  246. { /* PPC970FX */
  247. .pvr_mask = 0xffff0000,
  248. .pvr_value = 0x003c0000,
  249. .cpu_name = "PPC970FX",
  250. .cpu_features = CPU_FTRS_PPC970,
  251. .cpu_user_features = COMMON_USER_POWER4 |
  252. PPC_FEATURE_HAS_ALTIVEC_COMP,
  253. .mmu_features = MMU_FTRS_PPC970,
  254. .icache_bsize = 128,
  255. .dcache_bsize = 128,
  256. .num_pmcs = 8,
  257. .pmc_type = PPC_PMC_IBM,
  258. .cpu_setup = __setup_cpu_ppc970,
  259. .cpu_restore = __restore_cpu_ppc970,
  260. .oprofile_cpu_type = "ppc64/970",
  261. .oprofile_type = PPC_OPROFILE_POWER4,
  262. .platform = "ppc970",
  263. },
  264. { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
  265. .pvr_mask = 0xffffffff,
  266. .pvr_value = 0x00440100,
  267. .cpu_name = "PPC970MP",
  268. .cpu_features = CPU_FTRS_PPC970,
  269. .cpu_user_features = COMMON_USER_POWER4 |
  270. PPC_FEATURE_HAS_ALTIVEC_COMP,
  271. .mmu_features = MMU_FTRS_PPC970,
  272. .icache_bsize = 128,
  273. .dcache_bsize = 128,
  274. .num_pmcs = 8,
  275. .pmc_type = PPC_PMC_IBM,
  276. .cpu_setup = __setup_cpu_ppc970,
  277. .cpu_restore = __restore_cpu_ppc970,
  278. .oprofile_cpu_type = "ppc64/970MP",
  279. .oprofile_type = PPC_OPROFILE_POWER4,
  280. .platform = "ppc970",
  281. },
  282. { /* PPC970MP */
  283. .pvr_mask = 0xffff0000,
  284. .pvr_value = 0x00440000,
  285. .cpu_name = "PPC970MP",
  286. .cpu_features = CPU_FTRS_PPC970,
  287. .cpu_user_features = COMMON_USER_POWER4 |
  288. PPC_FEATURE_HAS_ALTIVEC_COMP,
  289. .mmu_features = MMU_FTRS_PPC970,
  290. .icache_bsize = 128,
  291. .dcache_bsize = 128,
  292. .num_pmcs = 8,
  293. .pmc_type = PPC_PMC_IBM,
  294. .cpu_setup = __setup_cpu_ppc970MP,
  295. .cpu_restore = __restore_cpu_ppc970,
  296. .oprofile_cpu_type = "ppc64/970MP",
  297. .oprofile_type = PPC_OPROFILE_POWER4,
  298. .platform = "ppc970",
  299. },
  300. { /* PPC970GX */
  301. .pvr_mask = 0xffff0000,
  302. .pvr_value = 0x00450000,
  303. .cpu_name = "PPC970GX",
  304. .cpu_features = CPU_FTRS_PPC970,
  305. .cpu_user_features = COMMON_USER_POWER4 |
  306. PPC_FEATURE_HAS_ALTIVEC_COMP,
  307. .mmu_features = MMU_FTRS_PPC970,
  308. .icache_bsize = 128,
  309. .dcache_bsize = 128,
  310. .num_pmcs = 8,
  311. .pmc_type = PPC_PMC_IBM,
  312. .cpu_setup = __setup_cpu_ppc970,
  313. .oprofile_cpu_type = "ppc64/970",
  314. .oprofile_type = PPC_OPROFILE_POWER4,
  315. .platform = "ppc970",
  316. },
  317. { /* Power5 GR */
  318. .pvr_mask = 0xffff0000,
  319. .pvr_value = 0x003a0000,
  320. .cpu_name = "POWER5 (gr)",
  321. .cpu_features = CPU_FTRS_POWER5,
  322. .cpu_user_features = COMMON_USER_POWER5,
  323. .mmu_features = MMU_FTRS_POWER5,
  324. .icache_bsize = 128,
  325. .dcache_bsize = 128,
  326. .num_pmcs = 6,
  327. .pmc_type = PPC_PMC_IBM,
  328. .oprofile_cpu_type = "ppc64/power5",
  329. .oprofile_type = PPC_OPROFILE_POWER4,
  330. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  331. * and above but only works on POWER5 and above
  332. */
  333. .oprofile_mmcra_sihv = MMCRA_SIHV,
  334. .oprofile_mmcra_sipr = MMCRA_SIPR,
  335. .platform = "power5",
  336. },
  337. { /* Power5++ */
  338. .pvr_mask = 0xffffff00,
  339. .pvr_value = 0x003b0300,
  340. .cpu_name = "POWER5+ (gs)",
  341. .cpu_features = CPU_FTRS_POWER5,
  342. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  343. .mmu_features = MMU_FTRS_POWER5,
  344. .icache_bsize = 128,
  345. .dcache_bsize = 128,
  346. .num_pmcs = 6,
  347. .oprofile_cpu_type = "ppc64/power5++",
  348. .oprofile_type = PPC_OPROFILE_POWER4,
  349. .oprofile_mmcra_sihv = MMCRA_SIHV,
  350. .oprofile_mmcra_sipr = MMCRA_SIPR,
  351. .platform = "power5+",
  352. },
  353. { /* Power5 GS */
  354. .pvr_mask = 0xffff0000,
  355. .pvr_value = 0x003b0000,
  356. .cpu_name = "POWER5+ (gs)",
  357. .cpu_features = CPU_FTRS_POWER5,
  358. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  359. .mmu_features = MMU_FTRS_POWER5,
  360. .icache_bsize = 128,
  361. .dcache_bsize = 128,
  362. .num_pmcs = 6,
  363. .pmc_type = PPC_PMC_IBM,
  364. .oprofile_cpu_type = "ppc64/power5+",
  365. .oprofile_type = PPC_OPROFILE_POWER4,
  366. .oprofile_mmcra_sihv = MMCRA_SIHV,
  367. .oprofile_mmcra_sipr = MMCRA_SIPR,
  368. .platform = "power5+",
  369. },
  370. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  371. .pvr_mask = 0xffffffff,
  372. .pvr_value = 0x0f000001,
  373. .cpu_name = "POWER5+",
  374. .cpu_features = CPU_FTRS_POWER5,
  375. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  376. .mmu_features = MMU_FTRS_POWER5,
  377. .icache_bsize = 128,
  378. .dcache_bsize = 128,
  379. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  380. .oprofile_type = PPC_OPROFILE_POWER4,
  381. .platform = "power5+",
  382. },
  383. { /* Power6 */
  384. .pvr_mask = 0xffff0000,
  385. .pvr_value = 0x003e0000,
  386. .cpu_name = "POWER6 (raw)",
  387. .cpu_features = CPU_FTRS_POWER6,
  388. .cpu_user_features = COMMON_USER_POWER6 |
  389. PPC_FEATURE_POWER6_EXT,
  390. .mmu_features = MMU_FTRS_POWER6,
  391. .icache_bsize = 128,
  392. .dcache_bsize = 128,
  393. .num_pmcs = 6,
  394. .pmc_type = PPC_PMC_IBM,
  395. .oprofile_cpu_type = "ppc64/power6",
  396. .oprofile_type = PPC_OPROFILE_POWER4,
  397. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  398. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  399. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  400. POWER6_MMCRA_OTHER,
  401. .platform = "power6x",
  402. },
  403. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  404. .pvr_mask = 0xffffffff,
  405. .pvr_value = 0x0f000002,
  406. .cpu_name = "POWER6 (architected)",
  407. .cpu_features = CPU_FTRS_POWER6,
  408. .cpu_user_features = COMMON_USER_POWER6,
  409. .mmu_features = MMU_FTRS_POWER6,
  410. .icache_bsize = 128,
  411. .dcache_bsize = 128,
  412. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  413. .oprofile_type = PPC_OPROFILE_POWER4,
  414. .platform = "power6",
  415. },
  416. { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
  417. .pvr_mask = 0xffffffff,
  418. .pvr_value = 0x0f000003,
  419. .cpu_name = "POWER7 (architected)",
  420. .cpu_features = CPU_FTRS_POWER7,
  421. .cpu_user_features = COMMON_USER_POWER7,
  422. .mmu_features = MMU_FTRS_POWER7,
  423. .icache_bsize = 128,
  424. .dcache_bsize = 128,
  425. .oprofile_type = PPC_OPROFILE_POWER4,
  426. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  427. .cpu_setup = __setup_cpu_power7,
  428. .cpu_restore = __restore_cpu_power7,
  429. .platform = "power7",
  430. },
  431. { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
  432. .pvr_mask = 0xffffffff,
  433. .pvr_value = 0x0f000004,
  434. .cpu_name = "POWER8 (architected)",
  435. .cpu_features = CPU_FTRS_POWER8,
  436. .cpu_user_features = COMMON_USER_POWER8,
  437. .mmu_features = MMU_FTRS_POWER8,
  438. .icache_bsize = 128,
  439. .dcache_bsize = 128,
  440. .oprofile_type = PPC_OPROFILE_POWER4,
  441. .oprofile_cpu_type = "ppc64/ibm-compat-v1",
  442. .cpu_setup = __setup_cpu_power8,
  443. .cpu_restore = __restore_cpu_power8,
  444. .platform = "power8",
  445. },
  446. { /* Power7 */
  447. .pvr_mask = 0xffff0000,
  448. .pvr_value = 0x003f0000,
  449. .cpu_name = "POWER7 (raw)",
  450. .cpu_features = CPU_FTRS_POWER7,
  451. .cpu_user_features = COMMON_USER_POWER7,
  452. .mmu_features = MMU_FTRS_POWER7,
  453. .icache_bsize = 128,
  454. .dcache_bsize = 128,
  455. .num_pmcs = 6,
  456. .pmc_type = PPC_PMC_IBM,
  457. .oprofile_cpu_type = "ppc64/power7",
  458. .oprofile_type = PPC_OPROFILE_POWER4,
  459. .cpu_setup = __setup_cpu_power7,
  460. .cpu_restore = __restore_cpu_power7,
  461. .platform = "power7",
  462. },
  463. { /* Power7+ */
  464. .pvr_mask = 0xffff0000,
  465. .pvr_value = 0x004A0000,
  466. .cpu_name = "POWER7+ (raw)",
  467. .cpu_features = CPU_FTRS_POWER7,
  468. .cpu_user_features = COMMON_USER_POWER7,
  469. .mmu_features = MMU_FTRS_POWER7,
  470. .icache_bsize = 128,
  471. .dcache_bsize = 128,
  472. .num_pmcs = 6,
  473. .pmc_type = PPC_PMC_IBM,
  474. .oprofile_cpu_type = "ppc64/power7",
  475. .oprofile_type = PPC_OPROFILE_POWER4,
  476. .cpu_setup = __setup_cpu_power7,
  477. .cpu_restore = __restore_cpu_power7,
  478. .platform = "power7+",
  479. },
  480. { /* Power8 */
  481. .pvr_mask = 0xffff0000,
  482. .pvr_value = 0x004b0000,
  483. .cpu_name = "POWER8 (raw)",
  484. .cpu_features = CPU_FTRS_POWER8,
  485. .cpu_user_features = COMMON_USER_POWER8,
  486. .mmu_features = MMU_FTRS_POWER8,
  487. .icache_bsize = 128,
  488. .dcache_bsize = 128,
  489. .num_pmcs = 6,
  490. .pmc_type = PPC_PMC_IBM,
  491. .oprofile_cpu_type = "ppc64/power8",
  492. .oprofile_type = PPC_OPROFILE_POWER4,
  493. .cpu_setup = __setup_cpu_power8,
  494. .cpu_restore = __restore_cpu_power8,
  495. .platform = "power8",
  496. },
  497. { /* Cell Broadband Engine */
  498. .pvr_mask = 0xffff0000,
  499. .pvr_value = 0x00700000,
  500. .cpu_name = "Cell Broadband Engine",
  501. .cpu_features = CPU_FTRS_CELL,
  502. .cpu_user_features = COMMON_USER_PPC64 |
  503. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  504. PPC_FEATURE_SMT,
  505. .mmu_features = MMU_FTRS_CELL,
  506. .icache_bsize = 128,
  507. .dcache_bsize = 128,
  508. .num_pmcs = 4,
  509. .pmc_type = PPC_PMC_IBM,
  510. .oprofile_cpu_type = "ppc64/cell-be",
  511. .oprofile_type = PPC_OPROFILE_CELL,
  512. .platform = "ppc-cell-be",
  513. },
  514. { /* PA Semi PA6T */
  515. .pvr_mask = 0x7fff0000,
  516. .pvr_value = 0x00900000,
  517. .cpu_name = "PA6T",
  518. .cpu_features = CPU_FTRS_PA6T,
  519. .cpu_user_features = COMMON_USER_PA6T,
  520. .mmu_features = MMU_FTRS_PA6T,
  521. .icache_bsize = 64,
  522. .dcache_bsize = 64,
  523. .num_pmcs = 6,
  524. .pmc_type = PPC_PMC_PA6T,
  525. .cpu_setup = __setup_cpu_pa6t,
  526. .cpu_restore = __restore_cpu_pa6t,
  527. .oprofile_cpu_type = "ppc64/pa6t",
  528. .oprofile_type = PPC_OPROFILE_PA6T,
  529. .platform = "pa6t",
  530. },
  531. { /* default match */
  532. .pvr_mask = 0x00000000,
  533. .pvr_value = 0x00000000,
  534. .cpu_name = "POWER4 (compatible)",
  535. .cpu_features = CPU_FTRS_COMPATIBLE,
  536. .cpu_user_features = COMMON_USER_PPC64,
  537. .mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
  538. .icache_bsize = 128,
  539. .dcache_bsize = 128,
  540. .num_pmcs = 6,
  541. .pmc_type = PPC_PMC_IBM,
  542. .platform = "power4",
  543. }
  544. #endif /* CONFIG_PPC_BOOK3S_64 */
  545. #ifdef CONFIG_PPC32
  546. #if CLASSIC_PPC
  547. { /* 601 */
  548. .pvr_mask = 0xffff0000,
  549. .pvr_value = 0x00010000,
  550. .cpu_name = "601",
  551. .cpu_features = CPU_FTRS_PPC601,
  552. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  553. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  554. .mmu_features = MMU_FTR_HPTE_TABLE,
  555. .icache_bsize = 32,
  556. .dcache_bsize = 32,
  557. .machine_check = machine_check_generic,
  558. .platform = "ppc601",
  559. },
  560. { /* 603 */
  561. .pvr_mask = 0xffff0000,
  562. .pvr_value = 0x00030000,
  563. .cpu_name = "603",
  564. .cpu_features = CPU_FTRS_603,
  565. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  566. .mmu_features = 0,
  567. .icache_bsize = 32,
  568. .dcache_bsize = 32,
  569. .cpu_setup = __setup_cpu_603,
  570. .machine_check = machine_check_generic,
  571. .platform = "ppc603",
  572. },
  573. { /* 603e */
  574. .pvr_mask = 0xffff0000,
  575. .pvr_value = 0x00060000,
  576. .cpu_name = "603e",
  577. .cpu_features = CPU_FTRS_603,
  578. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  579. .mmu_features = 0,
  580. .icache_bsize = 32,
  581. .dcache_bsize = 32,
  582. .cpu_setup = __setup_cpu_603,
  583. .machine_check = machine_check_generic,
  584. .platform = "ppc603",
  585. },
  586. { /* 603ev */
  587. .pvr_mask = 0xffff0000,
  588. .pvr_value = 0x00070000,
  589. .cpu_name = "603ev",
  590. .cpu_features = CPU_FTRS_603,
  591. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  592. .mmu_features = 0,
  593. .icache_bsize = 32,
  594. .dcache_bsize = 32,
  595. .cpu_setup = __setup_cpu_603,
  596. .machine_check = machine_check_generic,
  597. .platform = "ppc603",
  598. },
  599. { /* 604 */
  600. .pvr_mask = 0xffff0000,
  601. .pvr_value = 0x00040000,
  602. .cpu_name = "604",
  603. .cpu_features = CPU_FTRS_604,
  604. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  605. .mmu_features = MMU_FTR_HPTE_TABLE,
  606. .icache_bsize = 32,
  607. .dcache_bsize = 32,
  608. .num_pmcs = 2,
  609. .cpu_setup = __setup_cpu_604,
  610. .machine_check = machine_check_generic,
  611. .platform = "ppc604",
  612. },
  613. { /* 604e */
  614. .pvr_mask = 0xfffff000,
  615. .pvr_value = 0x00090000,
  616. .cpu_name = "604e",
  617. .cpu_features = CPU_FTRS_604,
  618. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  619. .mmu_features = MMU_FTR_HPTE_TABLE,
  620. .icache_bsize = 32,
  621. .dcache_bsize = 32,
  622. .num_pmcs = 4,
  623. .cpu_setup = __setup_cpu_604,
  624. .machine_check = machine_check_generic,
  625. .platform = "ppc604",
  626. },
  627. { /* 604r */
  628. .pvr_mask = 0xffff0000,
  629. .pvr_value = 0x00090000,
  630. .cpu_name = "604r",
  631. .cpu_features = CPU_FTRS_604,
  632. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  633. .mmu_features = MMU_FTR_HPTE_TABLE,
  634. .icache_bsize = 32,
  635. .dcache_bsize = 32,
  636. .num_pmcs = 4,
  637. .cpu_setup = __setup_cpu_604,
  638. .machine_check = machine_check_generic,
  639. .platform = "ppc604",
  640. },
  641. { /* 604ev */
  642. .pvr_mask = 0xffff0000,
  643. .pvr_value = 0x000a0000,
  644. .cpu_name = "604ev",
  645. .cpu_features = CPU_FTRS_604,
  646. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  647. .mmu_features = MMU_FTR_HPTE_TABLE,
  648. .icache_bsize = 32,
  649. .dcache_bsize = 32,
  650. .num_pmcs = 4,
  651. .cpu_setup = __setup_cpu_604,
  652. .machine_check = machine_check_generic,
  653. .platform = "ppc604",
  654. },
  655. { /* 740/750 (0x4202, don't support TAU ?) */
  656. .pvr_mask = 0xffffffff,
  657. .pvr_value = 0x00084202,
  658. .cpu_name = "740/750",
  659. .cpu_features = CPU_FTRS_740_NOTAU,
  660. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  661. .mmu_features = MMU_FTR_HPTE_TABLE,
  662. .icache_bsize = 32,
  663. .dcache_bsize = 32,
  664. .num_pmcs = 4,
  665. .cpu_setup = __setup_cpu_750,
  666. .machine_check = machine_check_generic,
  667. .platform = "ppc750",
  668. },
  669. { /* 750CX (80100 and 8010x?) */
  670. .pvr_mask = 0xfffffff0,
  671. .pvr_value = 0x00080100,
  672. .cpu_name = "750CX",
  673. .cpu_features = CPU_FTRS_750,
  674. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  675. .mmu_features = MMU_FTR_HPTE_TABLE,
  676. .icache_bsize = 32,
  677. .dcache_bsize = 32,
  678. .num_pmcs = 4,
  679. .cpu_setup = __setup_cpu_750cx,
  680. .machine_check = machine_check_generic,
  681. .platform = "ppc750",
  682. },
  683. { /* 750CX (82201 and 82202) */
  684. .pvr_mask = 0xfffffff0,
  685. .pvr_value = 0x00082200,
  686. .cpu_name = "750CX",
  687. .cpu_features = CPU_FTRS_750,
  688. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  689. .mmu_features = MMU_FTR_HPTE_TABLE,
  690. .icache_bsize = 32,
  691. .dcache_bsize = 32,
  692. .num_pmcs = 4,
  693. .pmc_type = PPC_PMC_IBM,
  694. .cpu_setup = __setup_cpu_750cx,
  695. .machine_check = machine_check_generic,
  696. .platform = "ppc750",
  697. },
  698. { /* 750CXe (82214) */
  699. .pvr_mask = 0xfffffff0,
  700. .pvr_value = 0x00082210,
  701. .cpu_name = "750CXe",
  702. .cpu_features = CPU_FTRS_750,
  703. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  704. .mmu_features = MMU_FTR_HPTE_TABLE,
  705. .icache_bsize = 32,
  706. .dcache_bsize = 32,
  707. .num_pmcs = 4,
  708. .pmc_type = PPC_PMC_IBM,
  709. .cpu_setup = __setup_cpu_750cx,
  710. .machine_check = machine_check_generic,
  711. .platform = "ppc750",
  712. },
  713. { /* 750CXe "Gekko" (83214) */
  714. .pvr_mask = 0xffffffff,
  715. .pvr_value = 0x00083214,
  716. .cpu_name = "750CXe",
  717. .cpu_features = CPU_FTRS_750,
  718. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  719. .mmu_features = MMU_FTR_HPTE_TABLE,
  720. .icache_bsize = 32,
  721. .dcache_bsize = 32,
  722. .num_pmcs = 4,
  723. .pmc_type = PPC_PMC_IBM,
  724. .cpu_setup = __setup_cpu_750cx,
  725. .machine_check = machine_check_generic,
  726. .platform = "ppc750",
  727. },
  728. { /* 750CL (and "Broadway") */
  729. .pvr_mask = 0xfffff0e0,
  730. .pvr_value = 0x00087000,
  731. .cpu_name = "750CL",
  732. .cpu_features = CPU_FTRS_750CL,
  733. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  734. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  735. .icache_bsize = 32,
  736. .dcache_bsize = 32,
  737. .num_pmcs = 4,
  738. .pmc_type = PPC_PMC_IBM,
  739. .cpu_setup = __setup_cpu_750,
  740. .machine_check = machine_check_generic,
  741. .platform = "ppc750",
  742. .oprofile_cpu_type = "ppc/750",
  743. .oprofile_type = PPC_OPROFILE_G4,
  744. },
  745. { /* 745/755 */
  746. .pvr_mask = 0xfffff000,
  747. .pvr_value = 0x00083000,
  748. .cpu_name = "745/755",
  749. .cpu_features = CPU_FTRS_750,
  750. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  751. .mmu_features = MMU_FTR_HPTE_TABLE,
  752. .icache_bsize = 32,
  753. .dcache_bsize = 32,
  754. .num_pmcs = 4,
  755. .pmc_type = PPC_PMC_IBM,
  756. .cpu_setup = __setup_cpu_750,
  757. .machine_check = machine_check_generic,
  758. .platform = "ppc750",
  759. },
  760. { /* 750FX rev 1.x */
  761. .pvr_mask = 0xffffff00,
  762. .pvr_value = 0x70000100,
  763. .cpu_name = "750FX",
  764. .cpu_features = CPU_FTRS_750FX1,
  765. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  766. .mmu_features = MMU_FTR_HPTE_TABLE,
  767. .icache_bsize = 32,
  768. .dcache_bsize = 32,
  769. .num_pmcs = 4,
  770. .pmc_type = PPC_PMC_IBM,
  771. .cpu_setup = __setup_cpu_750,
  772. .machine_check = machine_check_generic,
  773. .platform = "ppc750",
  774. .oprofile_cpu_type = "ppc/750",
  775. .oprofile_type = PPC_OPROFILE_G4,
  776. },
  777. { /* 750FX rev 2.0 must disable HID0[DPM] */
  778. .pvr_mask = 0xffffffff,
  779. .pvr_value = 0x70000200,
  780. .cpu_name = "750FX",
  781. .cpu_features = CPU_FTRS_750FX2,
  782. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  783. .mmu_features = MMU_FTR_HPTE_TABLE,
  784. .icache_bsize = 32,
  785. .dcache_bsize = 32,
  786. .num_pmcs = 4,
  787. .pmc_type = PPC_PMC_IBM,
  788. .cpu_setup = __setup_cpu_750,
  789. .machine_check = machine_check_generic,
  790. .platform = "ppc750",
  791. .oprofile_cpu_type = "ppc/750",
  792. .oprofile_type = PPC_OPROFILE_G4,
  793. },
  794. { /* 750FX (All revs except 2.0) */
  795. .pvr_mask = 0xffff0000,
  796. .pvr_value = 0x70000000,
  797. .cpu_name = "750FX",
  798. .cpu_features = CPU_FTRS_750FX,
  799. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  800. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  801. .icache_bsize = 32,
  802. .dcache_bsize = 32,
  803. .num_pmcs = 4,
  804. .pmc_type = PPC_PMC_IBM,
  805. .cpu_setup = __setup_cpu_750fx,
  806. .machine_check = machine_check_generic,
  807. .platform = "ppc750",
  808. .oprofile_cpu_type = "ppc/750",
  809. .oprofile_type = PPC_OPROFILE_G4,
  810. },
  811. { /* 750GX */
  812. .pvr_mask = 0xffff0000,
  813. .pvr_value = 0x70020000,
  814. .cpu_name = "750GX",
  815. .cpu_features = CPU_FTRS_750GX,
  816. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  817. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  818. .icache_bsize = 32,
  819. .dcache_bsize = 32,
  820. .num_pmcs = 4,
  821. .pmc_type = PPC_PMC_IBM,
  822. .cpu_setup = __setup_cpu_750fx,
  823. .machine_check = machine_check_generic,
  824. .platform = "ppc750",
  825. .oprofile_cpu_type = "ppc/750",
  826. .oprofile_type = PPC_OPROFILE_G4,
  827. },
  828. { /* 740/750 (L2CR bit need fixup for 740) */
  829. .pvr_mask = 0xffff0000,
  830. .pvr_value = 0x00080000,
  831. .cpu_name = "740/750",
  832. .cpu_features = CPU_FTRS_740,
  833. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  834. .mmu_features = MMU_FTR_HPTE_TABLE,
  835. .icache_bsize = 32,
  836. .dcache_bsize = 32,
  837. .num_pmcs = 4,
  838. .pmc_type = PPC_PMC_IBM,
  839. .cpu_setup = __setup_cpu_750,
  840. .machine_check = machine_check_generic,
  841. .platform = "ppc750",
  842. },
  843. { /* 7400 rev 1.1 ? (no TAU) */
  844. .pvr_mask = 0xffffffff,
  845. .pvr_value = 0x000c1101,
  846. .cpu_name = "7400 (1.1)",
  847. .cpu_features = CPU_FTRS_7400_NOTAU,
  848. .cpu_user_features = COMMON_USER |
  849. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  850. .mmu_features = MMU_FTR_HPTE_TABLE,
  851. .icache_bsize = 32,
  852. .dcache_bsize = 32,
  853. .num_pmcs = 4,
  854. .pmc_type = PPC_PMC_G4,
  855. .cpu_setup = __setup_cpu_7400,
  856. .machine_check = machine_check_generic,
  857. .platform = "ppc7400",
  858. },
  859. { /* 7400 */
  860. .pvr_mask = 0xffff0000,
  861. .pvr_value = 0x000c0000,
  862. .cpu_name = "7400",
  863. .cpu_features = CPU_FTRS_7400,
  864. .cpu_user_features = COMMON_USER |
  865. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  866. .mmu_features = MMU_FTR_HPTE_TABLE,
  867. .icache_bsize = 32,
  868. .dcache_bsize = 32,
  869. .num_pmcs = 4,
  870. .pmc_type = PPC_PMC_G4,
  871. .cpu_setup = __setup_cpu_7400,
  872. .machine_check = machine_check_generic,
  873. .platform = "ppc7400",
  874. },
  875. { /* 7410 */
  876. .pvr_mask = 0xffff0000,
  877. .pvr_value = 0x800c0000,
  878. .cpu_name = "7410",
  879. .cpu_features = CPU_FTRS_7400,
  880. .cpu_user_features = COMMON_USER |
  881. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  882. .mmu_features = MMU_FTR_HPTE_TABLE,
  883. .icache_bsize = 32,
  884. .dcache_bsize = 32,
  885. .num_pmcs = 4,
  886. .pmc_type = PPC_PMC_G4,
  887. .cpu_setup = __setup_cpu_7410,
  888. .machine_check = machine_check_generic,
  889. .platform = "ppc7400",
  890. },
  891. { /* 7450 2.0 - no doze/nap */
  892. .pvr_mask = 0xffffffff,
  893. .pvr_value = 0x80000200,
  894. .cpu_name = "7450",
  895. .cpu_features = CPU_FTRS_7450_20,
  896. .cpu_user_features = COMMON_USER |
  897. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  898. .mmu_features = MMU_FTR_HPTE_TABLE,
  899. .icache_bsize = 32,
  900. .dcache_bsize = 32,
  901. .num_pmcs = 6,
  902. .pmc_type = PPC_PMC_G4,
  903. .cpu_setup = __setup_cpu_745x,
  904. .oprofile_cpu_type = "ppc/7450",
  905. .oprofile_type = PPC_OPROFILE_G4,
  906. .machine_check = machine_check_generic,
  907. .platform = "ppc7450",
  908. },
  909. { /* 7450 2.1 */
  910. .pvr_mask = 0xffffffff,
  911. .pvr_value = 0x80000201,
  912. .cpu_name = "7450",
  913. .cpu_features = CPU_FTRS_7450_21,
  914. .cpu_user_features = COMMON_USER |
  915. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  916. .mmu_features = MMU_FTR_HPTE_TABLE,
  917. .icache_bsize = 32,
  918. .dcache_bsize = 32,
  919. .num_pmcs = 6,
  920. .pmc_type = PPC_PMC_G4,
  921. .cpu_setup = __setup_cpu_745x,
  922. .oprofile_cpu_type = "ppc/7450",
  923. .oprofile_type = PPC_OPROFILE_G4,
  924. .machine_check = machine_check_generic,
  925. .platform = "ppc7450",
  926. },
  927. { /* 7450 2.3 and newer */
  928. .pvr_mask = 0xffff0000,
  929. .pvr_value = 0x80000000,
  930. .cpu_name = "7450",
  931. .cpu_features = CPU_FTRS_7450_23,
  932. .cpu_user_features = COMMON_USER |
  933. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  934. .mmu_features = MMU_FTR_HPTE_TABLE,
  935. .icache_bsize = 32,
  936. .dcache_bsize = 32,
  937. .num_pmcs = 6,
  938. .pmc_type = PPC_PMC_G4,
  939. .cpu_setup = __setup_cpu_745x,
  940. .oprofile_cpu_type = "ppc/7450",
  941. .oprofile_type = PPC_OPROFILE_G4,
  942. .machine_check = machine_check_generic,
  943. .platform = "ppc7450",
  944. },
  945. { /* 7455 rev 1.x */
  946. .pvr_mask = 0xffffff00,
  947. .pvr_value = 0x80010100,
  948. .cpu_name = "7455",
  949. .cpu_features = CPU_FTRS_7455_1,
  950. .cpu_user_features = COMMON_USER |
  951. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  952. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  953. .icache_bsize = 32,
  954. .dcache_bsize = 32,
  955. .num_pmcs = 6,
  956. .pmc_type = PPC_PMC_G4,
  957. .cpu_setup = __setup_cpu_745x,
  958. .oprofile_cpu_type = "ppc/7450",
  959. .oprofile_type = PPC_OPROFILE_G4,
  960. .machine_check = machine_check_generic,
  961. .platform = "ppc7450",
  962. },
  963. { /* 7455 rev 2.0 */
  964. .pvr_mask = 0xffffffff,
  965. .pvr_value = 0x80010200,
  966. .cpu_name = "7455",
  967. .cpu_features = CPU_FTRS_7455_20,
  968. .cpu_user_features = COMMON_USER |
  969. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  970. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  971. .icache_bsize = 32,
  972. .dcache_bsize = 32,
  973. .num_pmcs = 6,
  974. .pmc_type = PPC_PMC_G4,
  975. .cpu_setup = __setup_cpu_745x,
  976. .oprofile_cpu_type = "ppc/7450",
  977. .oprofile_type = PPC_OPROFILE_G4,
  978. .machine_check = machine_check_generic,
  979. .platform = "ppc7450",
  980. },
  981. { /* 7455 others */
  982. .pvr_mask = 0xffff0000,
  983. .pvr_value = 0x80010000,
  984. .cpu_name = "7455",
  985. .cpu_features = CPU_FTRS_7455,
  986. .cpu_user_features = COMMON_USER |
  987. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  988. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  989. .icache_bsize = 32,
  990. .dcache_bsize = 32,
  991. .num_pmcs = 6,
  992. .pmc_type = PPC_PMC_G4,
  993. .cpu_setup = __setup_cpu_745x,
  994. .oprofile_cpu_type = "ppc/7450",
  995. .oprofile_type = PPC_OPROFILE_G4,
  996. .machine_check = machine_check_generic,
  997. .platform = "ppc7450",
  998. },
  999. { /* 7447/7457 Rev 1.0 */
  1000. .pvr_mask = 0xffffffff,
  1001. .pvr_value = 0x80020100,
  1002. .cpu_name = "7447/7457",
  1003. .cpu_features = CPU_FTRS_7447_10,
  1004. .cpu_user_features = COMMON_USER |
  1005. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1006. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1007. .icache_bsize = 32,
  1008. .dcache_bsize = 32,
  1009. .num_pmcs = 6,
  1010. .pmc_type = PPC_PMC_G4,
  1011. .cpu_setup = __setup_cpu_745x,
  1012. .oprofile_cpu_type = "ppc/7450",
  1013. .oprofile_type = PPC_OPROFILE_G4,
  1014. .machine_check = machine_check_generic,
  1015. .platform = "ppc7450",
  1016. },
  1017. { /* 7447/7457 Rev 1.1 */
  1018. .pvr_mask = 0xffffffff,
  1019. .pvr_value = 0x80020101,
  1020. .cpu_name = "7447/7457",
  1021. .cpu_features = CPU_FTRS_7447_10,
  1022. .cpu_user_features = COMMON_USER |
  1023. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1024. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1025. .icache_bsize = 32,
  1026. .dcache_bsize = 32,
  1027. .num_pmcs = 6,
  1028. .pmc_type = PPC_PMC_G4,
  1029. .cpu_setup = __setup_cpu_745x,
  1030. .oprofile_cpu_type = "ppc/7450",
  1031. .oprofile_type = PPC_OPROFILE_G4,
  1032. .machine_check = machine_check_generic,
  1033. .platform = "ppc7450",
  1034. },
  1035. { /* 7447/7457 Rev 1.2 and later */
  1036. .pvr_mask = 0xffff0000,
  1037. .pvr_value = 0x80020000,
  1038. .cpu_name = "7447/7457",
  1039. .cpu_features = CPU_FTRS_7447,
  1040. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1041. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1042. .icache_bsize = 32,
  1043. .dcache_bsize = 32,
  1044. .num_pmcs = 6,
  1045. .pmc_type = PPC_PMC_G4,
  1046. .cpu_setup = __setup_cpu_745x,
  1047. .oprofile_cpu_type = "ppc/7450",
  1048. .oprofile_type = PPC_OPROFILE_G4,
  1049. .machine_check = machine_check_generic,
  1050. .platform = "ppc7450",
  1051. },
  1052. { /* 7447A */
  1053. .pvr_mask = 0xffff0000,
  1054. .pvr_value = 0x80030000,
  1055. .cpu_name = "7447A",
  1056. .cpu_features = CPU_FTRS_7447A,
  1057. .cpu_user_features = COMMON_USER |
  1058. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1059. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1060. .icache_bsize = 32,
  1061. .dcache_bsize = 32,
  1062. .num_pmcs = 6,
  1063. .pmc_type = PPC_PMC_G4,
  1064. .cpu_setup = __setup_cpu_745x,
  1065. .oprofile_cpu_type = "ppc/7450",
  1066. .oprofile_type = PPC_OPROFILE_G4,
  1067. .machine_check = machine_check_generic,
  1068. .platform = "ppc7450",
  1069. },
  1070. { /* 7448 */
  1071. .pvr_mask = 0xffff0000,
  1072. .pvr_value = 0x80040000,
  1073. .cpu_name = "7448",
  1074. .cpu_features = CPU_FTRS_7448,
  1075. .cpu_user_features = COMMON_USER |
  1076. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  1077. .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS,
  1078. .icache_bsize = 32,
  1079. .dcache_bsize = 32,
  1080. .num_pmcs = 6,
  1081. .pmc_type = PPC_PMC_G4,
  1082. .cpu_setup = __setup_cpu_745x,
  1083. .oprofile_cpu_type = "ppc/7450",
  1084. .oprofile_type = PPC_OPROFILE_G4,
  1085. .machine_check = machine_check_generic,
  1086. .platform = "ppc7450",
  1087. },
  1088. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  1089. .pvr_mask = 0x7fff0000,
  1090. .pvr_value = 0x00810000,
  1091. .cpu_name = "82xx",
  1092. .cpu_features = CPU_FTRS_82XX,
  1093. .cpu_user_features = COMMON_USER,
  1094. .mmu_features = 0,
  1095. .icache_bsize = 32,
  1096. .dcache_bsize = 32,
  1097. .cpu_setup = __setup_cpu_603,
  1098. .machine_check = machine_check_generic,
  1099. .platform = "ppc603",
  1100. },
  1101. { /* All G2_LE (603e core, plus some) have the same pvr */
  1102. .pvr_mask = 0x7fff0000,
  1103. .pvr_value = 0x00820000,
  1104. .cpu_name = "G2_LE",
  1105. .cpu_features = CPU_FTRS_G2_LE,
  1106. .cpu_user_features = COMMON_USER,
  1107. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1108. .icache_bsize = 32,
  1109. .dcache_bsize = 32,
  1110. .cpu_setup = __setup_cpu_603,
  1111. .machine_check = machine_check_generic,
  1112. .platform = "ppc603",
  1113. },
  1114. { /* e300c1 (a 603e core, plus some) on 83xx */
  1115. .pvr_mask = 0x7fff0000,
  1116. .pvr_value = 0x00830000,
  1117. .cpu_name = "e300c1",
  1118. .cpu_features = CPU_FTRS_E300,
  1119. .cpu_user_features = COMMON_USER,
  1120. .mmu_features = MMU_FTR_USE_HIGH_BATS,
  1121. .icache_bsize = 32,
  1122. .dcache_bsize = 32,
  1123. .cpu_setup = __setup_cpu_603,
  1124. .machine_check = machine_check_generic,
  1125. .platform = "ppc603",
  1126. },
  1127. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  1128. .pvr_mask = 0x7fff0000,
  1129. .pvr_value = 0x00840000,
  1130. .cpu_name = "e300c2",
  1131. .cpu_features = CPU_FTRS_E300C2,
  1132. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1133. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1134. MMU_FTR_NEED_DTLB_SW_LRU,
  1135. .icache_bsize = 32,
  1136. .dcache_bsize = 32,
  1137. .cpu_setup = __setup_cpu_603,
  1138. .machine_check = machine_check_generic,
  1139. .platform = "ppc603",
  1140. },
  1141. { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
  1142. .pvr_mask = 0x7fff0000,
  1143. .pvr_value = 0x00850000,
  1144. .cpu_name = "e300c3",
  1145. .cpu_features = CPU_FTRS_E300,
  1146. .cpu_user_features = COMMON_USER,
  1147. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1148. MMU_FTR_NEED_DTLB_SW_LRU,
  1149. .icache_bsize = 32,
  1150. .dcache_bsize = 32,
  1151. .cpu_setup = __setup_cpu_603,
  1152. .num_pmcs = 4,
  1153. .oprofile_cpu_type = "ppc/e300",
  1154. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1155. .platform = "ppc603",
  1156. },
  1157. { /* e300c4 (e300c1, plus one IU) */
  1158. .pvr_mask = 0x7fff0000,
  1159. .pvr_value = 0x00860000,
  1160. .cpu_name = "e300c4",
  1161. .cpu_features = CPU_FTRS_E300,
  1162. .cpu_user_features = COMMON_USER,
  1163. .mmu_features = MMU_FTR_USE_HIGH_BATS |
  1164. MMU_FTR_NEED_DTLB_SW_LRU,
  1165. .icache_bsize = 32,
  1166. .dcache_bsize = 32,
  1167. .cpu_setup = __setup_cpu_603,
  1168. .machine_check = machine_check_generic,
  1169. .num_pmcs = 4,
  1170. .oprofile_cpu_type = "ppc/e300",
  1171. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1172. .platform = "ppc603",
  1173. },
  1174. { /* default match, we assume split I/D cache & TB (non-601)... */
  1175. .pvr_mask = 0x00000000,
  1176. .pvr_value = 0x00000000,
  1177. .cpu_name = "(generic PPC)",
  1178. .cpu_features = CPU_FTRS_CLASSIC32,
  1179. .cpu_user_features = COMMON_USER,
  1180. .mmu_features = MMU_FTR_HPTE_TABLE,
  1181. .icache_bsize = 32,
  1182. .dcache_bsize = 32,
  1183. .machine_check = machine_check_generic,
  1184. .platform = "ppc603",
  1185. },
  1186. #endif /* CLASSIC_PPC */
  1187. #ifdef CONFIG_8xx
  1188. { /* 8xx */
  1189. .pvr_mask = 0xffff0000,
  1190. .pvr_value = 0x00500000,
  1191. .cpu_name = "8xx",
  1192. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  1193. * if the 8xx code is there.... */
  1194. .cpu_features = CPU_FTRS_8XX,
  1195. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1196. .mmu_features = MMU_FTR_TYPE_8xx,
  1197. .icache_bsize = 16,
  1198. .dcache_bsize = 16,
  1199. .platform = "ppc823",
  1200. },
  1201. #endif /* CONFIG_8xx */
  1202. #ifdef CONFIG_40x
  1203. { /* 403GC */
  1204. .pvr_mask = 0xffffff00,
  1205. .pvr_value = 0x00200200,
  1206. .cpu_name = "403GC",
  1207. .cpu_features = CPU_FTRS_40X,
  1208. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1209. .mmu_features = MMU_FTR_TYPE_40x,
  1210. .icache_bsize = 16,
  1211. .dcache_bsize = 16,
  1212. .machine_check = machine_check_4xx,
  1213. .platform = "ppc403",
  1214. },
  1215. { /* 403GCX */
  1216. .pvr_mask = 0xffffff00,
  1217. .pvr_value = 0x00201400,
  1218. .cpu_name = "403GCX",
  1219. .cpu_features = CPU_FTRS_40X,
  1220. .cpu_user_features = PPC_FEATURE_32 |
  1221. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  1222. .mmu_features = MMU_FTR_TYPE_40x,
  1223. .icache_bsize = 16,
  1224. .dcache_bsize = 16,
  1225. .machine_check = machine_check_4xx,
  1226. .platform = "ppc403",
  1227. },
  1228. { /* 403G ?? */
  1229. .pvr_mask = 0xffff0000,
  1230. .pvr_value = 0x00200000,
  1231. .cpu_name = "403G ??",
  1232. .cpu_features = CPU_FTRS_40X,
  1233. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1234. .mmu_features = MMU_FTR_TYPE_40x,
  1235. .icache_bsize = 16,
  1236. .dcache_bsize = 16,
  1237. .machine_check = machine_check_4xx,
  1238. .platform = "ppc403",
  1239. },
  1240. { /* 405GP */
  1241. .pvr_mask = 0xffff0000,
  1242. .pvr_value = 0x40110000,
  1243. .cpu_name = "405GP",
  1244. .cpu_features = CPU_FTRS_40X,
  1245. .cpu_user_features = PPC_FEATURE_32 |
  1246. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1247. .mmu_features = MMU_FTR_TYPE_40x,
  1248. .icache_bsize = 32,
  1249. .dcache_bsize = 32,
  1250. .machine_check = machine_check_4xx,
  1251. .platform = "ppc405",
  1252. },
  1253. { /* STB 03xxx */
  1254. .pvr_mask = 0xffff0000,
  1255. .pvr_value = 0x40130000,
  1256. .cpu_name = "STB03xxx",
  1257. .cpu_features = CPU_FTRS_40X,
  1258. .cpu_user_features = PPC_FEATURE_32 |
  1259. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1260. .mmu_features = MMU_FTR_TYPE_40x,
  1261. .icache_bsize = 32,
  1262. .dcache_bsize = 32,
  1263. .machine_check = machine_check_4xx,
  1264. .platform = "ppc405",
  1265. },
  1266. { /* STB 04xxx */
  1267. .pvr_mask = 0xffff0000,
  1268. .pvr_value = 0x41810000,
  1269. .cpu_name = "STB04xxx",
  1270. .cpu_features = CPU_FTRS_40X,
  1271. .cpu_user_features = PPC_FEATURE_32 |
  1272. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1273. .mmu_features = MMU_FTR_TYPE_40x,
  1274. .icache_bsize = 32,
  1275. .dcache_bsize = 32,
  1276. .machine_check = machine_check_4xx,
  1277. .platform = "ppc405",
  1278. },
  1279. { /* NP405L */
  1280. .pvr_mask = 0xffff0000,
  1281. .pvr_value = 0x41610000,
  1282. .cpu_name = "NP405L",
  1283. .cpu_features = CPU_FTRS_40X,
  1284. .cpu_user_features = PPC_FEATURE_32 |
  1285. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1286. .mmu_features = MMU_FTR_TYPE_40x,
  1287. .icache_bsize = 32,
  1288. .dcache_bsize = 32,
  1289. .machine_check = machine_check_4xx,
  1290. .platform = "ppc405",
  1291. },
  1292. { /* NP4GS3 */
  1293. .pvr_mask = 0xffff0000,
  1294. .pvr_value = 0x40B10000,
  1295. .cpu_name = "NP4GS3",
  1296. .cpu_features = CPU_FTRS_40X,
  1297. .cpu_user_features = PPC_FEATURE_32 |
  1298. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1299. .mmu_features = MMU_FTR_TYPE_40x,
  1300. .icache_bsize = 32,
  1301. .dcache_bsize = 32,
  1302. .machine_check = machine_check_4xx,
  1303. .platform = "ppc405",
  1304. },
  1305. { /* NP405H */
  1306. .pvr_mask = 0xffff0000,
  1307. .pvr_value = 0x41410000,
  1308. .cpu_name = "NP405H",
  1309. .cpu_features = CPU_FTRS_40X,
  1310. .cpu_user_features = PPC_FEATURE_32 |
  1311. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1312. .mmu_features = MMU_FTR_TYPE_40x,
  1313. .icache_bsize = 32,
  1314. .dcache_bsize = 32,
  1315. .machine_check = machine_check_4xx,
  1316. .platform = "ppc405",
  1317. },
  1318. { /* 405GPr */
  1319. .pvr_mask = 0xffff0000,
  1320. .pvr_value = 0x50910000,
  1321. .cpu_name = "405GPr",
  1322. .cpu_features = CPU_FTRS_40X,
  1323. .cpu_user_features = PPC_FEATURE_32 |
  1324. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1325. .mmu_features = MMU_FTR_TYPE_40x,
  1326. .icache_bsize = 32,
  1327. .dcache_bsize = 32,
  1328. .machine_check = machine_check_4xx,
  1329. .platform = "ppc405",
  1330. },
  1331. { /* STBx25xx */
  1332. .pvr_mask = 0xffff0000,
  1333. .pvr_value = 0x51510000,
  1334. .cpu_name = "STBx25xx",
  1335. .cpu_features = CPU_FTRS_40X,
  1336. .cpu_user_features = PPC_FEATURE_32 |
  1337. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1338. .mmu_features = MMU_FTR_TYPE_40x,
  1339. .icache_bsize = 32,
  1340. .dcache_bsize = 32,
  1341. .machine_check = machine_check_4xx,
  1342. .platform = "ppc405",
  1343. },
  1344. { /* 405LP */
  1345. .pvr_mask = 0xffff0000,
  1346. .pvr_value = 0x41F10000,
  1347. .cpu_name = "405LP",
  1348. .cpu_features = CPU_FTRS_40X,
  1349. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1350. .mmu_features = MMU_FTR_TYPE_40x,
  1351. .icache_bsize = 32,
  1352. .dcache_bsize = 32,
  1353. .machine_check = machine_check_4xx,
  1354. .platform = "ppc405",
  1355. },
  1356. { /* Xilinx Virtex-II Pro */
  1357. .pvr_mask = 0xfffff000,
  1358. .pvr_value = 0x20010000,
  1359. .cpu_name = "Virtex-II Pro",
  1360. .cpu_features = CPU_FTRS_40X,
  1361. .cpu_user_features = PPC_FEATURE_32 |
  1362. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1363. .mmu_features = MMU_FTR_TYPE_40x,
  1364. .icache_bsize = 32,
  1365. .dcache_bsize = 32,
  1366. .machine_check = machine_check_4xx,
  1367. .platform = "ppc405",
  1368. },
  1369. { /* Xilinx Virtex-4 FX */
  1370. .pvr_mask = 0xfffff000,
  1371. .pvr_value = 0x20011000,
  1372. .cpu_name = "Virtex-4 FX",
  1373. .cpu_features = CPU_FTRS_40X,
  1374. .cpu_user_features = PPC_FEATURE_32 |
  1375. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1376. .mmu_features = MMU_FTR_TYPE_40x,
  1377. .icache_bsize = 32,
  1378. .dcache_bsize = 32,
  1379. .machine_check = machine_check_4xx,
  1380. .platform = "ppc405",
  1381. },
  1382. { /* 405EP */
  1383. .pvr_mask = 0xffff0000,
  1384. .pvr_value = 0x51210000,
  1385. .cpu_name = "405EP",
  1386. .cpu_features = CPU_FTRS_40X,
  1387. .cpu_user_features = PPC_FEATURE_32 |
  1388. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1389. .mmu_features = MMU_FTR_TYPE_40x,
  1390. .icache_bsize = 32,
  1391. .dcache_bsize = 32,
  1392. .machine_check = machine_check_4xx,
  1393. .platform = "ppc405",
  1394. },
  1395. { /* 405EX Rev. A/B with Security */
  1396. .pvr_mask = 0xffff000f,
  1397. .pvr_value = 0x12910007,
  1398. .cpu_name = "405EX Rev. A/B",
  1399. .cpu_features = CPU_FTRS_40X,
  1400. .cpu_user_features = PPC_FEATURE_32 |
  1401. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1402. .mmu_features = MMU_FTR_TYPE_40x,
  1403. .icache_bsize = 32,
  1404. .dcache_bsize = 32,
  1405. .machine_check = machine_check_4xx,
  1406. .platform = "ppc405",
  1407. },
  1408. { /* 405EX Rev. C without Security */
  1409. .pvr_mask = 0xffff000f,
  1410. .pvr_value = 0x1291000d,
  1411. .cpu_name = "405EX Rev. C",
  1412. .cpu_features = CPU_FTRS_40X,
  1413. .cpu_user_features = PPC_FEATURE_32 |
  1414. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1415. .mmu_features = MMU_FTR_TYPE_40x,
  1416. .icache_bsize = 32,
  1417. .dcache_bsize = 32,
  1418. .machine_check = machine_check_4xx,
  1419. .platform = "ppc405",
  1420. },
  1421. { /* 405EX Rev. C with Security */
  1422. .pvr_mask = 0xffff000f,
  1423. .pvr_value = 0x1291000f,
  1424. .cpu_name = "405EX Rev. C",
  1425. .cpu_features = CPU_FTRS_40X,
  1426. .cpu_user_features = PPC_FEATURE_32 |
  1427. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1428. .mmu_features = MMU_FTR_TYPE_40x,
  1429. .icache_bsize = 32,
  1430. .dcache_bsize = 32,
  1431. .machine_check = machine_check_4xx,
  1432. .platform = "ppc405",
  1433. },
  1434. { /* 405EX Rev. D without Security */
  1435. .pvr_mask = 0xffff000f,
  1436. .pvr_value = 0x12910003,
  1437. .cpu_name = "405EX Rev. D",
  1438. .cpu_features = CPU_FTRS_40X,
  1439. .cpu_user_features = PPC_FEATURE_32 |
  1440. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1441. .mmu_features = MMU_FTR_TYPE_40x,
  1442. .icache_bsize = 32,
  1443. .dcache_bsize = 32,
  1444. .machine_check = machine_check_4xx,
  1445. .platform = "ppc405",
  1446. },
  1447. { /* 405EX Rev. D with Security */
  1448. .pvr_mask = 0xffff000f,
  1449. .pvr_value = 0x12910005,
  1450. .cpu_name = "405EX Rev. D",
  1451. .cpu_features = CPU_FTRS_40X,
  1452. .cpu_user_features = PPC_FEATURE_32 |
  1453. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1454. .mmu_features = MMU_FTR_TYPE_40x,
  1455. .icache_bsize = 32,
  1456. .dcache_bsize = 32,
  1457. .machine_check = machine_check_4xx,
  1458. .platform = "ppc405",
  1459. },
  1460. { /* 405EXr Rev. A/B without Security */
  1461. .pvr_mask = 0xffff000f,
  1462. .pvr_value = 0x12910001,
  1463. .cpu_name = "405EXr Rev. A/B",
  1464. .cpu_features = CPU_FTRS_40X,
  1465. .cpu_user_features = PPC_FEATURE_32 |
  1466. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1467. .mmu_features = MMU_FTR_TYPE_40x,
  1468. .icache_bsize = 32,
  1469. .dcache_bsize = 32,
  1470. .machine_check = machine_check_4xx,
  1471. .platform = "ppc405",
  1472. },
  1473. { /* 405EXr Rev. C without Security */
  1474. .pvr_mask = 0xffff000f,
  1475. .pvr_value = 0x12910009,
  1476. .cpu_name = "405EXr Rev. C",
  1477. .cpu_features = CPU_FTRS_40X,
  1478. .cpu_user_features = PPC_FEATURE_32 |
  1479. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1480. .mmu_features = MMU_FTR_TYPE_40x,
  1481. .icache_bsize = 32,
  1482. .dcache_bsize = 32,
  1483. .machine_check = machine_check_4xx,
  1484. .platform = "ppc405",
  1485. },
  1486. { /* 405EXr Rev. C with Security */
  1487. .pvr_mask = 0xffff000f,
  1488. .pvr_value = 0x1291000b,
  1489. .cpu_name = "405EXr Rev. C",
  1490. .cpu_features = CPU_FTRS_40X,
  1491. .cpu_user_features = PPC_FEATURE_32 |
  1492. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1493. .mmu_features = MMU_FTR_TYPE_40x,
  1494. .icache_bsize = 32,
  1495. .dcache_bsize = 32,
  1496. .machine_check = machine_check_4xx,
  1497. .platform = "ppc405",
  1498. },
  1499. { /* 405EXr Rev. D without Security */
  1500. .pvr_mask = 0xffff000f,
  1501. .pvr_value = 0x12910000,
  1502. .cpu_name = "405EXr Rev. D",
  1503. .cpu_features = CPU_FTRS_40X,
  1504. .cpu_user_features = PPC_FEATURE_32 |
  1505. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1506. .mmu_features = MMU_FTR_TYPE_40x,
  1507. .icache_bsize = 32,
  1508. .dcache_bsize = 32,
  1509. .machine_check = machine_check_4xx,
  1510. .platform = "ppc405",
  1511. },
  1512. { /* 405EXr Rev. D with Security */
  1513. .pvr_mask = 0xffff000f,
  1514. .pvr_value = 0x12910002,
  1515. .cpu_name = "405EXr Rev. D",
  1516. .cpu_features = CPU_FTRS_40X,
  1517. .cpu_user_features = PPC_FEATURE_32 |
  1518. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1519. .mmu_features = MMU_FTR_TYPE_40x,
  1520. .icache_bsize = 32,
  1521. .dcache_bsize = 32,
  1522. .machine_check = machine_check_4xx,
  1523. .platform = "ppc405",
  1524. },
  1525. {
  1526. /* 405EZ */
  1527. .pvr_mask = 0xffff0000,
  1528. .pvr_value = 0x41510000,
  1529. .cpu_name = "405EZ",
  1530. .cpu_features = CPU_FTRS_40X,
  1531. .cpu_user_features = PPC_FEATURE_32 |
  1532. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1533. .mmu_features = MMU_FTR_TYPE_40x,
  1534. .icache_bsize = 32,
  1535. .dcache_bsize = 32,
  1536. .machine_check = machine_check_4xx,
  1537. .platform = "ppc405",
  1538. },
  1539. { /* APM8018X */
  1540. .pvr_mask = 0xffff0000,
  1541. .pvr_value = 0x7ff11432,
  1542. .cpu_name = "APM8018X",
  1543. .cpu_features = CPU_FTRS_40X,
  1544. .cpu_user_features = PPC_FEATURE_32 |
  1545. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1546. .mmu_features = MMU_FTR_TYPE_40x,
  1547. .icache_bsize = 32,
  1548. .dcache_bsize = 32,
  1549. .machine_check = machine_check_4xx,
  1550. .platform = "ppc405",
  1551. },
  1552. { /* default match */
  1553. .pvr_mask = 0x00000000,
  1554. .pvr_value = 0x00000000,
  1555. .cpu_name = "(generic 40x PPC)",
  1556. .cpu_features = CPU_FTRS_40X,
  1557. .cpu_user_features = PPC_FEATURE_32 |
  1558. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1559. .mmu_features = MMU_FTR_TYPE_40x,
  1560. .icache_bsize = 32,
  1561. .dcache_bsize = 32,
  1562. .machine_check = machine_check_4xx,
  1563. .platform = "ppc405",
  1564. }
  1565. #endif /* CONFIG_40x */
  1566. #ifdef CONFIG_44x
  1567. {
  1568. .pvr_mask = 0xf0000fff,
  1569. .pvr_value = 0x40000850,
  1570. .cpu_name = "440GR Rev. A",
  1571. .cpu_features = CPU_FTRS_44X,
  1572. .cpu_user_features = COMMON_USER_BOOKE,
  1573. .mmu_features = MMU_FTR_TYPE_44x,
  1574. .icache_bsize = 32,
  1575. .dcache_bsize = 32,
  1576. .machine_check = machine_check_4xx,
  1577. .platform = "ppc440",
  1578. },
  1579. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1580. .pvr_mask = 0xf0000fff,
  1581. .pvr_value = 0x40000858,
  1582. .cpu_name = "440EP Rev. A",
  1583. .cpu_features = CPU_FTRS_44X,
  1584. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1585. .mmu_features = MMU_FTR_TYPE_44x,
  1586. .icache_bsize = 32,
  1587. .dcache_bsize = 32,
  1588. .cpu_setup = __setup_cpu_440ep,
  1589. .machine_check = machine_check_4xx,
  1590. .platform = "ppc440",
  1591. },
  1592. {
  1593. .pvr_mask = 0xf0000fff,
  1594. .pvr_value = 0x400008d3,
  1595. .cpu_name = "440GR Rev. B",
  1596. .cpu_features = CPU_FTRS_44X,
  1597. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1598. .mmu_features = MMU_FTR_TYPE_44x,
  1599. .icache_bsize = 32,
  1600. .dcache_bsize = 32,
  1601. .machine_check = machine_check_4xx,
  1602. .platform = "ppc440",
  1603. },
  1604. { /* Matches both physical and logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1605. .pvr_mask = 0xf0000ff7,
  1606. .pvr_value = 0x400008d4,
  1607. .cpu_name = "440EP Rev. C",
  1608. .cpu_features = CPU_FTRS_44X,
  1609. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1610. .mmu_features = MMU_FTR_TYPE_44x,
  1611. .icache_bsize = 32,
  1612. .dcache_bsize = 32,
  1613. .cpu_setup = __setup_cpu_440ep,
  1614. .machine_check = machine_check_4xx,
  1615. .platform = "ppc440",
  1616. },
  1617. { /* Use logical PVR for 440EP (logical pvr = pvr | 0x8) */
  1618. .pvr_mask = 0xf0000fff,
  1619. .pvr_value = 0x400008db,
  1620. .cpu_name = "440EP Rev. B",
  1621. .cpu_features = CPU_FTRS_44X,
  1622. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1623. .mmu_features = MMU_FTR_TYPE_44x,
  1624. .icache_bsize = 32,
  1625. .dcache_bsize = 32,
  1626. .cpu_setup = __setup_cpu_440ep,
  1627. .machine_check = machine_check_4xx,
  1628. .platform = "ppc440",
  1629. },
  1630. { /* 440GRX */
  1631. .pvr_mask = 0xf0000ffb,
  1632. .pvr_value = 0x200008D0,
  1633. .cpu_name = "440GRX",
  1634. .cpu_features = CPU_FTRS_44X,
  1635. .cpu_user_features = COMMON_USER_BOOKE,
  1636. .mmu_features = MMU_FTR_TYPE_44x,
  1637. .icache_bsize = 32,
  1638. .dcache_bsize = 32,
  1639. .cpu_setup = __setup_cpu_440grx,
  1640. .machine_check = machine_check_440A,
  1641. .platform = "ppc440",
  1642. },
  1643. { /* Use logical PVR for 440EPx (logical pvr = pvr | 0x8) */
  1644. .pvr_mask = 0xf0000ffb,
  1645. .pvr_value = 0x200008D8,
  1646. .cpu_name = "440EPX",
  1647. .cpu_features = CPU_FTRS_44X,
  1648. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1649. .mmu_features = MMU_FTR_TYPE_44x,
  1650. .icache_bsize = 32,
  1651. .dcache_bsize = 32,
  1652. .cpu_setup = __setup_cpu_440epx,
  1653. .machine_check = machine_check_440A,
  1654. .platform = "ppc440",
  1655. },
  1656. { /* 440GP Rev. B */
  1657. .pvr_mask = 0xf0000fff,
  1658. .pvr_value = 0x40000440,
  1659. .cpu_name = "440GP Rev. B",
  1660. .cpu_features = CPU_FTRS_44X,
  1661. .cpu_user_features = COMMON_USER_BOOKE,
  1662. .mmu_features = MMU_FTR_TYPE_44x,
  1663. .icache_bsize = 32,
  1664. .dcache_bsize = 32,
  1665. .machine_check = machine_check_4xx,
  1666. .platform = "ppc440gp",
  1667. },
  1668. { /* 440GP Rev. C */
  1669. .pvr_mask = 0xf0000fff,
  1670. .pvr_value = 0x40000481,
  1671. .cpu_name = "440GP Rev. C",
  1672. .cpu_features = CPU_FTRS_44X,
  1673. .cpu_user_features = COMMON_USER_BOOKE,
  1674. .mmu_features = MMU_FTR_TYPE_44x,
  1675. .icache_bsize = 32,
  1676. .dcache_bsize = 32,
  1677. .machine_check = machine_check_4xx,
  1678. .platform = "ppc440gp",
  1679. },
  1680. { /* 440GX Rev. A */
  1681. .pvr_mask = 0xf0000fff,
  1682. .pvr_value = 0x50000850,
  1683. .cpu_name = "440GX Rev. A",
  1684. .cpu_features = CPU_FTRS_44X,
  1685. .cpu_user_features = COMMON_USER_BOOKE,
  1686. .mmu_features = MMU_FTR_TYPE_44x,
  1687. .icache_bsize = 32,
  1688. .dcache_bsize = 32,
  1689. .cpu_setup = __setup_cpu_440gx,
  1690. .machine_check = machine_check_440A,
  1691. .platform = "ppc440",
  1692. },
  1693. { /* 440GX Rev. B */
  1694. .pvr_mask = 0xf0000fff,
  1695. .pvr_value = 0x50000851,
  1696. .cpu_name = "440GX Rev. B",
  1697. .cpu_features = CPU_FTRS_44X,
  1698. .cpu_user_features = COMMON_USER_BOOKE,
  1699. .mmu_features = MMU_FTR_TYPE_44x,
  1700. .icache_bsize = 32,
  1701. .dcache_bsize = 32,
  1702. .cpu_setup = __setup_cpu_440gx,
  1703. .machine_check = machine_check_440A,
  1704. .platform = "ppc440",
  1705. },
  1706. { /* 440GX Rev. C */
  1707. .pvr_mask = 0xf0000fff,
  1708. .pvr_value = 0x50000892,
  1709. .cpu_name = "440GX Rev. C",
  1710. .cpu_features = CPU_FTRS_44X,
  1711. .cpu_user_features = COMMON_USER_BOOKE,
  1712. .mmu_features = MMU_FTR_TYPE_44x,
  1713. .icache_bsize = 32,
  1714. .dcache_bsize = 32,
  1715. .cpu_setup = __setup_cpu_440gx,
  1716. .machine_check = machine_check_440A,
  1717. .platform = "ppc440",
  1718. },
  1719. { /* 440GX Rev. F */
  1720. .pvr_mask = 0xf0000fff,
  1721. .pvr_value = 0x50000894,
  1722. .cpu_name = "440GX Rev. F",
  1723. .cpu_features = CPU_FTRS_44X,
  1724. .cpu_user_features = COMMON_USER_BOOKE,
  1725. .mmu_features = MMU_FTR_TYPE_44x,
  1726. .icache_bsize = 32,
  1727. .dcache_bsize = 32,
  1728. .cpu_setup = __setup_cpu_440gx,
  1729. .machine_check = machine_check_440A,
  1730. .platform = "ppc440",
  1731. },
  1732. { /* 440SP Rev. A */
  1733. .pvr_mask = 0xfff00fff,
  1734. .pvr_value = 0x53200891,
  1735. .cpu_name = "440SP Rev. A",
  1736. .cpu_features = CPU_FTRS_44X,
  1737. .cpu_user_features = COMMON_USER_BOOKE,
  1738. .mmu_features = MMU_FTR_TYPE_44x,
  1739. .icache_bsize = 32,
  1740. .dcache_bsize = 32,
  1741. .machine_check = machine_check_4xx,
  1742. .platform = "ppc440",
  1743. },
  1744. { /* 440SPe Rev. A */
  1745. .pvr_mask = 0xfff00fff,
  1746. .pvr_value = 0x53400890,
  1747. .cpu_name = "440SPe Rev. A",
  1748. .cpu_features = CPU_FTRS_44X,
  1749. .cpu_user_features = COMMON_USER_BOOKE,
  1750. .mmu_features = MMU_FTR_TYPE_44x,
  1751. .icache_bsize = 32,
  1752. .dcache_bsize = 32,
  1753. .cpu_setup = __setup_cpu_440spe,
  1754. .machine_check = machine_check_440A,
  1755. .platform = "ppc440",
  1756. },
  1757. { /* 440SPe Rev. B */
  1758. .pvr_mask = 0xfff00fff,
  1759. .pvr_value = 0x53400891,
  1760. .cpu_name = "440SPe Rev. B",
  1761. .cpu_features = CPU_FTRS_44X,
  1762. .cpu_user_features = COMMON_USER_BOOKE,
  1763. .mmu_features = MMU_FTR_TYPE_44x,
  1764. .icache_bsize = 32,
  1765. .dcache_bsize = 32,
  1766. .cpu_setup = __setup_cpu_440spe,
  1767. .machine_check = machine_check_440A,
  1768. .platform = "ppc440",
  1769. },
  1770. { /* 440 in Xilinx Virtex-5 FXT */
  1771. .pvr_mask = 0xfffffff0,
  1772. .pvr_value = 0x7ff21910,
  1773. .cpu_name = "440 in Virtex-5 FXT",
  1774. .cpu_features = CPU_FTRS_44X,
  1775. .cpu_user_features = COMMON_USER_BOOKE,
  1776. .mmu_features = MMU_FTR_TYPE_44x,
  1777. .icache_bsize = 32,
  1778. .dcache_bsize = 32,
  1779. .cpu_setup = __setup_cpu_440x5,
  1780. .machine_check = machine_check_440A,
  1781. .platform = "ppc440",
  1782. },
  1783. { /* 460EX */
  1784. .pvr_mask = 0xffff0006,
  1785. .pvr_value = 0x13020002,
  1786. .cpu_name = "460EX",
  1787. .cpu_features = CPU_FTRS_440x6,
  1788. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1789. .mmu_features = MMU_FTR_TYPE_44x,
  1790. .icache_bsize = 32,
  1791. .dcache_bsize = 32,
  1792. .cpu_setup = __setup_cpu_460ex,
  1793. .machine_check = machine_check_440A,
  1794. .platform = "ppc440",
  1795. },
  1796. { /* 460EX Rev B */
  1797. .pvr_mask = 0xffff0007,
  1798. .pvr_value = 0x13020004,
  1799. .cpu_name = "460EX Rev. B",
  1800. .cpu_features = CPU_FTRS_440x6,
  1801. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1802. .mmu_features = MMU_FTR_TYPE_44x,
  1803. .icache_bsize = 32,
  1804. .dcache_bsize = 32,
  1805. .cpu_setup = __setup_cpu_460ex,
  1806. .machine_check = machine_check_440A,
  1807. .platform = "ppc440",
  1808. },
  1809. { /* 460GT */
  1810. .pvr_mask = 0xffff0006,
  1811. .pvr_value = 0x13020000,
  1812. .cpu_name = "460GT",
  1813. .cpu_features = CPU_FTRS_440x6,
  1814. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1815. .mmu_features = MMU_FTR_TYPE_44x,
  1816. .icache_bsize = 32,
  1817. .dcache_bsize = 32,
  1818. .cpu_setup = __setup_cpu_460gt,
  1819. .machine_check = machine_check_440A,
  1820. .platform = "ppc440",
  1821. },
  1822. { /* 460GT Rev B */
  1823. .pvr_mask = 0xffff0007,
  1824. .pvr_value = 0x13020005,
  1825. .cpu_name = "460GT Rev. B",
  1826. .cpu_features = CPU_FTRS_440x6,
  1827. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1828. .mmu_features = MMU_FTR_TYPE_44x,
  1829. .icache_bsize = 32,
  1830. .dcache_bsize = 32,
  1831. .cpu_setup = __setup_cpu_460gt,
  1832. .machine_check = machine_check_440A,
  1833. .platform = "ppc440",
  1834. },
  1835. { /* 460SX */
  1836. .pvr_mask = 0xffffff00,
  1837. .pvr_value = 0x13541800,
  1838. .cpu_name = "460SX",
  1839. .cpu_features = CPU_FTRS_44X,
  1840. .cpu_user_features = COMMON_USER_BOOKE,
  1841. .mmu_features = MMU_FTR_TYPE_44x,
  1842. .icache_bsize = 32,
  1843. .dcache_bsize = 32,
  1844. .cpu_setup = __setup_cpu_460sx,
  1845. .machine_check = machine_check_440A,
  1846. .platform = "ppc440",
  1847. },
  1848. { /* 464 in APM821xx */
  1849. .pvr_mask = 0xfffffff0,
  1850. .pvr_value = 0x12C41C80,
  1851. .cpu_name = "APM821XX",
  1852. .cpu_features = CPU_FTRS_44X,
  1853. .cpu_user_features = COMMON_USER_BOOKE |
  1854. PPC_FEATURE_HAS_FPU,
  1855. .mmu_features = MMU_FTR_TYPE_44x,
  1856. .icache_bsize = 32,
  1857. .dcache_bsize = 32,
  1858. .cpu_setup = __setup_cpu_apm821xx,
  1859. .machine_check = machine_check_440A,
  1860. .platform = "ppc440",
  1861. },
  1862. { /* 476 DD2 core */
  1863. .pvr_mask = 0xffffffff,
  1864. .pvr_value = 0x11a52080,
  1865. .cpu_name = "476",
  1866. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1867. .cpu_user_features = COMMON_USER_BOOKE |
  1868. PPC_FEATURE_HAS_FPU,
  1869. .mmu_features = MMU_FTR_TYPE_47x |
  1870. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1871. .icache_bsize = 32,
  1872. .dcache_bsize = 128,
  1873. .machine_check = machine_check_47x,
  1874. .platform = "ppc470",
  1875. },
  1876. { /* 476fpe */
  1877. .pvr_mask = 0xffff0000,
  1878. .pvr_value = 0x7ff50000,
  1879. .cpu_name = "476fpe",
  1880. .cpu_features = CPU_FTRS_47X | CPU_FTR_476_DD2,
  1881. .cpu_user_features = COMMON_USER_BOOKE |
  1882. PPC_FEATURE_HAS_FPU,
  1883. .mmu_features = MMU_FTR_TYPE_47x |
  1884. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1885. .icache_bsize = 32,
  1886. .dcache_bsize = 128,
  1887. .machine_check = machine_check_47x,
  1888. .platform = "ppc470",
  1889. },
  1890. { /* 476 iss */
  1891. .pvr_mask = 0xffff0000,
  1892. .pvr_value = 0x00050000,
  1893. .cpu_name = "476",
  1894. .cpu_features = CPU_FTRS_47X,
  1895. .cpu_user_features = COMMON_USER_BOOKE |
  1896. PPC_FEATURE_HAS_FPU,
  1897. .mmu_features = MMU_FTR_TYPE_47x |
  1898. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1899. .icache_bsize = 32,
  1900. .dcache_bsize = 128,
  1901. .machine_check = machine_check_47x,
  1902. .platform = "ppc470",
  1903. },
  1904. { /* 476 others */
  1905. .pvr_mask = 0xffff0000,
  1906. .pvr_value = 0x11a50000,
  1907. .cpu_name = "476",
  1908. .cpu_features = CPU_FTRS_47X,
  1909. .cpu_user_features = COMMON_USER_BOOKE |
  1910. PPC_FEATURE_HAS_FPU,
  1911. .mmu_features = MMU_FTR_TYPE_47x |
  1912. MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_LOCK_BCAST_INVAL,
  1913. .icache_bsize = 32,
  1914. .dcache_bsize = 128,
  1915. .machine_check = machine_check_47x,
  1916. .platform = "ppc470",
  1917. },
  1918. { /* default match */
  1919. .pvr_mask = 0x00000000,
  1920. .pvr_value = 0x00000000,
  1921. .cpu_name = "(generic 44x PPC)",
  1922. .cpu_features = CPU_FTRS_44X,
  1923. .cpu_user_features = COMMON_USER_BOOKE,
  1924. .mmu_features = MMU_FTR_TYPE_44x,
  1925. .icache_bsize = 32,
  1926. .dcache_bsize = 32,
  1927. .machine_check = machine_check_4xx,
  1928. .platform = "ppc440",
  1929. }
  1930. #endif /* CONFIG_44x */
  1931. #ifdef CONFIG_E200
  1932. { /* e200z5 */
  1933. .pvr_mask = 0xfff00000,
  1934. .pvr_value = 0x81000000,
  1935. .cpu_name = "e200z5",
  1936. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1937. .cpu_features = CPU_FTRS_E200,
  1938. .cpu_user_features = COMMON_USER_BOOKE |
  1939. PPC_FEATURE_HAS_EFP_SINGLE |
  1940. PPC_FEATURE_UNIFIED_CACHE,
  1941. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1942. .dcache_bsize = 32,
  1943. .machine_check = machine_check_e200,
  1944. .platform = "ppc5554",
  1945. },
  1946. { /* e200z6 */
  1947. .pvr_mask = 0xfff00000,
  1948. .pvr_value = 0x81100000,
  1949. .cpu_name = "e200z6",
  1950. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1951. .cpu_features = CPU_FTRS_E200,
  1952. .cpu_user_features = COMMON_USER_BOOKE |
  1953. PPC_FEATURE_HAS_SPE_COMP |
  1954. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  1955. PPC_FEATURE_UNIFIED_CACHE,
  1956. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1957. .dcache_bsize = 32,
  1958. .machine_check = machine_check_e200,
  1959. .platform = "ppc5554",
  1960. },
  1961. { /* default match */
  1962. .pvr_mask = 0x00000000,
  1963. .pvr_value = 0x00000000,
  1964. .cpu_name = "(generic E200 PPC)",
  1965. .cpu_features = CPU_FTRS_E200,
  1966. .cpu_user_features = COMMON_USER_BOOKE |
  1967. PPC_FEATURE_HAS_EFP_SINGLE |
  1968. PPC_FEATURE_UNIFIED_CACHE,
  1969. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1970. .dcache_bsize = 32,
  1971. .cpu_setup = __setup_cpu_e200,
  1972. .machine_check = machine_check_e200,
  1973. .platform = "ppc5554",
  1974. }
  1975. #endif /* CONFIG_E200 */
  1976. #endif /* CONFIG_PPC32 */
  1977. #ifdef CONFIG_E500
  1978. #ifdef CONFIG_PPC32
  1979. { /* e500 */
  1980. .pvr_mask = 0xffff0000,
  1981. .pvr_value = 0x80200000,
  1982. .cpu_name = "e500",
  1983. .cpu_features = CPU_FTRS_E500,
  1984. .cpu_user_features = COMMON_USER_BOOKE |
  1985. PPC_FEATURE_HAS_SPE_COMP |
  1986. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  1987. .mmu_features = MMU_FTR_TYPE_FSL_E,
  1988. .icache_bsize = 32,
  1989. .dcache_bsize = 32,
  1990. .num_pmcs = 4,
  1991. .oprofile_cpu_type = "ppc/e500",
  1992. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  1993. .cpu_setup = __setup_cpu_e500v1,
  1994. .machine_check = machine_check_e500,
  1995. .platform = "ppc8540",
  1996. },
  1997. { /* e500v2 */
  1998. .pvr_mask = 0xffff0000,
  1999. .pvr_value = 0x80210000,
  2000. .cpu_name = "e500v2",
  2001. .cpu_features = CPU_FTRS_E500_2,
  2002. .cpu_user_features = COMMON_USER_BOOKE |
  2003. PPC_FEATURE_HAS_SPE_COMP |
  2004. PPC_FEATURE_HAS_EFP_SINGLE_COMP |
  2005. PPC_FEATURE_HAS_EFP_DOUBLE_COMP,
  2006. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS,
  2007. .icache_bsize = 32,
  2008. .dcache_bsize = 32,
  2009. .num_pmcs = 4,
  2010. .oprofile_cpu_type = "ppc/e500",
  2011. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2012. .cpu_setup = __setup_cpu_e500v2,
  2013. .machine_check = machine_check_e500,
  2014. .platform = "ppc8548",
  2015. },
  2016. { /* e500mc */
  2017. .pvr_mask = 0xffff0000,
  2018. .pvr_value = 0x80230000,
  2019. .cpu_name = "e500mc",
  2020. .cpu_features = CPU_FTRS_E500MC,
  2021. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2022. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2023. MMU_FTR_USE_TLBILX,
  2024. .icache_bsize = 64,
  2025. .dcache_bsize = 64,
  2026. .num_pmcs = 4,
  2027. .oprofile_cpu_type = "ppc/e500mc",
  2028. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2029. .cpu_setup = __setup_cpu_e500mc,
  2030. .machine_check = machine_check_e500mc,
  2031. .platform = "ppce500mc",
  2032. },
  2033. #endif /* CONFIG_PPC32 */
  2034. { /* e5500 */
  2035. .pvr_mask = 0xffff0000,
  2036. .pvr_value = 0x80240000,
  2037. .cpu_name = "e5500",
  2038. .cpu_features = CPU_FTRS_E5500,
  2039. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2040. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2041. MMU_FTR_USE_TLBILX,
  2042. .icache_bsize = 64,
  2043. .dcache_bsize = 64,
  2044. .num_pmcs = 4,
  2045. .oprofile_cpu_type = "ppc/e500mc",
  2046. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2047. .cpu_setup = __setup_cpu_e5500,
  2048. #ifndef CONFIG_PPC32
  2049. .cpu_restore = __restore_cpu_e5500,
  2050. #endif
  2051. .machine_check = machine_check_e500mc,
  2052. .platform = "ppce5500",
  2053. },
  2054. { /* e6500 */
  2055. .pvr_mask = 0xffff0000,
  2056. .pvr_value = 0x80400000,
  2057. .cpu_name = "e6500",
  2058. .cpu_features = CPU_FTRS_E6500,
  2059. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  2060. .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
  2061. MMU_FTR_USE_TLBILX,
  2062. .icache_bsize = 64,
  2063. .dcache_bsize = 64,
  2064. .num_pmcs = 4,
  2065. .oprofile_cpu_type = "ppc/e6500",
  2066. .oprofile_type = PPC_OPROFILE_FSL_EMB,
  2067. .cpu_setup = __setup_cpu_e5500,
  2068. #ifndef CONFIG_PPC32
  2069. .cpu_restore = __restore_cpu_e5500,
  2070. #endif
  2071. .machine_check = machine_check_e500mc,
  2072. .platform = "ppce6500",
  2073. },
  2074. #ifdef CONFIG_PPC32
  2075. { /* default match */
  2076. .pvr_mask = 0x00000000,
  2077. .pvr_value = 0x00000000,
  2078. .cpu_name = "(generic E500 PPC)",
  2079. .cpu_features = CPU_FTRS_E500,
  2080. .cpu_user_features = COMMON_USER_BOOKE |
  2081. PPC_FEATURE_HAS_SPE_COMP |
  2082. PPC_FEATURE_HAS_EFP_SINGLE_COMP,
  2083. .mmu_features = MMU_FTR_TYPE_FSL_E,
  2084. .icache_bsize = 32,
  2085. .dcache_bsize = 32,
  2086. .machine_check = machine_check_e500,
  2087. .platform = "powerpc",
  2088. }
  2089. #endif /* CONFIG_PPC32 */
  2090. #endif /* CONFIG_E500 */
  2091. #ifdef CONFIG_PPC_A2
  2092. { /* Standard A2 (>= DD2) + FPU core */
  2093. .pvr_mask = 0xffff0000,
  2094. .pvr_value = 0x00480000,
  2095. .cpu_name = "A2 (>= DD2)",
  2096. .cpu_features = CPU_FTRS_A2,
  2097. .cpu_user_features = COMMON_USER_PPC64,
  2098. .mmu_features = MMU_FTRS_A2,
  2099. .icache_bsize = 64,
  2100. .dcache_bsize = 64,
  2101. .num_pmcs = 0,
  2102. .cpu_setup = __setup_cpu_a2,
  2103. .cpu_restore = __restore_cpu_a2,
  2104. .machine_check = machine_check_generic,
  2105. .platform = "ppca2",
  2106. },
  2107. { /* This is a default entry to get going, to be replaced by
  2108. * a real one at some stage
  2109. */
  2110. #define CPU_FTRS_BASE_BOOK3E (CPU_FTR_USE_TB | \
  2111. CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_SMT | \
  2112. CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
  2113. .pvr_mask = 0x00000000,
  2114. .pvr_value = 0x00000000,
  2115. .cpu_name = "Book3E",
  2116. .cpu_features = CPU_FTRS_BASE_BOOK3E,
  2117. .cpu_user_features = COMMON_USER_PPC64,
  2118. .mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
  2119. MMU_FTR_USE_TLBIVAX_BCAST |
  2120. MMU_FTR_LOCK_BCAST_INVAL,
  2121. .icache_bsize = 64,
  2122. .dcache_bsize = 64,
  2123. .num_pmcs = 0,
  2124. .machine_check = machine_check_generic,
  2125. .platform = "power6",
  2126. },
  2127. #endif /* CONFIG_PPC_A2 */
  2128. };
  2129. static struct cpu_spec the_cpu_spec;
  2130. static struct cpu_spec * __init setup_cpu_spec(unsigned long offset,
  2131. struct cpu_spec *s)
  2132. {
  2133. struct cpu_spec *t = &the_cpu_spec;
  2134. struct cpu_spec old;
  2135. t = PTRRELOC(t);
  2136. old = *t;
  2137. /* Copy everything, then do fixups */
  2138. *t = *s;
  2139. /*
  2140. * If we are overriding a previous value derived from the real
  2141. * PVR with a new value obtained using a logical PVR value,
  2142. * don't modify the performance monitor fields.
  2143. */
  2144. if (old.num_pmcs && !s->num_pmcs) {
  2145. t->num_pmcs = old.num_pmcs;
  2146. t->pmc_type = old.pmc_type;
  2147. t->oprofile_type = old.oprofile_type;
  2148. t->oprofile_mmcra_sihv = old.oprofile_mmcra_sihv;
  2149. t->oprofile_mmcra_sipr = old.oprofile_mmcra_sipr;
  2150. t->oprofile_mmcra_clear = old.oprofile_mmcra_clear;
  2151. /*
  2152. * If we have passed through this logic once before and
  2153. * have pulled the default case because the real PVR was
  2154. * not found inside cpu_specs[], then we are possibly
  2155. * running in compatibility mode. In that case, let the
  2156. * oprofiler know which set of compatibility counters to
  2157. * pull from by making sure the oprofile_cpu_type string
  2158. * is set to that of compatibility mode. If the
  2159. * oprofile_cpu_type already has a value, then we are
  2160. * possibly overriding a real PVR with a logical one,
  2161. * and, in that case, keep the current value for
  2162. * oprofile_cpu_type.
  2163. */
  2164. if (old.oprofile_cpu_type != NULL) {
  2165. t->oprofile_cpu_type = old.oprofile_cpu_type;
  2166. t->oprofile_type = old.oprofile_type;
  2167. }
  2168. }
  2169. *PTRRELOC(&cur_cpu_spec) = &the_cpu_spec;
  2170. /*
  2171. * Set the base platform string once; assumes
  2172. * we're called with real pvr first.
  2173. */
  2174. if (*PTRRELOC(&powerpc_base_platform) == NULL)
  2175. *PTRRELOC(&powerpc_base_platform) = t->platform;
  2176. #if defined(CONFIG_PPC64) || defined(CONFIG_BOOKE)
  2177. /* ppc64 and booke expect identify_cpu to also call setup_cpu for
  2178. * that processor. I will consolidate that at a later time, for now,
  2179. * just use #ifdef. We also don't need to PTRRELOC the function
  2180. * pointer on ppc64 and booke as we are running at 0 in real mode
  2181. * on ppc64 and reloc_offset is always 0 on booke.
  2182. */
  2183. if (t->cpu_setup) {
  2184. t->cpu_setup(offset, t);
  2185. }
  2186. #endif /* CONFIG_PPC64 || CONFIG_BOOKE */
  2187. return t;
  2188. }
  2189. struct cpu_spec * __init identify_cpu(unsigned long offset, unsigned int pvr)
  2190. {
  2191. struct cpu_spec *s = cpu_specs;
  2192. int i;
  2193. s = PTRRELOC(s);
  2194. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++) {
  2195. if ((pvr & s->pvr_mask) == s->pvr_value)
  2196. return setup_cpu_spec(offset, s);
  2197. }
  2198. BUG();
  2199. return NULL;
  2200. }