mpc8560ads.dts 9.5 KB

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  1. /*
  2. * MPC8560 ADS Device Tree Source
  3. *
  4. * Copyright 2006, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. /include/ "fsl/e500v2_power_isa.dtsi"
  13. / {
  14. model = "MPC8560ADS";
  15. compatible = "MPC8560ADS", "MPC85xxADS";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. ethernet0 = &enet0;
  20. ethernet1 = &enet1;
  21. ethernet2 = &enet2;
  22. ethernet3 = &enet3;
  23. serial0 = &serial0;
  24. serial1 = &serial1;
  25. pci0 = &pci0;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. PowerPC,8560@0 {
  31. device_type = "cpu";
  32. reg = <0x0>;
  33. d-cache-line-size = <32>; // 32 bytes
  34. i-cache-line-size = <32>; // 32 bytes
  35. d-cache-size = <0x8000>; // L1, 32K
  36. i-cache-size = <0x8000>; // L1, 32K
  37. timebase-frequency = <82500000>;
  38. bus-frequency = <330000000>;
  39. clock-frequency = <825000000>;
  40. };
  41. };
  42. memory {
  43. device_type = "memory";
  44. reg = <0x0 0x10000000>;
  45. };
  46. soc8560@e0000000 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. device_type = "soc";
  50. compatible = "simple-bus";
  51. ranges = <0x0 0xe0000000 0x100000>;
  52. bus-frequency = <330000000>;
  53. ecm-law@0 {
  54. compatible = "fsl,ecm-law";
  55. reg = <0x0 0x1000>;
  56. fsl,num-laws = <8>;
  57. };
  58. ecm@1000 {
  59. compatible = "fsl,mpc8560-ecm", "fsl,ecm";
  60. reg = <0x1000 0x1000>;
  61. interrupts = <17 2>;
  62. interrupt-parent = <&mpic>;
  63. };
  64. memory-controller@2000 {
  65. compatible = "fsl,mpc8540-memory-controller";
  66. reg = <0x2000 0x1000>;
  67. interrupt-parent = <&mpic>;
  68. interrupts = <18 2>;
  69. };
  70. L2: l2-cache-controller@20000 {
  71. compatible = "fsl,mpc8540-l2-cache-controller";
  72. reg = <0x20000 0x1000>;
  73. cache-line-size = <32>; // 32 bytes
  74. cache-size = <0x40000>; // L2, 256K
  75. interrupt-parent = <&mpic>;
  76. interrupts = <16 2>;
  77. };
  78. dma@21300 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  82. reg = <0x21300 0x4>;
  83. ranges = <0x0 0x21100 0x200>;
  84. cell-index = <0>;
  85. dma-channel@0 {
  86. compatible = "fsl,mpc8560-dma-channel",
  87. "fsl,eloplus-dma-channel";
  88. reg = <0x0 0x80>;
  89. cell-index = <0>;
  90. interrupt-parent = <&mpic>;
  91. interrupts = <20 2>;
  92. };
  93. dma-channel@80 {
  94. compatible = "fsl,mpc8560-dma-channel",
  95. "fsl,eloplus-dma-channel";
  96. reg = <0x80 0x80>;
  97. cell-index = <1>;
  98. interrupt-parent = <&mpic>;
  99. interrupts = <21 2>;
  100. };
  101. dma-channel@100 {
  102. compatible = "fsl,mpc8560-dma-channel",
  103. "fsl,eloplus-dma-channel";
  104. reg = <0x100 0x80>;
  105. cell-index = <2>;
  106. interrupt-parent = <&mpic>;
  107. interrupts = <22 2>;
  108. };
  109. dma-channel@180 {
  110. compatible = "fsl,mpc8560-dma-channel",
  111. "fsl,eloplus-dma-channel";
  112. reg = <0x180 0x80>;
  113. cell-index = <3>;
  114. interrupt-parent = <&mpic>;
  115. interrupts = <23 2>;
  116. };
  117. };
  118. enet0: ethernet@24000 {
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. cell-index = <0>;
  122. device_type = "network";
  123. model = "TSEC";
  124. compatible = "gianfar";
  125. reg = <0x24000 0x1000>;
  126. ranges = <0x0 0x24000 0x1000>;
  127. local-mac-address = [ 00 00 00 00 00 00 ];
  128. interrupts = <29 2 30 2 34 2>;
  129. interrupt-parent = <&mpic>;
  130. tbi-handle = <&tbi0>;
  131. phy-handle = <&phy0>;
  132. mdio@520 {
  133. #address-cells = <1>;
  134. #size-cells = <0>;
  135. compatible = "fsl,gianfar-mdio";
  136. reg = <0x520 0x20>;
  137. phy0: ethernet-phy@0 {
  138. interrupt-parent = <&mpic>;
  139. interrupts = <5 1>;
  140. reg = <0x0>;
  141. device_type = "ethernet-phy";
  142. };
  143. phy1: ethernet-phy@1 {
  144. interrupt-parent = <&mpic>;
  145. interrupts = <5 1>;
  146. reg = <0x1>;
  147. device_type = "ethernet-phy";
  148. };
  149. phy2: ethernet-phy@2 {
  150. interrupt-parent = <&mpic>;
  151. interrupts = <7 1>;
  152. reg = <0x2>;
  153. device_type = "ethernet-phy";
  154. };
  155. phy3: ethernet-phy@3 {
  156. interrupt-parent = <&mpic>;
  157. interrupts = <7 1>;
  158. reg = <0x3>;
  159. device_type = "ethernet-phy";
  160. };
  161. tbi0: tbi-phy@11 {
  162. reg = <0x11>;
  163. device_type = "tbi-phy";
  164. };
  165. };
  166. };
  167. enet1: ethernet@25000 {
  168. #address-cells = <1>;
  169. #size-cells = <1>;
  170. cell-index = <1>;
  171. device_type = "network";
  172. model = "TSEC";
  173. compatible = "gianfar";
  174. reg = <0x25000 0x1000>;
  175. ranges = <0x0 0x25000 0x1000>;
  176. local-mac-address = [ 00 00 00 00 00 00 ];
  177. interrupts = <35 2 36 2 40 2>;
  178. interrupt-parent = <&mpic>;
  179. tbi-handle = <&tbi1>;
  180. phy-handle = <&phy1>;
  181. mdio@520 {
  182. #address-cells = <1>;
  183. #size-cells = <0>;
  184. compatible = "fsl,gianfar-tbi";
  185. reg = <0x520 0x20>;
  186. tbi1: tbi-phy@11 {
  187. reg = <0x11>;
  188. device_type = "tbi-phy";
  189. };
  190. };
  191. };
  192. mpic: pic@40000 {
  193. interrupt-controller;
  194. #address-cells = <0>;
  195. #interrupt-cells = <2>;
  196. reg = <0x40000 0x40000>;
  197. compatible = "chrp,open-pic";
  198. device_type = "open-pic";
  199. };
  200. cpm@919c0 {
  201. #address-cells = <1>;
  202. #size-cells = <1>;
  203. compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
  204. reg = <0x919c0 0x30>;
  205. ranges;
  206. muram@80000 {
  207. #address-cells = <1>;
  208. #size-cells = <1>;
  209. ranges = <0x0 0x80000 0x10000>;
  210. data@0 {
  211. compatible = "fsl,cpm-muram-data";
  212. reg = <0x0 0x4000 0x9000 0x2000>;
  213. };
  214. };
  215. brg@919f0 {
  216. compatible = "fsl,mpc8560-brg",
  217. "fsl,cpm2-brg",
  218. "fsl,cpm-brg";
  219. reg = <0x919f0 0x10 0x915f0 0x10>;
  220. clock-frequency = <165000000>;
  221. };
  222. cpmpic: pic@90c00 {
  223. interrupt-controller;
  224. #address-cells = <0>;
  225. #interrupt-cells = <2>;
  226. interrupts = <46 2>;
  227. interrupt-parent = <&mpic>;
  228. reg = <0x90c00 0x80>;
  229. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  230. };
  231. serial0: serial@91a00 {
  232. device_type = "serial";
  233. compatible = "fsl,mpc8560-scc-uart",
  234. "fsl,cpm2-scc-uart";
  235. reg = <0x91a00 0x20 0x88000 0x100>;
  236. fsl,cpm-brg = <1>;
  237. fsl,cpm-command = <0x800000>;
  238. current-speed = <115200>;
  239. interrupts = <40 8>;
  240. interrupt-parent = <&cpmpic>;
  241. };
  242. serial1: serial@91a20 {
  243. device_type = "serial";
  244. compatible = "fsl,mpc8560-scc-uart",
  245. "fsl,cpm2-scc-uart";
  246. reg = <0x91a20 0x20 0x88100 0x100>;
  247. fsl,cpm-brg = <2>;
  248. fsl,cpm-command = <0x4a00000>;
  249. current-speed = <115200>;
  250. interrupts = <41 8>;
  251. interrupt-parent = <&cpmpic>;
  252. };
  253. enet2: ethernet@91320 {
  254. device_type = "network";
  255. compatible = "fsl,mpc8560-fcc-enet",
  256. "fsl,cpm2-fcc-enet";
  257. reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
  258. local-mac-address = [ 00 00 00 00 00 00 ];
  259. fsl,cpm-command = <0x16200300>;
  260. interrupts = <33 8>;
  261. interrupt-parent = <&cpmpic>;
  262. phy-handle = <&phy2>;
  263. };
  264. enet3: ethernet@91340 {
  265. device_type = "network";
  266. compatible = "fsl,mpc8560-fcc-enet",
  267. "fsl,cpm2-fcc-enet";
  268. reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
  269. local-mac-address = [ 00 00 00 00 00 00 ];
  270. fsl,cpm-command = <0x1a400300>;
  271. interrupts = <34 8>;
  272. interrupt-parent = <&cpmpic>;
  273. phy-handle = <&phy3>;
  274. };
  275. };
  276. };
  277. pci0: pci@e0008000 {
  278. #interrupt-cells = <1>;
  279. #size-cells = <2>;
  280. #address-cells = <3>;
  281. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  282. device_type = "pci";
  283. reg = <0xe0008000 0x1000>;
  284. clock-frequency = <66666666>;
  285. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  286. interrupt-map = <
  287. /* IDSEL 0x2 */
  288. 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
  289. 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
  290. 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
  291. 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
  292. /* IDSEL 0x3 */
  293. 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
  294. 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
  295. 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
  296. 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
  297. /* IDSEL 0x4 */
  298. 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
  299. 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
  300. 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
  301. 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
  302. /* IDSEL 0x5 */
  303. 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
  304. 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
  305. 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
  306. 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
  307. /* IDSEL 12 */
  308. 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
  309. 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
  310. 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
  311. 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
  312. /* IDSEL 13 */
  313. 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
  314. 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
  315. 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
  316. 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
  317. /* IDSEL 14*/
  318. 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
  319. 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
  320. 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
  321. 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
  322. /* IDSEL 15 */
  323. 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
  324. 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
  325. 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
  326. 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
  327. /* IDSEL 18 */
  328. 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
  329. 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
  330. 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
  331. 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
  332. /* IDSEL 19 */
  333. 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
  334. 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
  335. 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
  336. 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
  337. /* IDSEL 20 */
  338. 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
  339. 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
  340. 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
  341. 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
  342. /* IDSEL 21 */
  343. 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
  344. 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
  345. 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
  346. 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
  347. interrupt-parent = <&mpic>;
  348. interrupts = <24 2>;
  349. bus-range = <0 0>;
  350. ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  351. 0x1000000 0x0 0x0 0xe2000000 0x0 0x1000000>;
  352. };
  353. };