mpc8544ds.dtsi 5.0 KB

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  1. /*
  2. * MPC8544DS Device Tree Source stub (no addresses or top-level ranges)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &board_lbc {
  35. nor@0,0 {
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. compatible = "cfi-flash";
  39. reg = <0x0 0x0 0x800000>;
  40. bank-width = <2>;
  41. device-width = <1>;
  42. partition@0 {
  43. reg = <0x0 0x10000>;
  44. label = "dtb-nor";
  45. };
  46. partition@20000 {
  47. reg = <0x20000 0x30000>;
  48. label = "diagnostic-nor";
  49. read-only;
  50. };
  51. partition@200000 {
  52. reg = <0x200000 0x200000>;
  53. label = "dink-nor";
  54. read-only;
  55. };
  56. partition@400000 {
  57. reg = <0x400000 0x380000>;
  58. label = "kernel-nor";
  59. };
  60. partition@780000 {
  61. reg = <0x780000 0x80000>;
  62. label = "u-boot-nor";
  63. read-only;
  64. };
  65. };
  66. };
  67. &board_soc {
  68. enet0: ethernet@24000 {
  69. phy-handle = <&phy0>;
  70. tbi-handle = <&tbi0>;
  71. phy-connection-type = "rgmii-id";
  72. };
  73. mdio@24520 {
  74. phy0: ethernet-phy@0 {
  75. interrupts = <10 1 0 0>;
  76. reg = <0x0>;
  77. device_type = "ethernet-phy";
  78. };
  79. phy1: ethernet-phy@1 {
  80. interrupts = <10 1 0 0>;
  81. reg = <0x1>;
  82. device_type = "ethernet-phy";
  83. };
  84. sgmii_phy0: sgmii-phy@0 {
  85. interrupts = <6 1 0 0>;
  86. reg = <0x1c>;
  87. };
  88. sgmii_phy1: sgmii-phy@1 {
  89. interrupts = <6 1 0 0>;
  90. reg = <0x1d>;
  91. };
  92. tbi0: tbi-phy@11 {
  93. reg = <0x11>;
  94. device_type = "tbi-phy";
  95. };
  96. };
  97. enet2: ethernet@26000 {
  98. phy-handle = <&phy1>;
  99. tbi-handle = <&tbi1>;
  100. phy-connection-type = "rgmii-id";
  101. };
  102. mdio@26520 {
  103. tbi1: tbi-phy@11 {
  104. reg = <0x11>;
  105. device_type = "tbi-phy";
  106. };
  107. };
  108. };
  109. &board_pci3 {
  110. pcie@0 {
  111. interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
  112. interrupt-map = <
  113. // IDSEL 0x1c USB
  114. 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
  115. 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
  116. 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
  117. 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
  118. // IDSEL 0x1d Audio
  119. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  120. // IDSEL 0x1e Legacy
  121. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  122. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  123. // IDSEL 0x1f IDE/SATA
  124. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  125. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  126. >;
  127. uli1575@0 {
  128. reg = <0x0 0x0 0x0 0x0 0x0>;
  129. #size-cells = <2>;
  130. #address-cells = <3>;
  131. ranges = <0x2000000 0x0 0xb0000000
  132. 0x2000000 0x0 0xb0000000
  133. 0x0 0x100000
  134. 0x1000000 0x0 0x0
  135. 0x1000000 0x0 0x0
  136. 0x0 0x100000>;
  137. isa@1e {
  138. device_type = "isa";
  139. #interrupt-cells = <2>;
  140. #size-cells = <1>;
  141. #address-cells = <2>;
  142. reg = <0xf000 0x0 0x0 0x0 0x0>;
  143. ranges = <0x1 0x0 0x1000000 0x0 0x0
  144. 0x1000>;
  145. interrupt-parent = <&i8259>;
  146. i8259: interrupt-controller@20 {
  147. reg = <0x1 0x20 0x2
  148. 0x1 0xa0 0x2
  149. 0x1 0x4d0 0x2>;
  150. interrupt-controller;
  151. device_type = "interrupt-controller";
  152. #address-cells = <0>;
  153. #interrupt-cells = <2>;
  154. compatible = "chrp,iic";
  155. interrupts = <9 2 0 0>;
  156. interrupt-parent = <&mpic>;
  157. };
  158. i8042@60 {
  159. #size-cells = <0>;
  160. #address-cells = <1>;
  161. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  162. interrupts = <1 3 12 3>;
  163. interrupt-parent =
  164. <&i8259>;
  165. keyboard@0 {
  166. reg = <0x0>;
  167. compatible = "pnpPNP,303";
  168. };
  169. mouse@1 {
  170. reg = <0x1>;
  171. compatible = "pnpPNP,f03";
  172. };
  173. };
  174. rtc@70 {
  175. compatible = "pnpPNP,b00";
  176. reg = <0x1 0x70 0x2>;
  177. };
  178. gpio@400 {
  179. reg = <0x1 0x400 0x80>;
  180. };
  181. };
  182. };
  183. };
  184. };