sead3-time.c 2.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  7. */
  8. #include <linux/init.h>
  9. #include <asm/setup.h>
  10. #include <asm/time.h>
  11. #include <asm/irq.h>
  12. #include <asm/mips-boards/generic.h>
  13. #include <asm/mips-boards/prom.h>
  14. unsigned long cpu_khz;
  15. static int mips_cpu_timer_irq;
  16. static int mips_cpu_perf_irq;
  17. static void mips_timer_dispatch(void)
  18. {
  19. do_IRQ(mips_cpu_timer_irq);
  20. }
  21. static void mips_perf_dispatch(void)
  22. {
  23. do_IRQ(mips_cpu_perf_irq);
  24. }
  25. static void __iomem *status_reg = (void __iomem *)0xbf000410;
  26. /*
  27. * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
  28. */
  29. static unsigned int __init estimate_cpu_frequency(void)
  30. {
  31. unsigned int prid = read_c0_prid() & 0xffff00;
  32. unsigned int tick = 0;
  33. unsigned int freq;
  34. unsigned int orig;
  35. unsigned long flags;
  36. local_irq_save(flags);
  37. orig = readl(status_reg) & 0x2; /* get original sample */
  38. /* wait for transition */
  39. while ((readl(status_reg) & 0x2) == orig)
  40. ;
  41. orig = orig ^ 0x2; /* flip the bit */
  42. write_c0_count(0);
  43. /* wait 1 second (the sampling clock transitions every 10ms) */
  44. while (tick < 100) {
  45. /* wait for transition */
  46. while ((readl(status_reg) & 0x2) == orig)
  47. ;
  48. orig = orig ^ 0x2; /* flip the bit */
  49. tick++;
  50. }
  51. freq = read_c0_count();
  52. local_irq_restore(flags);
  53. mips_hpt_frequency = freq;
  54. /* Adjust for processor */
  55. if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
  56. (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
  57. freq *= 2;
  58. freq += 5000; /* rounding */
  59. freq -= freq%10000;
  60. return freq ;
  61. }
  62. void read_persistent_clock(struct timespec *ts)
  63. {
  64. ts->tv_sec = 0;
  65. ts->tv_nsec = 0;
  66. }
  67. static void __init plat_perf_setup(void)
  68. {
  69. if (cp0_perfcount_irq >= 0) {
  70. if (cpu_has_vint)
  71. set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
  72. mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
  73. }
  74. }
  75. unsigned int __cpuinit get_c0_compare_int(void)
  76. {
  77. if (cpu_has_vint)
  78. set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
  79. mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  80. return mips_cpu_timer_irq;
  81. }
  82. void __init plat_time_init(void)
  83. {
  84. unsigned int est_freq;
  85. est_freq = estimate_cpu_frequency();
  86. pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
  87. (est_freq % 1000000) * 100 / 1000000);
  88. cpu_khz = est_freq / 1000;
  89. mips_scroll_message();
  90. plat_perf_setup();
  91. }