m528x.c 3.2 KB

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  1. /***************************************************************************/
  2. /*
  3. * linux/arch/m68knommu/platform/528x/config.c
  4. *
  5. * Sub-architcture dependent initialization code for the Freescale
  6. * 5280, 5281 and 5282 CPUs.
  7. *
  8. * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
  9. * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  10. */
  11. /***************************************************************************/
  12. #include <linux/kernel.h>
  13. #include <linux/param.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/io.h>
  17. #include <asm/machdep.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/mcfuart.h>
  21. #include <asm/mcfclk.h>
  22. /***************************************************************************/
  23. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  24. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  25. DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
  26. DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
  27. DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
  28. DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
  29. DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  30. DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  31. DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
  32. DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
  33. struct clk *mcf_clks[] = {
  34. &clk_pll,
  35. &clk_sys,
  36. &clk_mcfpit0,
  37. &clk_mcfpit1,
  38. &clk_mcfpit2,
  39. &clk_mcfpit3,
  40. &clk_mcfuart0,
  41. &clk_mcfuart1,
  42. &clk_mcfuart2,
  43. &clk_fec0,
  44. NULL
  45. };
  46. /***************************************************************************/
  47. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  48. static void __init m528x_qspi_init(void)
  49. {
  50. /* setup Port QS for QSPI with gpio CS control */
  51. __raw_writeb(0x07, MCFGPIO_PQSPAR);
  52. }
  53. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  54. /***************************************************************************/
  55. static void __init m528x_uarts_init(void)
  56. {
  57. u8 port;
  58. /* make sure PUAPAR is set for UART0 and UART1 */
  59. port = readb(MCFGPIO_PUAPAR);
  60. port |= 0x03 | (0x03 << 2);
  61. writeb(port, MCFGPIO_PUAPAR);
  62. }
  63. /***************************************************************************/
  64. static void __init m528x_fec_init(void)
  65. {
  66. u16 v16;
  67. /* Set multi-function pins to ethernet mode for fec0 */
  68. v16 = readw(MCFGPIO_PASPAR);
  69. writew(v16 | 0xf00, MCFGPIO_PASPAR);
  70. writeb(0xc0, MCFGPIO_PEHLPAR);
  71. }
  72. /***************************************************************************/
  73. #ifdef CONFIG_WILDFIRE
  74. void wildfire_halt(void)
  75. {
  76. writeb(0, 0x30000007);
  77. writeb(0x2, 0x30000007);
  78. }
  79. #endif
  80. #ifdef CONFIG_WILDFIREMOD
  81. void wildfiremod_halt(void)
  82. {
  83. printk(KERN_INFO "WildFireMod hibernating...\n");
  84. /* Set portE.5 to Digital IO */
  85. MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
  86. /* Make portE.5 an output */
  87. MCF5282_GPIO_DDRE |= (1 << 5);
  88. /* Now toggle portE.5 from low to high */
  89. MCF5282_GPIO_PORTE &= ~(1 << 5);
  90. MCF5282_GPIO_PORTE |= (1 << 5);
  91. printk(KERN_EMERG "Failed to hibernate. Halting!\n");
  92. }
  93. #endif
  94. void __init config_BSP(char *commandp, int size)
  95. {
  96. #ifdef CONFIG_WILDFIRE
  97. mach_halt = wildfire_halt;
  98. #endif
  99. #ifdef CONFIG_WILDFIREMOD
  100. mach_halt = wildfiremod_halt;
  101. #endif
  102. mach_sched_init = hw_timer_init;
  103. m528x_uarts_init();
  104. m528x_fec_init();
  105. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  106. m528x_qspi_init();
  107. #endif
  108. }
  109. /***************************************************************************/