m525x.c 2.3 KB

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  1. /***************************************************************************/
  2. /*
  3. * 525x.c
  4. *
  5. * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
  6. */
  7. /***************************************************************************/
  8. #include <linux/kernel.h>
  9. #include <linux/param.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/platform_device.h>
  13. #include <asm/machdep.h>
  14. #include <asm/coldfire.h>
  15. #include <asm/mcfsim.h>
  16. #include <asm/mcfclk.h>
  17. /***************************************************************************/
  18. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  19. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  20. DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
  21. DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
  22. DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
  23. DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
  24. struct clk *mcf_clks[] = {
  25. &clk_pll,
  26. &clk_sys,
  27. &clk_mcftmr0,
  28. &clk_mcftmr1,
  29. &clk_mcfuart0,
  30. &clk_mcfuart1,
  31. NULL
  32. };
  33. /***************************************************************************/
  34. static void __init m525x_qspi_init(void)
  35. {
  36. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  37. /* set the GPIO function for the qspi cs gpios */
  38. /* FIXME: replace with pinmux/pinctl support */
  39. u32 f = readl(MCFSIM2_GPIOFUNC);
  40. f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
  41. writel(f, MCFSIM2_GPIOFUNC);
  42. /* QSPI irq setup */
  43. writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
  44. MCFSIM_QSPIICR);
  45. mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
  46. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  47. }
  48. static void __init m525x_i2c_init(void)
  49. {
  50. #if IS_ENABLED(CONFIG_I2C_COLDFIRE)
  51. u32 r;
  52. /* first I2C controller uses regular irq setup */
  53. writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
  54. MCFSIM_I2CICR);
  55. mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
  56. /* second I2C controller is completely different */
  57. r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  58. r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
  59. r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
  60. writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  61. #endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
  62. }
  63. /***************************************************************************/
  64. void __init config_BSP(char *commandp, int size)
  65. {
  66. mach_sched_init = hw_timer_init;
  67. m525x_qspi_init();
  68. m525x_i2c_init();
  69. }
  70. /***************************************************************************/