smpboot.c 20 KB

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  1. /*
  2. * SMP boot-related support
  3. *
  4. * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
  5. * David Mosberger-Tang <davidm@hpl.hp.com>
  6. * Copyright (C) 2001, 2004-2005 Intel Corp
  7. * Rohit Seth <rohit.seth@intel.com>
  8. * Suresh Siddha <suresh.b.siddha@intel.com>
  9. * Gordon Jin <gordon.jin@intel.com>
  10. * Ashok Raj <ashok.raj@intel.com>
  11. *
  12. * 01/05/16 Rohit Seth <rohit.seth@intel.com> Moved SMP booting functions from smp.c to here.
  13. * 01/04/27 David Mosberger <davidm@hpl.hp.com> Added ITC synching code.
  14. * 02/07/31 David Mosberger <davidm@hpl.hp.com> Switch over to hotplug-CPU boot-sequence.
  15. * smp_boot_cpus()/smp_commence() is replaced by
  16. * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
  17. * 04/06/21 Ashok Raj <ashok.raj@intel.com> Added CPU Hotplug Support
  18. * 04/12/26 Jin Gordon <gordon.jin@intel.com>
  19. * 04/12/26 Rohit Seth <rohit.seth@intel.com>
  20. * Add multi-threading and multi-core detection
  21. * 05/01/30 Suresh Siddha <suresh.b.siddha@intel.com>
  22. * Setup cpu_sibling_map and cpu_core_map
  23. */
  24. #include <linux/module.h>
  25. #include <linux/acpi.h>
  26. #include <linux/bootmem.h>
  27. #include <linux/cpu.h>
  28. #include <linux/delay.h>
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/irq.h>
  32. #include <linux/kernel.h>
  33. #include <linux/kernel_stat.h>
  34. #include <linux/mm.h>
  35. #include <linux/notifier.h>
  36. #include <linux/smp.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/efi.h>
  39. #include <linux/percpu.h>
  40. #include <linux/bitops.h>
  41. #include <linux/atomic.h>
  42. #include <asm/cache.h>
  43. #include <asm/current.h>
  44. #include <asm/delay.h>
  45. #include <asm/io.h>
  46. #include <asm/irq.h>
  47. #include <asm/machvec.h>
  48. #include <asm/mca.h>
  49. #include <asm/page.h>
  50. #include <asm/paravirt.h>
  51. #include <asm/pgalloc.h>
  52. #include <asm/pgtable.h>
  53. #include <asm/processor.h>
  54. #include <asm/ptrace.h>
  55. #include <asm/sal.h>
  56. #include <asm/tlbflush.h>
  57. #include <asm/unistd.h>
  58. #include <asm/sn/arch.h>
  59. #define SMP_DEBUG 0
  60. #if SMP_DEBUG
  61. #define Dprintk(x...) printk(x)
  62. #else
  63. #define Dprintk(x...)
  64. #endif
  65. #ifdef CONFIG_HOTPLUG_CPU
  66. #ifdef CONFIG_PERMIT_BSP_REMOVE
  67. #define bsp_remove_ok 1
  68. #else
  69. #define bsp_remove_ok 0
  70. #endif
  71. /*
  72. * Global array allocated for NR_CPUS at boot time
  73. */
  74. struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
  75. /*
  76. * start_ap in head.S uses this to store current booting cpu
  77. * info.
  78. */
  79. struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
  80. #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
  81. #else
  82. #define set_brendez_area(x)
  83. #endif
  84. /*
  85. * ITC synchronization related stuff:
  86. */
  87. #define MASTER (0)
  88. #define SLAVE (SMP_CACHE_BYTES/8)
  89. #define NUM_ROUNDS 64 /* magic value */
  90. #define NUM_ITERS 5 /* likewise */
  91. static DEFINE_SPINLOCK(itc_sync_lock);
  92. static volatile unsigned long go[SLAVE + 1];
  93. #define DEBUG_ITC_SYNC 0
  94. extern void start_ap (void);
  95. extern unsigned long ia64_iobase;
  96. struct task_struct *task_for_booting_cpu;
  97. /*
  98. * State for each CPU
  99. */
  100. DEFINE_PER_CPU(int, cpu_state);
  101. cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
  102. EXPORT_SYMBOL(cpu_core_map);
  103. DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
  104. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  105. int smp_num_siblings = 1;
  106. /* which logical CPU number maps to which CPU (physical APIC ID) */
  107. volatile int ia64_cpu_to_sapicid[NR_CPUS];
  108. EXPORT_SYMBOL(ia64_cpu_to_sapicid);
  109. static volatile cpumask_t cpu_callin_map;
  110. struct smp_boot_data smp_boot_data __initdata;
  111. unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
  112. char __initdata no_int_routing;
  113. unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
  114. #ifdef CONFIG_FORCE_CPEI_RETARGET
  115. #define CPEI_OVERRIDE_DEFAULT (1)
  116. #else
  117. #define CPEI_OVERRIDE_DEFAULT (0)
  118. #endif
  119. unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
  120. static int __init
  121. cmdl_force_cpei(char *str)
  122. {
  123. int value=0;
  124. get_option (&str, &value);
  125. force_cpei_retarget = value;
  126. return 1;
  127. }
  128. __setup("force_cpei=", cmdl_force_cpei);
  129. static int __init
  130. nointroute (char *str)
  131. {
  132. no_int_routing = 1;
  133. printk ("no_int_routing on\n");
  134. return 1;
  135. }
  136. __setup("nointroute", nointroute);
  137. static void fix_b0_for_bsp(void)
  138. {
  139. #ifdef CONFIG_HOTPLUG_CPU
  140. int cpuid;
  141. static int fix_bsp_b0 = 1;
  142. cpuid = smp_processor_id();
  143. /*
  144. * Cache the b0 value on the first AP that comes up
  145. */
  146. if (!(fix_bsp_b0 && cpuid))
  147. return;
  148. sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
  149. printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
  150. fix_bsp_b0 = 0;
  151. #endif
  152. }
  153. void
  154. sync_master (void *arg)
  155. {
  156. unsigned long flags, i;
  157. go[MASTER] = 0;
  158. local_irq_save(flags);
  159. {
  160. for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
  161. while (!go[MASTER])
  162. cpu_relax();
  163. go[MASTER] = 0;
  164. go[SLAVE] = ia64_get_itc();
  165. }
  166. }
  167. local_irq_restore(flags);
  168. }
  169. /*
  170. * Return the number of cycles by which our itc differs from the itc on the master
  171. * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
  172. * negative that it is behind.
  173. */
  174. static inline long
  175. get_delta (long *rt, long *master)
  176. {
  177. unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
  178. unsigned long tcenter, t0, t1, tm;
  179. long i;
  180. for (i = 0; i < NUM_ITERS; ++i) {
  181. t0 = ia64_get_itc();
  182. go[MASTER] = 1;
  183. while (!(tm = go[SLAVE]))
  184. cpu_relax();
  185. go[SLAVE] = 0;
  186. t1 = ia64_get_itc();
  187. if (t1 - t0 < best_t1 - best_t0)
  188. best_t0 = t0, best_t1 = t1, best_tm = tm;
  189. }
  190. *rt = best_t1 - best_t0;
  191. *master = best_tm - best_t0;
  192. /* average best_t0 and best_t1 without overflow: */
  193. tcenter = (best_t0/2 + best_t1/2);
  194. if (best_t0 % 2 + best_t1 % 2 == 2)
  195. ++tcenter;
  196. return tcenter - best_tm;
  197. }
  198. /*
  199. * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
  200. * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
  201. * unaccounted-for errors (such as getting a machine check in the middle of a calibration
  202. * step). The basic idea is for the slave to ask the master what itc value it has and to
  203. * read its own itc before and after the master responds. Each iteration gives us three
  204. * timestamps:
  205. *
  206. * slave master
  207. *
  208. * t0 ---\
  209. * ---\
  210. * --->
  211. * tm
  212. * /---
  213. * /---
  214. * t1 <---
  215. *
  216. *
  217. * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
  218. * and t1. If we achieve this, the clocks are synchronized provided the interconnect
  219. * between the slave and the master is symmetric. Even if the interconnect were
  220. * asymmetric, we would still know that the synchronization error is smaller than the
  221. * roundtrip latency (t0 - t1).
  222. *
  223. * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
  224. * within one or two cycles. However, we can only *guarantee* that the synchronization is
  225. * accurate to within a round-trip time, which is typically in the range of several
  226. * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
  227. * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
  228. * than half a micro second or so.
  229. */
  230. void
  231. ia64_sync_itc (unsigned int master)
  232. {
  233. long i, delta, adj, adjust_latency = 0, done = 0;
  234. unsigned long flags, rt, master_time_stamp, bound;
  235. #if DEBUG_ITC_SYNC
  236. struct {
  237. long rt; /* roundtrip time */
  238. long master; /* master's timestamp */
  239. long diff; /* difference between midpoint and master's timestamp */
  240. long lat; /* estimate of itc adjustment latency */
  241. } t[NUM_ROUNDS];
  242. #endif
  243. /*
  244. * Make sure local timer ticks are disabled while we sync. If
  245. * they were enabled, we'd have to worry about nasty issues
  246. * like setting the ITC ahead of (or a long time before) the
  247. * next scheduled tick.
  248. */
  249. BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
  250. go[MASTER] = 1;
  251. if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
  252. printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
  253. return;
  254. }
  255. while (go[MASTER])
  256. cpu_relax(); /* wait for master to be ready */
  257. spin_lock_irqsave(&itc_sync_lock, flags);
  258. {
  259. for (i = 0; i < NUM_ROUNDS; ++i) {
  260. delta = get_delta(&rt, &master_time_stamp);
  261. if (delta == 0) {
  262. done = 1; /* let's lock on to this... */
  263. bound = rt;
  264. }
  265. if (!done) {
  266. if (i > 0) {
  267. adjust_latency += -delta;
  268. adj = -delta + adjust_latency/4;
  269. } else
  270. adj = -delta;
  271. ia64_set_itc(ia64_get_itc() + adj);
  272. }
  273. #if DEBUG_ITC_SYNC
  274. t[i].rt = rt;
  275. t[i].master = master_time_stamp;
  276. t[i].diff = delta;
  277. t[i].lat = adjust_latency/4;
  278. #endif
  279. }
  280. }
  281. spin_unlock_irqrestore(&itc_sync_lock, flags);
  282. #if DEBUG_ITC_SYNC
  283. for (i = 0; i < NUM_ROUNDS; ++i)
  284. printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
  285. t[i].rt, t[i].master, t[i].diff, t[i].lat);
  286. #endif
  287. printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
  288. "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
  289. }
  290. /*
  291. * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
  292. */
  293. static inline void smp_setup_percpu_timer(void)
  294. {
  295. }
  296. static void __cpuinit
  297. smp_callin (void)
  298. {
  299. int cpuid, phys_id, itc_master;
  300. struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
  301. extern void ia64_init_itm(void);
  302. extern volatile int time_keeper_id;
  303. #ifdef CONFIG_PERFMON
  304. extern void pfm_init_percpu(void);
  305. #endif
  306. cpuid = smp_processor_id();
  307. phys_id = hard_smp_processor_id();
  308. itc_master = time_keeper_id;
  309. if (cpu_online(cpuid)) {
  310. printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
  311. phys_id, cpuid);
  312. BUG();
  313. }
  314. fix_b0_for_bsp();
  315. /*
  316. * numa_node_id() works after this.
  317. */
  318. set_numa_node(cpu_to_node_map[cpuid]);
  319. set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
  320. spin_lock(&vector_lock);
  321. /* Setup the per cpu irq handling data structures */
  322. __setup_vector_irq(cpuid);
  323. notify_cpu_starting(cpuid);
  324. set_cpu_online(cpuid, true);
  325. per_cpu(cpu_state, cpuid) = CPU_ONLINE;
  326. spin_unlock(&vector_lock);
  327. smp_setup_percpu_timer();
  328. ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
  329. #ifdef CONFIG_PERFMON
  330. pfm_init_percpu();
  331. #endif
  332. local_irq_enable();
  333. if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  334. /*
  335. * Synchronize the ITC with the BP. Need to do this after irqs are
  336. * enabled because ia64_sync_itc() calls smp_call_function_single(), which
  337. * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
  338. * local_bh_enable(), which bugs out if irqs are not enabled...
  339. */
  340. Dprintk("Going to syncup ITC with ITC Master.\n");
  341. ia64_sync_itc(itc_master);
  342. }
  343. /*
  344. * Get our bogomips.
  345. */
  346. ia64_init_itm();
  347. /*
  348. * Delay calibration can be skipped if new processor is identical to the
  349. * previous processor.
  350. */
  351. last_cpuinfo = cpu_data(cpuid - 1);
  352. this_cpuinfo = local_cpu_data;
  353. if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
  354. last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
  355. last_cpuinfo->features != this_cpuinfo->features ||
  356. last_cpuinfo->revision != this_cpuinfo->revision ||
  357. last_cpuinfo->family != this_cpuinfo->family ||
  358. last_cpuinfo->archrev != this_cpuinfo->archrev ||
  359. last_cpuinfo->model != this_cpuinfo->model)
  360. calibrate_delay();
  361. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  362. /*
  363. * Allow the master to continue.
  364. */
  365. cpu_set(cpuid, cpu_callin_map);
  366. Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
  367. }
  368. /*
  369. * Activate a secondary processor. head.S calls this.
  370. */
  371. int __cpuinit
  372. start_secondary (void *unused)
  373. {
  374. /* Early console may use I/O ports */
  375. ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
  376. #ifndef CONFIG_PRINTK_TIME
  377. Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
  378. #endif
  379. efi_map_pal_code();
  380. cpu_init();
  381. preempt_disable();
  382. smp_callin();
  383. cpu_idle();
  384. return 0;
  385. }
  386. static int __cpuinit
  387. do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
  388. {
  389. int timeout;
  390. task_for_booting_cpu = idle;
  391. Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
  392. set_brendez_area(cpu);
  393. platform_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
  394. /*
  395. * Wait 10s total for the AP to start
  396. */
  397. Dprintk("Waiting on callin_map ...");
  398. for (timeout = 0; timeout < 100000; timeout++) {
  399. if (cpu_isset(cpu, cpu_callin_map))
  400. break; /* It has booted */
  401. udelay(100);
  402. }
  403. Dprintk("\n");
  404. if (!cpu_isset(cpu, cpu_callin_map)) {
  405. printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
  406. ia64_cpu_to_sapicid[cpu] = -1;
  407. set_cpu_online(cpu, false); /* was set in smp_callin() */
  408. return -EINVAL;
  409. }
  410. return 0;
  411. }
  412. static int __init
  413. decay (char *str)
  414. {
  415. int ticks;
  416. get_option (&str, &ticks);
  417. return 1;
  418. }
  419. __setup("decay=", decay);
  420. /*
  421. * Initialize the logical CPU number to SAPICID mapping
  422. */
  423. void __init
  424. smp_build_cpu_map (void)
  425. {
  426. int sapicid, cpu, i;
  427. int boot_cpu_id = hard_smp_processor_id();
  428. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  429. ia64_cpu_to_sapicid[cpu] = -1;
  430. }
  431. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  432. init_cpu_present(cpumask_of(0));
  433. set_cpu_possible(0, true);
  434. for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
  435. sapicid = smp_boot_data.cpu_phys_id[i];
  436. if (sapicid == boot_cpu_id)
  437. continue;
  438. set_cpu_present(cpu, true);
  439. set_cpu_possible(cpu, true);
  440. ia64_cpu_to_sapicid[cpu] = sapicid;
  441. cpu++;
  442. }
  443. }
  444. /*
  445. * Cycle through the APs sending Wakeup IPIs to boot each.
  446. */
  447. void __init
  448. smp_prepare_cpus (unsigned int max_cpus)
  449. {
  450. int boot_cpu_id = hard_smp_processor_id();
  451. /*
  452. * Initialize the per-CPU profiling counter/multiplier
  453. */
  454. smp_setup_percpu_timer();
  455. cpu_set(0, cpu_callin_map);
  456. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  457. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  458. printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
  459. current_thread_info()->cpu = 0;
  460. /*
  461. * If SMP should be disabled, then really disable it!
  462. */
  463. if (!max_cpus) {
  464. printk(KERN_INFO "SMP mode deactivated.\n");
  465. init_cpu_online(cpumask_of(0));
  466. init_cpu_present(cpumask_of(0));
  467. init_cpu_possible(cpumask_of(0));
  468. return;
  469. }
  470. }
  471. void smp_prepare_boot_cpu(void)
  472. {
  473. set_cpu_online(smp_processor_id(), true);
  474. cpu_set(smp_processor_id(), cpu_callin_map);
  475. set_numa_node(cpu_to_node_map[smp_processor_id()]);
  476. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  477. paravirt_post_smp_prepare_boot_cpu();
  478. }
  479. #ifdef CONFIG_HOTPLUG_CPU
  480. static inline void
  481. clear_cpu_sibling_map(int cpu)
  482. {
  483. int i;
  484. for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
  485. cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
  486. for_each_cpu_mask(i, cpu_core_map[cpu])
  487. cpu_clear(cpu, cpu_core_map[i]);
  488. per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
  489. }
  490. static void
  491. remove_siblinginfo(int cpu)
  492. {
  493. int last = 0;
  494. if (cpu_data(cpu)->threads_per_core == 1 &&
  495. cpu_data(cpu)->cores_per_socket == 1) {
  496. cpu_clear(cpu, cpu_core_map[cpu]);
  497. cpu_clear(cpu, per_cpu(cpu_sibling_map, cpu));
  498. return;
  499. }
  500. last = (cpus_weight(cpu_core_map[cpu]) == 1 ? 1 : 0);
  501. /* remove it from all sibling map's */
  502. clear_cpu_sibling_map(cpu);
  503. }
  504. extern void fixup_irqs(void);
  505. int migrate_platform_irqs(unsigned int cpu)
  506. {
  507. int new_cpei_cpu;
  508. struct irq_data *data = NULL;
  509. const struct cpumask *mask;
  510. int retval = 0;
  511. /*
  512. * dont permit CPEI target to removed.
  513. */
  514. if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
  515. printk ("CPU (%d) is CPEI Target\n", cpu);
  516. if (can_cpei_retarget()) {
  517. /*
  518. * Now re-target the CPEI to a different processor
  519. */
  520. new_cpei_cpu = cpumask_any(cpu_online_mask);
  521. mask = cpumask_of(new_cpei_cpu);
  522. set_cpei_target_cpu(new_cpei_cpu);
  523. data = irq_get_irq_data(ia64_cpe_irq);
  524. /*
  525. * Switch for now, immediately, we need to do fake intr
  526. * as other interrupts, but need to study CPEI behaviour with
  527. * polling before making changes.
  528. */
  529. if (data && data->chip) {
  530. data->chip->irq_disable(data);
  531. data->chip->irq_set_affinity(data, mask, false);
  532. data->chip->irq_enable(data);
  533. printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
  534. }
  535. }
  536. if (!data) {
  537. printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
  538. retval = -EBUSY;
  539. }
  540. }
  541. return retval;
  542. }
  543. /* must be called with cpucontrol mutex held */
  544. int __cpu_disable(void)
  545. {
  546. int cpu = smp_processor_id();
  547. /*
  548. * dont permit boot processor for now
  549. */
  550. if (cpu == 0 && !bsp_remove_ok) {
  551. printk ("Your platform does not support removal of BSP\n");
  552. return (-EBUSY);
  553. }
  554. if (ia64_platform_is("sn2")) {
  555. if (!sn_cpu_disable_allowed(cpu))
  556. return -EBUSY;
  557. }
  558. set_cpu_online(cpu, false);
  559. if (migrate_platform_irqs(cpu)) {
  560. set_cpu_online(cpu, true);
  561. return -EBUSY;
  562. }
  563. remove_siblinginfo(cpu);
  564. fixup_irqs();
  565. local_flush_tlb_all();
  566. cpu_clear(cpu, cpu_callin_map);
  567. return 0;
  568. }
  569. void __cpu_die(unsigned int cpu)
  570. {
  571. unsigned int i;
  572. for (i = 0; i < 100; i++) {
  573. /* They ack this in play_dead by setting CPU_DEAD */
  574. if (per_cpu(cpu_state, cpu) == CPU_DEAD)
  575. {
  576. printk ("CPU %d is now offline\n", cpu);
  577. return;
  578. }
  579. msleep(100);
  580. }
  581. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  582. }
  583. #endif /* CONFIG_HOTPLUG_CPU */
  584. void
  585. smp_cpus_done (unsigned int dummy)
  586. {
  587. int cpu;
  588. unsigned long bogosum = 0;
  589. /*
  590. * Allow the user to impress friends.
  591. */
  592. for_each_online_cpu(cpu) {
  593. bogosum += cpu_data(cpu)->loops_per_jiffy;
  594. }
  595. printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  596. (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
  597. }
  598. static inline void set_cpu_sibling_map(int cpu)
  599. {
  600. int i;
  601. for_each_online_cpu(i) {
  602. if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
  603. cpu_set(i, cpu_core_map[cpu]);
  604. cpu_set(cpu, cpu_core_map[i]);
  605. if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
  606. cpu_set(i, per_cpu(cpu_sibling_map, cpu));
  607. cpu_set(cpu, per_cpu(cpu_sibling_map, i));
  608. }
  609. }
  610. }
  611. }
  612. int __cpuinit
  613. __cpu_up(unsigned int cpu, struct task_struct *tidle)
  614. {
  615. int ret;
  616. int sapicid;
  617. sapicid = ia64_cpu_to_sapicid[cpu];
  618. if (sapicid == -1)
  619. return -EINVAL;
  620. /*
  621. * Already booted cpu? not valid anymore since we dont
  622. * do idle loop tightspin anymore.
  623. */
  624. if (cpu_isset(cpu, cpu_callin_map))
  625. return -EINVAL;
  626. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  627. /* Processor goes to start_secondary(), sets online flag */
  628. ret = do_boot_cpu(sapicid, cpu, tidle);
  629. if (ret < 0)
  630. return ret;
  631. if (cpu_data(cpu)->threads_per_core == 1 &&
  632. cpu_data(cpu)->cores_per_socket == 1) {
  633. cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
  634. cpu_set(cpu, cpu_core_map[cpu]);
  635. return 0;
  636. }
  637. set_cpu_sibling_map(cpu);
  638. return 0;
  639. }
  640. /*
  641. * Assume that CPUs have been discovered by some platform-dependent interface. For
  642. * SoftSDV/Lion, that would be ACPI.
  643. *
  644. * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
  645. */
  646. void __init
  647. init_smp_config(void)
  648. {
  649. struct fptr {
  650. unsigned long fp;
  651. unsigned long gp;
  652. } *ap_startup;
  653. long sal_ret;
  654. /* Tell SAL where to drop the APs. */
  655. ap_startup = (struct fptr *) start_ap;
  656. sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
  657. ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
  658. if (sal_ret < 0)
  659. printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
  660. ia64_sal_strerror(sal_ret));
  661. }
  662. /*
  663. * identify_siblings(cpu) gets called from identify_cpu. This populates the
  664. * information related to logical execution units in per_cpu_data structure.
  665. */
  666. void identify_siblings(struct cpuinfo_ia64 *c)
  667. {
  668. long status;
  669. u16 pltid;
  670. pal_logical_to_physical_t info;
  671. status = ia64_pal_logical_to_phys(-1, &info);
  672. if (status != PAL_STATUS_SUCCESS) {
  673. if (status != PAL_STATUS_UNIMPLEMENTED) {
  674. printk(KERN_ERR
  675. "ia64_pal_logical_to_phys failed with %ld\n",
  676. status);
  677. return;
  678. }
  679. info.overview_ppid = 0;
  680. info.overview_cpp = 1;
  681. info.overview_tpc = 1;
  682. }
  683. status = ia64_sal_physical_id_info(&pltid);
  684. if (status != PAL_STATUS_SUCCESS) {
  685. if (status != PAL_STATUS_UNIMPLEMENTED)
  686. printk(KERN_ERR
  687. "ia64_sal_pltid failed with %ld\n",
  688. status);
  689. return;
  690. }
  691. c->socket_id = (pltid << 8) | info.overview_ppid;
  692. if (info.overview_cpp == 1 && info.overview_tpc == 1)
  693. return;
  694. c->cores_per_socket = info.overview_cpp;
  695. c->threads_per_core = info.overview_tpc;
  696. c->num_log = info.overview_num_log;
  697. c->core_id = info.log1_cid;
  698. c->thread_id = info.log1_tid;
  699. }
  700. /*
  701. * returns non zero, if multi-threading is enabled
  702. * on at least one physical package. Due to hotplug cpu
  703. * and (maxcpus=), all threads may not necessarily be enabled
  704. * even though the processor supports multi-threading.
  705. */
  706. int is_multithreading_enabled(void)
  707. {
  708. int i, j;
  709. for_each_present_cpu(i) {
  710. for_each_present_cpu(j) {
  711. if (j == i)
  712. continue;
  713. if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
  714. if (cpu_data(j)->core_id == cpu_data(i)->core_id)
  715. return 1;
  716. }
  717. }
  718. }
  719. return 0;
  720. }
  721. EXPORT_SYMBOL_GPL(is_multithreading_enabled);