proc.S 4.2 KB

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  1. /*
  2. * Based on arch/arm/mm/proc.S
  3. *
  4. * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5. * Copyright (C) 2012 ARM Ltd.
  6. * Author: Catalin Marinas <catalin.marinas@arm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include <linux/init.h>
  21. #include <linux/linkage.h>
  22. #include <asm/assembler.h>
  23. #include <asm/asm-offsets.h>
  24. #include <asm/hwcap.h>
  25. #include <asm/pgtable-hwdef.h>
  26. #include <asm/pgtable.h>
  27. #include "proc-macros.S"
  28. #ifndef CONFIG_SMP
  29. /* PTWs cacheable, inner/outer WBWA not shareable */
  30. #define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
  31. #else
  32. /* PTWs cacheable, inner/outer WBWA shareable */
  33. #define TCR_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA | TCR_SHARED
  34. #endif
  35. #define MAIR(attr, mt) ((attr) << ((mt) * 8))
  36. /*
  37. * cpu_cache_off()
  38. *
  39. * Turn the CPU D-cache off.
  40. */
  41. ENTRY(cpu_cache_off)
  42. mrs x0, sctlr_el1
  43. bic x0, x0, #1 << 2 // clear SCTLR.C
  44. msr sctlr_el1, x0
  45. isb
  46. ret
  47. ENDPROC(cpu_cache_off)
  48. /*
  49. * cpu_reset(loc)
  50. *
  51. * Perform a soft reset of the system. Put the CPU into the same state
  52. * as it would be if it had been reset, and branch to what would be the
  53. * reset vector. It must be executed with the flat identity mapping.
  54. *
  55. * - loc - location to jump to for soft reset
  56. */
  57. .align 5
  58. ENTRY(cpu_reset)
  59. mrs x1, sctlr_el1
  60. bic x1, x1, #1
  61. msr sctlr_el1, x1 // disable the MMU
  62. isb
  63. ret x0
  64. ENDPROC(cpu_reset)
  65. /*
  66. * cpu_do_idle()
  67. *
  68. * Idle the processor (wait for interrupt).
  69. */
  70. ENTRY(cpu_do_idle)
  71. dsb sy // WFI may enter a low-power mode
  72. wfi
  73. ret
  74. ENDPROC(cpu_do_idle)
  75. /*
  76. * cpu_switch_mm(pgd_phys, tsk)
  77. *
  78. * Set the translation table base pointer to be pgd_phys.
  79. *
  80. * - pgd_phys - physical address of new TTB
  81. */
  82. ENTRY(cpu_do_switch_mm)
  83. mmid w1, x1 // get mm->context.id
  84. bfi x0, x1, #48, #16 // set the ASID
  85. msr ttbr0_el1, x0 // set TTBR0
  86. isb
  87. ret
  88. ENDPROC(cpu_do_switch_mm)
  89. cpu_name:
  90. .ascii "AArch64 Processor"
  91. .align
  92. .section ".text.init", #alloc, #execinstr
  93. /*
  94. * __cpu_setup
  95. *
  96. * Initialise the processor for turning the MMU on. Return in x0 the
  97. * value of the SCTLR_EL1 register.
  98. */
  99. ENTRY(__cpu_setup)
  100. /*
  101. * Preserve the link register across the function call.
  102. */
  103. mov x28, lr
  104. bl __flush_dcache_all
  105. mov lr, x28
  106. ic iallu // I+BTB cache invalidate
  107. dsb sy
  108. mov x0, #3 << 20
  109. msr cpacr_el1, x0 // Enable FP/ASIMD
  110. mov x0, #1
  111. msr oslar_el1, x0 // Set the debug OS lock
  112. tlbi vmalle1is // invalidate I + D TLBs
  113. /*
  114. * Memory region attributes for LPAE:
  115. *
  116. * n = AttrIndx[2:0]
  117. * n MAIR
  118. * DEVICE_nGnRnE 000 00000000
  119. * DEVICE_nGnRE 001 00000100
  120. * DEVICE_GRE 010 00001100
  121. * NORMAL_NC 011 01000100
  122. * NORMAL 100 11111111
  123. */
  124. ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
  125. MAIR(0x04, MT_DEVICE_nGnRE) | \
  126. MAIR(0x0c, MT_DEVICE_GRE) | \
  127. MAIR(0x44, MT_NORMAL_NC) | \
  128. MAIR(0xff, MT_NORMAL)
  129. msr mair_el1, x5
  130. /*
  131. * Prepare SCTLR
  132. */
  133. adr x5, crval
  134. ldp w5, w6, [x5]
  135. mrs x0, sctlr_el1
  136. bic x0, x0, x5 // clear bits
  137. orr x0, x0, x6 // set bits
  138. /*
  139. * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
  140. * both user and kernel.
  141. */
  142. ldr x10, =TCR_TxSZ(VA_BITS) | TCR_FLAGS | TCR_IPS_40BIT | \
  143. TCR_ASID16 | (1 << 31)
  144. #ifdef CONFIG_ARM64_64K_PAGES
  145. orr x10, x10, TCR_TG0_64K
  146. orr x10, x10, TCR_TG1_64K
  147. #endif
  148. msr tcr_el1, x10
  149. ret // return to head.S
  150. ENDPROC(__cpu_setup)
  151. /*
  152. * n n T
  153. * U E WT T UD US IHBS
  154. * CE0 XWHW CZ ME TEEA S
  155. * .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
  156. * 0011 0... 1101 ..0. ..0. 10.. .... .... < hardware reserved
  157. * .... .100 .... 01.1 11.1 ..01 0001 1101 < software settings
  158. */
  159. .type crval, #object
  160. crval:
  161. .word 0x030802e2 // clear
  162. .word 0x0405d11d // set