devices-db8500.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  5. * License terms: GNU General Public License (GPL) version 2
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/io.h>
  11. #include <linux/gpio.h>
  12. #include <linux/amba/bus.h>
  13. #include <linux/amba/pl022.h>
  14. #include <linux/platform_data/dma-ste-dma40.h>
  15. #include <linux/mfd/dbx500-prcmu.h>
  16. #include <mach/hardware.h>
  17. #include <mach/setup.h>
  18. #include <mach/irqs.h>
  19. #include "devices-db8500.h"
  20. #include "ste-dma40-db8500.h"
  21. static struct resource dma40_resources[] = {
  22. [0] = {
  23. .start = U8500_DMA_BASE,
  24. .end = U8500_DMA_BASE + SZ_4K - 1,
  25. .flags = IORESOURCE_MEM,
  26. .name = "base",
  27. },
  28. [1] = {
  29. .start = U8500_DMA_LCPA_BASE,
  30. .end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
  31. .flags = IORESOURCE_MEM,
  32. .name = "lcpa",
  33. },
  34. [2] = {
  35. .start = IRQ_DB8500_DMA,
  36. .end = IRQ_DB8500_DMA,
  37. .flags = IORESOURCE_IRQ,
  38. }
  39. };
  40. /* Default configuration for physcial memcpy */
  41. struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
  42. .mode = STEDMA40_MODE_PHYSICAL,
  43. .dir = STEDMA40_MEM_TO_MEM,
  44. .src_info.data_width = STEDMA40_BYTE_WIDTH,
  45. .src_info.psize = STEDMA40_PSIZE_PHY_1,
  46. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  47. .dst_info.data_width = STEDMA40_BYTE_WIDTH,
  48. .dst_info.psize = STEDMA40_PSIZE_PHY_1,
  49. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  50. };
  51. /* Default configuration for logical memcpy */
  52. struct stedma40_chan_cfg dma40_memcpy_conf_log = {
  53. .dir = STEDMA40_MEM_TO_MEM,
  54. .src_info.data_width = STEDMA40_BYTE_WIDTH,
  55. .src_info.psize = STEDMA40_PSIZE_LOG_1,
  56. .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  57. .dst_info.data_width = STEDMA40_BYTE_WIDTH,
  58. .dst_info.psize = STEDMA40_PSIZE_LOG_1,
  59. .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
  60. };
  61. /*
  62. * Mapping between destination event lines and physical device address.
  63. * The event line is tied to a device and therefore the address is constant.
  64. * When the address comes from a primecell it will be configured in runtime
  65. * and we set the address to -1 as a placeholder.
  66. */
  67. static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
  68. /* MUSB - these will be runtime-reconfigured */
  69. [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
  70. [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
  71. [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
  72. [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
  73. [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
  74. [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
  75. [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
  76. [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
  77. /* PrimeCells - run-time configured */
  78. [DB8500_DMA_DEV0_SPI0_TX] = -1,
  79. [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
  80. [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
  81. [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
  82. [DB8500_DMA_DEV8_SSP0_TX] = -1,
  83. [DB8500_DMA_DEV9_SSP1_TX] = -1,
  84. [DB8500_DMA_DEV11_UART2_TX] = -1,
  85. [DB8500_DMA_DEV12_UART1_TX] = -1,
  86. [DB8500_DMA_DEV13_UART0_TX] = -1,
  87. [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
  88. [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
  89. [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
  90. [DB8500_DMA_DEV33_SPI2_TX] = -1,
  91. [DB8500_DMA_DEV35_SPI1_TX] = -1,
  92. [DB8500_DMA_DEV40_SPI3_TX] = -1,
  93. [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
  94. [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
  95. [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
  96. [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
  97. [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
  98. [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
  99. [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
  100. [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
  101. };
  102. /* Mapping between source event lines and physical device address */
  103. static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
  104. /* MUSB - these will be runtime-reconfigured */
  105. [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
  106. [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
  107. [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
  108. [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
  109. [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
  110. [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
  111. [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
  112. [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
  113. /* PrimeCells */
  114. [DB8500_DMA_DEV0_SPI0_RX] = -1,
  115. [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
  116. [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
  117. [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
  118. [DB8500_DMA_DEV8_SSP0_RX] = -1,
  119. [DB8500_DMA_DEV9_SSP1_RX] = -1,
  120. [DB8500_DMA_DEV11_UART2_RX] = -1,
  121. [DB8500_DMA_DEV12_UART1_RX] = -1,
  122. [DB8500_DMA_DEV13_UART0_RX] = -1,
  123. [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
  124. [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
  125. [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
  126. [DB8500_DMA_DEV33_SPI2_RX] = -1,
  127. [DB8500_DMA_DEV35_SPI1_RX] = -1,
  128. [DB8500_DMA_DEV40_SPI3_RX] = -1,
  129. [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
  130. [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
  131. [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
  132. [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
  133. [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
  134. [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
  135. [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
  136. };
  137. /* Reserved event lines for memcpy only */
  138. static int dma40_memcpy_event[] = {
  139. DB8500_DMA_MEMCPY_TX_0,
  140. DB8500_DMA_MEMCPY_TX_1,
  141. DB8500_DMA_MEMCPY_TX_2,
  142. DB8500_DMA_MEMCPY_TX_3,
  143. DB8500_DMA_MEMCPY_TX_4,
  144. DB8500_DMA_MEMCPY_TX_5,
  145. };
  146. static struct stedma40_platform_data dma40_plat_data = {
  147. .dev_len = DB8500_DMA_NR_DEV,
  148. .dev_rx = dma40_rx_map,
  149. .dev_tx = dma40_tx_map,
  150. .memcpy = dma40_memcpy_event,
  151. .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
  152. .memcpy_conf_phy = &dma40_memcpy_conf_phy,
  153. .memcpy_conf_log = &dma40_memcpy_conf_log,
  154. .disabled_channels = {-1},
  155. };
  156. struct platform_device u8500_dma40_device = {
  157. .dev = {
  158. .platform_data = &dma40_plat_data,
  159. },
  160. .name = "dma40",
  161. .id = 0,
  162. .num_resources = ARRAY_SIZE(dma40_resources),
  163. .resource = dma40_resources
  164. };
  165. struct resource keypad_resources[] = {
  166. [0] = {
  167. .start = U8500_SKE_BASE,
  168. .end = U8500_SKE_BASE + SZ_4K - 1,
  169. .flags = IORESOURCE_MEM,
  170. },
  171. [1] = {
  172. .start = IRQ_DB8500_KB,
  173. .end = IRQ_DB8500_KB,
  174. .flags = IORESOURCE_IRQ,
  175. },
  176. };
  177. struct platform_device u8500_ske_keypad_device = {
  178. .name = "nmk-ske-keypad",
  179. .id = -1,
  180. .num_resources = ARRAY_SIZE(keypad_resources),
  181. .resource = keypad_resources,
  182. };
  183. struct prcmu_pdata db8500_prcmu_pdata = {
  184. .ab_platdata = &ab8500_platdata,
  185. .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET,
  186. .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET,
  187. };
  188. static struct resource db8500_prcmu_res[] = {
  189. {
  190. .name = "prcmu",
  191. .start = U8500_PRCMU_BASE,
  192. .end = U8500_PRCMU_BASE + SZ_8K - 1,
  193. .flags = IORESOURCE_MEM,
  194. },
  195. {
  196. .name = "prcmu-tcdm",
  197. .start = U8500_PRCMU_TCDM_BASE,
  198. .end = U8500_PRCMU_TCDM_BASE + SZ_4K - 1,
  199. .flags = IORESOURCE_MEM,
  200. },
  201. {
  202. .name = "irq",
  203. .start = IRQ_DB8500_PRCMU1,
  204. .end = IRQ_DB8500_PRCMU1,
  205. .flags = IORESOURCE_IRQ,
  206. },
  207. {
  208. .name = "prcmu-tcpm",
  209. .start = U8500_PRCMU_TCPM_BASE,
  210. .end = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
  211. .flags = IORESOURCE_MEM,
  212. },
  213. };
  214. struct platform_device db8500_prcmu_device = {
  215. .name = "db8500-prcmu",
  216. .resource = db8500_prcmu_res,
  217. .num_resources = ARRAY_SIZE(db8500_prcmu_res),
  218. .dev = {
  219. .platform_data = &db8500_prcmu_pdata,
  220. },
  221. };