mach-mini6410.c 8.3 KB

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  1. /* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
  2. *
  3. * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
  4. * Copyright 2008 Openmoko, Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * Ben Dooks <ben@simtec.co.uk>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. */
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/fb.h>
  17. #include <linux/gpio.h>
  18. #include <linux/kernel.h>
  19. #include <linux/list.h>
  20. #include <linux/dm9000.h>
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/partitions.h>
  23. #include <linux/serial_core.h>
  24. #include <linux/types.h>
  25. #include <asm/mach-types.h>
  26. #include <asm/mach/arch.h>
  27. #include <asm/mach/map.h>
  28. #include <mach/map.h>
  29. #include <mach/regs-gpio.h>
  30. #include <plat/adc.h>
  31. #include <plat/cpu.h>
  32. #include <plat/devs.h>
  33. #include <plat/fb.h>
  34. #include <linux/platform_data/mtd-nand-s3c2410.h>
  35. #include <plat/regs-serial.h>
  36. #include <linux/platform_data/touchscreen-s3c2410.h>
  37. #include <video/platform_lcd.h>
  38. #include <video/samsung_fimd.h>
  39. #include "common.h"
  40. #include "regs-modem.h"
  41. #include "regs-srom.h"
  42. #define UCON S3C2410_UCON_DEFAULT
  43. #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
  44. #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
  45. static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
  46. [0] = {
  47. .hwport = 0,
  48. .flags = 0,
  49. .ucon = UCON,
  50. .ulcon = ULCON,
  51. .ufcon = UFCON,
  52. },
  53. [1] = {
  54. .hwport = 1,
  55. .flags = 0,
  56. .ucon = UCON,
  57. .ulcon = ULCON,
  58. .ufcon = UFCON,
  59. },
  60. [2] = {
  61. .hwport = 2,
  62. .flags = 0,
  63. .ucon = UCON,
  64. .ulcon = ULCON,
  65. .ufcon = UFCON,
  66. },
  67. [3] = {
  68. .hwport = 3,
  69. .flags = 0,
  70. .ucon = UCON,
  71. .ulcon = ULCON,
  72. .ufcon = UFCON,
  73. },
  74. };
  75. /* DM9000AEP 10/100 ethernet controller */
  76. static struct resource mini6410_dm9k_resource[] = {
  77. [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
  78. [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
  79. [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
  80. | IORESOURCE_IRQ_HIGHLEVEL),
  81. };
  82. static struct dm9000_plat_data mini6410_dm9k_pdata = {
  83. .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
  84. };
  85. static struct platform_device mini6410_device_eth = {
  86. .name = "dm9000",
  87. .id = -1,
  88. .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
  89. .resource = mini6410_dm9k_resource,
  90. .dev = {
  91. .platform_data = &mini6410_dm9k_pdata,
  92. },
  93. };
  94. static struct mtd_partition mini6410_nand_part[] = {
  95. [0] = {
  96. .name = "uboot",
  97. .size = SZ_1M,
  98. .offset = 0,
  99. },
  100. [1] = {
  101. .name = "kernel",
  102. .size = SZ_2M,
  103. .offset = SZ_1M,
  104. },
  105. [2] = {
  106. .name = "rootfs",
  107. .size = MTDPART_SIZ_FULL,
  108. .offset = SZ_1M + SZ_2M,
  109. },
  110. };
  111. static struct s3c2410_nand_set mini6410_nand_sets[] = {
  112. [0] = {
  113. .name = "nand",
  114. .nr_chips = 1,
  115. .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
  116. .partitions = mini6410_nand_part,
  117. },
  118. };
  119. static struct s3c2410_platform_nand mini6410_nand_info = {
  120. .tacls = 25,
  121. .twrph0 = 55,
  122. .twrph1 = 40,
  123. .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
  124. .sets = mini6410_nand_sets,
  125. };
  126. static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
  127. .max_bpp = 32,
  128. .default_bpp = 16,
  129. .xres = 480,
  130. .yres = 272,
  131. };
  132. static struct fb_videomode mini6410_lcd_type0_timing = {
  133. /* 4.3" 480x272 */
  134. .left_margin = 3,
  135. .right_margin = 2,
  136. .upper_margin = 1,
  137. .lower_margin = 1,
  138. .hsync_len = 40,
  139. .vsync_len = 1,
  140. .xres = 480,
  141. .yres = 272,
  142. };
  143. static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
  144. .max_bpp = 32,
  145. .default_bpp = 16,
  146. .xres = 800,
  147. .yres = 480,
  148. };
  149. static struct fb_videomode mini6410_lcd_type1_timing = {
  150. /* 7.0" 800x480 */
  151. .left_margin = 8,
  152. .right_margin = 13,
  153. .upper_margin = 7,
  154. .lower_margin = 5,
  155. .hsync_len = 3,
  156. .vsync_len = 1,
  157. .xres = 800,
  158. .yres = 480,
  159. };
  160. static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
  161. {
  162. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  163. .vtiming = &mini6410_lcd_type0_timing,
  164. .win[0] = &mini6410_lcd_type0_fb_win,
  165. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  166. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  167. }, {
  168. .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
  169. .vtiming = &mini6410_lcd_type1_timing,
  170. .win[0] = &mini6410_lcd_type1_fb_win,
  171. .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
  172. .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
  173. },
  174. { },
  175. };
  176. static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
  177. unsigned int power)
  178. {
  179. if (power)
  180. gpio_direction_output(S3C64XX_GPE(0), 1);
  181. else
  182. gpio_direction_output(S3C64XX_GPE(0), 0);
  183. }
  184. static struct plat_lcd_data mini6410_lcd_power_data = {
  185. .set_power = mini6410_lcd_power_set,
  186. };
  187. static struct platform_device mini6410_lcd_powerdev = {
  188. .name = "platform-lcd",
  189. .dev.parent = &s3c_device_fb.dev,
  190. .dev.platform_data = &mini6410_lcd_power_data,
  191. };
  192. static struct platform_device *mini6410_devices[] __initdata = {
  193. &mini6410_device_eth,
  194. &s3c_device_hsmmc0,
  195. &s3c_device_hsmmc1,
  196. &s3c_device_ohci,
  197. &s3c_device_nand,
  198. &s3c_device_fb,
  199. &mini6410_lcd_powerdev,
  200. &s3c_device_adc,
  201. &s3c_device_ts,
  202. };
  203. static void __init mini6410_map_io(void)
  204. {
  205. u32 tmp;
  206. s3c64xx_init_io(NULL, 0);
  207. s3c24xx_init_clocks(12000000);
  208. s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
  209. /* set the LCD type */
  210. tmp = __raw_readl(S3C64XX_SPCON);
  211. tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
  212. tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
  213. __raw_writel(tmp, S3C64XX_SPCON);
  214. /* remove the LCD bypass */
  215. tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
  216. tmp &= ~MIFPCON_LCD_BYPASS;
  217. __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
  218. }
  219. /*
  220. * mini6410_features string
  221. *
  222. * 0-9 LCD configuration
  223. *
  224. */
  225. static char mini6410_features_str[12] __initdata = "0";
  226. static int __init mini6410_features_setup(char *str)
  227. {
  228. if (str)
  229. strlcpy(mini6410_features_str, str,
  230. sizeof(mini6410_features_str));
  231. return 1;
  232. }
  233. __setup("mini6410=", mini6410_features_setup);
  234. #define FEATURE_SCREEN (1 << 0)
  235. struct mini6410_features_t {
  236. int done;
  237. int lcd_index;
  238. };
  239. static void mini6410_parse_features(
  240. struct mini6410_features_t *features,
  241. const char *features_str)
  242. {
  243. const char *fp = features_str;
  244. features->done = 0;
  245. features->lcd_index = 0;
  246. while (*fp) {
  247. char f = *fp++;
  248. switch (f) {
  249. case '0'...'9': /* tft screen */
  250. if (features->done & FEATURE_SCREEN) {
  251. printk(KERN_INFO "MINI6410: '%c' ignored, "
  252. "screen type already set\n", f);
  253. } else {
  254. int li = f - '0';
  255. if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
  256. printk(KERN_INFO "MINI6410: '%c' out "
  257. "of range LCD mode\n", f);
  258. else {
  259. features->lcd_index = li;
  260. }
  261. }
  262. features->done |= FEATURE_SCREEN;
  263. break;
  264. }
  265. }
  266. }
  267. static void __init mini6410_machine_init(void)
  268. {
  269. u32 cs1;
  270. struct mini6410_features_t features = { 0 };
  271. printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
  272. mini6410_features_str);
  273. /* Parse the feature string */
  274. mini6410_parse_features(&features, mini6410_features_str);
  275. printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
  276. mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
  277. mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
  278. s3c_nand_set_platdata(&mini6410_nand_info);
  279. s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
  280. s3c24xx_ts_set_platdata(NULL);
  281. /* configure nCS1 width to 16 bits */
  282. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  283. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  284. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  285. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  286. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  287. S3C64XX_SROM_BW__NCS1__SHIFT;
  288. __raw_writel(cs1, S3C64XX_SROM_BW);
  289. /* set timing for nCS1 suitable for ethernet chip */
  290. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  291. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  292. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  293. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  294. (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
  295. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  296. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  297. gpio_request(S3C64XX_GPF(15), "LCD power");
  298. gpio_request(S3C64XX_GPE(0), "LCD power");
  299. platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
  300. }
  301. MACHINE_START(MINI6410, "MINI6410")
  302. /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
  303. .atag_offset = 0x100,
  304. .init_irq = s3c6410_init_irq,
  305. .map_io = mini6410_map_io,
  306. .init_machine = mini6410_machine_init,
  307. .init_late = s3c64xx_init_late,
  308. .init_time = s3c24xx_timer_init,
  309. .restart = s3c64xx_restart,
  310. MACHINE_END