dma-s3c2443.c 4.2 KB

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  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-ac97.h>
  25. #include <plat/regs-dma.h>
  26. #include <mach/regs-lcd.h>
  27. #include <mach/regs-sdi.h>
  28. #include <plat/regs-iis.h>
  29. #include <plat/regs-spi.h>
  30. #define MAP(x) { \
  31. [0] = (x) | DMA_CH_VALID, \
  32. [1] = (x) | DMA_CH_VALID, \
  33. [2] = (x) | DMA_CH_VALID, \
  34. [3] = (x) | DMA_CH_VALID, \
  35. [4] = (x) | DMA_CH_VALID, \
  36. [5] = (x) | DMA_CH_VALID, \
  37. }
  38. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  39. [DMACH_XD0] = {
  40. .name = "xdreq0",
  41. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  42. },
  43. [DMACH_XD1] = {
  44. .name = "xdreq1",
  45. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  46. },
  47. [DMACH_SDI] = { /* only on S3C2443 */
  48. .name = "sdi",
  49. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  50. },
  51. [DMACH_SPI0_RX] = {
  52. .name = "spi0-rx",
  53. .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
  54. },
  55. [DMACH_SPI0_TX] = {
  56. .name = "spi0-tx",
  57. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  58. },
  59. [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
  60. .name = "spi1-rx",
  61. .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
  62. },
  63. [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
  64. .name = "spi1-tx",
  65. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  66. },
  67. [DMACH_UART0] = {
  68. .name = "uart0",
  69. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  70. },
  71. [DMACH_UART1] = {
  72. .name = "uart1",
  73. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  74. },
  75. [DMACH_UART2] = {
  76. .name = "uart2",
  77. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  78. },
  79. [DMACH_UART3] = {
  80. .name = "uart3",
  81. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  82. },
  83. [DMACH_UART0_SRC2] = {
  84. .name = "uart0",
  85. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  86. },
  87. [DMACH_UART1_SRC2] = {
  88. .name = "uart1",
  89. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  90. },
  91. [DMACH_UART2_SRC2] = {
  92. .name = "uart2",
  93. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  94. },
  95. [DMACH_UART3_SRC2] = {
  96. .name = "uart3",
  97. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  98. },
  99. [DMACH_TIMER] = {
  100. .name = "timer",
  101. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  102. },
  103. [DMACH_I2S_IN] = {
  104. .name = "i2s-sdi",
  105. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  106. },
  107. [DMACH_I2S_OUT] = {
  108. .name = "i2s-sdo",
  109. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  110. },
  111. [DMACH_PCM_IN] = {
  112. .name = "pcm-in",
  113. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  114. },
  115. [DMACH_PCM_OUT] = {
  116. .name = "pcm-out",
  117. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  118. },
  119. [DMACH_MIC_IN] = {
  120. .name = "mic-in",
  121. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  122. },
  123. };
  124. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  125. struct s3c24xx_dma_map *map)
  126. {
  127. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  128. chan->regs + S3C2443_DMA_DMAREQSEL);
  129. }
  130. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  131. .select = s3c2443_dma_select,
  132. .dcon_mask = 0,
  133. .map = s3c2443_dma_mappings,
  134. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  135. };
  136. static int __init s3c2443_dma_add(struct device *dev,
  137. struct subsys_interface *sif)
  138. {
  139. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  140. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  141. }
  142. #ifdef CONFIG_CPU_S3C2416
  143. /* S3C2416 DMA contains the same selection table as the S3C2443 */
  144. static struct subsys_interface s3c2416_dma_interface = {
  145. .name = "s3c2416_dma",
  146. .subsys = &s3c2416_subsys,
  147. .add_dev = s3c2443_dma_add,
  148. };
  149. static int __init s3c2416_dma_init(void)
  150. {
  151. return subsys_interface_register(&s3c2416_dma_interface);
  152. }
  153. arch_initcall(s3c2416_dma_init);
  154. #endif
  155. #ifdef CONFIG_CPU_S3C2443
  156. static struct subsys_interface s3c2443_dma_interface = {
  157. .name = "s3c2443_dma",
  158. .subsys = &s3c2443_subsys,
  159. .add_dev = s3c2443_dma_add,
  160. };
  161. static int __init s3c2443_dma_init(void)
  162. {
  163. return subsys_interface_register(&s3c2443_dma_interface);
  164. }
  165. arch_initcall(s3c2443_dma_init);
  166. #endif