devices.c 22 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132
  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <mach/udc.h>
  9. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  10. #include <linux/platform_data/video-pxafb.h>
  11. #include <linux/platform_data/mmc-pxamci.h>
  12. #include <linux/platform_data/irda-pxaficp.h>
  13. #include <mach/irqs.h>
  14. #include <linux/platform_data/usb-ohci-pxa27x.h>
  15. #include <linux/platform_data/keypad-pxa27x.h>
  16. #include <linux/platform_data/camera-pxa.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = -1,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. };
  81. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  82. {
  83. memcpy(&pxa_udc_info, info, sizeof *info);
  84. }
  85. static struct resource pxa2xx_udc_resources[] = {
  86. [0] = {
  87. .start = 0x40600000,
  88. .end = 0x4060ffff,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USB,
  93. .end = IRQ_USB,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 udc_dma_mask = ~(u32)0;
  98. struct platform_device pxa25x_device_udc = {
  99. .name = "pxa25x-udc",
  100. .id = -1,
  101. .resource = pxa2xx_udc_resources,
  102. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  103. .dev = {
  104. .platform_data = &pxa_udc_info,
  105. .dma_mask = &udc_dma_mask,
  106. }
  107. };
  108. struct platform_device pxa27x_device_udc = {
  109. .name = "pxa27x-udc",
  110. .id = -1,
  111. .resource = pxa2xx_udc_resources,
  112. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  113. .dev = {
  114. .platform_data = &pxa_udc_info,
  115. .dma_mask = &udc_dma_mask,
  116. }
  117. };
  118. #ifdef CONFIG_PXA3xx
  119. static struct resource pxa3xx_u2d_resources[] = {
  120. [0] = {
  121. .start = 0x54100000,
  122. .end = 0x54100fff,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = IRQ_USB2,
  127. .end = IRQ_USB2,
  128. .flags = IORESOURCE_IRQ,
  129. },
  130. };
  131. struct platform_device pxa3xx_device_u2d = {
  132. .name = "pxa3xx-u2d",
  133. .id = -1,
  134. .resource = pxa3xx_u2d_resources,
  135. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  136. };
  137. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  138. {
  139. pxa_register_device(&pxa3xx_device_u2d, info);
  140. }
  141. #endif /* CONFIG_PXA3xx */
  142. static struct resource pxafb_resources[] = {
  143. [0] = {
  144. .start = 0x44000000,
  145. .end = 0x4400ffff,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. [1] = {
  149. .start = IRQ_LCD,
  150. .end = IRQ_LCD,
  151. .flags = IORESOURCE_IRQ,
  152. },
  153. };
  154. static u64 fb_dma_mask = ~(u64)0;
  155. struct platform_device pxa_device_fb = {
  156. .name = "pxa2xx-fb",
  157. .id = -1,
  158. .dev = {
  159. .dma_mask = &fb_dma_mask,
  160. .coherent_dma_mask = 0xffffffff,
  161. },
  162. .num_resources = ARRAY_SIZE(pxafb_resources),
  163. .resource = pxafb_resources,
  164. };
  165. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  166. {
  167. pxa_device_fb.dev.parent = parent;
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. static struct resource pxa_resource_ffuart[] = {
  171. {
  172. .start = 0x40100000,
  173. .end = 0x40100023,
  174. .flags = IORESOURCE_MEM,
  175. }, {
  176. .start = IRQ_FFUART,
  177. .end = IRQ_FFUART,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. };
  181. struct platform_device pxa_device_ffuart = {
  182. .name = "pxa2xx-uart",
  183. .id = 0,
  184. .resource = pxa_resource_ffuart,
  185. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  186. };
  187. void __init pxa_set_ffuart_info(void *info)
  188. {
  189. pxa_register_device(&pxa_device_ffuart, info);
  190. }
  191. static struct resource pxa_resource_btuart[] = {
  192. {
  193. .start = 0x40200000,
  194. .end = 0x40200023,
  195. .flags = IORESOURCE_MEM,
  196. }, {
  197. .start = IRQ_BTUART,
  198. .end = IRQ_BTUART,
  199. .flags = IORESOURCE_IRQ,
  200. }
  201. };
  202. struct platform_device pxa_device_btuart = {
  203. .name = "pxa2xx-uart",
  204. .id = 1,
  205. .resource = pxa_resource_btuart,
  206. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  207. };
  208. void __init pxa_set_btuart_info(void *info)
  209. {
  210. pxa_register_device(&pxa_device_btuart, info);
  211. }
  212. static struct resource pxa_resource_stuart[] = {
  213. {
  214. .start = 0x40700000,
  215. .end = 0x40700023,
  216. .flags = IORESOURCE_MEM,
  217. }, {
  218. .start = IRQ_STUART,
  219. .end = IRQ_STUART,
  220. .flags = IORESOURCE_IRQ,
  221. }
  222. };
  223. struct platform_device pxa_device_stuart = {
  224. .name = "pxa2xx-uart",
  225. .id = 2,
  226. .resource = pxa_resource_stuart,
  227. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  228. };
  229. void __init pxa_set_stuart_info(void *info)
  230. {
  231. pxa_register_device(&pxa_device_stuart, info);
  232. }
  233. static struct resource pxa_resource_hwuart[] = {
  234. {
  235. .start = 0x41600000,
  236. .end = 0x4160002F,
  237. .flags = IORESOURCE_MEM,
  238. }, {
  239. .start = IRQ_HWUART,
  240. .end = IRQ_HWUART,
  241. .flags = IORESOURCE_IRQ,
  242. }
  243. };
  244. struct platform_device pxa_device_hwuart = {
  245. .name = "pxa2xx-uart",
  246. .id = 3,
  247. .resource = pxa_resource_hwuart,
  248. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  249. };
  250. void __init pxa_set_hwuart_info(void *info)
  251. {
  252. if (cpu_is_pxa255())
  253. pxa_register_device(&pxa_device_hwuart, info);
  254. else
  255. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  256. }
  257. static struct resource pxai2c_resources[] = {
  258. {
  259. .start = 0x40301680,
  260. .end = 0x403016a3,
  261. .flags = IORESOURCE_MEM,
  262. }, {
  263. .start = IRQ_I2C,
  264. .end = IRQ_I2C,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. };
  268. struct platform_device pxa_device_i2c = {
  269. .name = "pxa2xx-i2c",
  270. .id = 0,
  271. .resource = pxai2c_resources,
  272. .num_resources = ARRAY_SIZE(pxai2c_resources),
  273. };
  274. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  275. {
  276. pxa_register_device(&pxa_device_i2c, info);
  277. }
  278. #ifdef CONFIG_PXA27x
  279. static struct resource pxa27x_resources_i2c_power[] = {
  280. {
  281. .start = 0x40f00180,
  282. .end = 0x40f001a3,
  283. .flags = IORESOURCE_MEM,
  284. }, {
  285. .start = IRQ_PWRI2C,
  286. .end = IRQ_PWRI2C,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. };
  290. struct platform_device pxa27x_device_i2c_power = {
  291. .name = "pxa2xx-i2c",
  292. .id = 1,
  293. .resource = pxa27x_resources_i2c_power,
  294. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  295. };
  296. #endif
  297. static struct resource pxai2s_resources[] = {
  298. {
  299. .start = 0x40400000,
  300. .end = 0x40400083,
  301. .flags = IORESOURCE_MEM,
  302. }, {
  303. .start = IRQ_I2S,
  304. .end = IRQ_I2S,
  305. .flags = IORESOURCE_IRQ,
  306. },
  307. };
  308. struct platform_device pxa_device_i2s = {
  309. .name = "pxa2xx-i2s",
  310. .id = -1,
  311. .resource = pxai2s_resources,
  312. .num_resources = ARRAY_SIZE(pxai2s_resources),
  313. };
  314. struct platform_device pxa_device_asoc_ssp1 = {
  315. .name = "pxa-ssp-dai",
  316. .id = 0,
  317. };
  318. struct platform_device pxa_device_asoc_ssp2= {
  319. .name = "pxa-ssp-dai",
  320. .id = 1,
  321. };
  322. struct platform_device pxa_device_asoc_ssp3 = {
  323. .name = "pxa-ssp-dai",
  324. .id = 2,
  325. };
  326. struct platform_device pxa_device_asoc_ssp4 = {
  327. .name = "pxa-ssp-dai",
  328. .id = 3,
  329. };
  330. struct platform_device pxa_device_asoc_platform = {
  331. .name = "pxa-pcm-audio",
  332. .id = -1,
  333. };
  334. static u64 pxaficp_dmamask = ~(u32)0;
  335. static struct resource pxa_ir_resources[] = {
  336. [0] = {
  337. .start = IRQ_STUART,
  338. .end = IRQ_STUART,
  339. .flags = IORESOURCE_IRQ,
  340. },
  341. [1] = {
  342. .start = IRQ_ICP,
  343. .end = IRQ_ICP,
  344. .flags = IORESOURCE_IRQ,
  345. },
  346. };
  347. struct platform_device pxa_device_ficp = {
  348. .name = "pxa2xx-ir",
  349. .id = -1,
  350. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  351. .resource = pxa_ir_resources,
  352. .dev = {
  353. .dma_mask = &pxaficp_dmamask,
  354. .coherent_dma_mask = 0xffffffff,
  355. },
  356. };
  357. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  358. {
  359. pxa_register_device(&pxa_device_ficp, info);
  360. }
  361. static struct resource pxa_rtc_resources[] = {
  362. [0] = {
  363. .start = 0x40900000,
  364. .end = 0x40900000 + 0x3b,
  365. .flags = IORESOURCE_MEM,
  366. },
  367. [1] = {
  368. .start = IRQ_RTC1Hz,
  369. .end = IRQ_RTC1Hz,
  370. .name = "rtc 1Hz",
  371. .flags = IORESOURCE_IRQ,
  372. },
  373. [2] = {
  374. .start = IRQ_RTCAlrm,
  375. .end = IRQ_RTCAlrm,
  376. .name = "rtc alarm",
  377. .flags = IORESOURCE_IRQ,
  378. },
  379. };
  380. struct platform_device pxa_device_rtc = {
  381. .name = "pxa-rtc",
  382. .id = -1,
  383. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  384. .resource = pxa_rtc_resources,
  385. };
  386. static struct resource sa1100_rtc_resources[] = {
  387. {
  388. .start = IRQ_RTC1Hz,
  389. .end = IRQ_RTC1Hz,
  390. .name = "rtc 1Hz",
  391. .flags = IORESOURCE_IRQ,
  392. }, {
  393. .start = IRQ_RTCAlrm,
  394. .end = IRQ_RTCAlrm,
  395. .name = "rtc alarm",
  396. .flags = IORESOURCE_IRQ,
  397. },
  398. };
  399. struct platform_device sa1100_device_rtc = {
  400. .name = "sa1100-rtc",
  401. .id = -1,
  402. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  403. .resource = sa1100_rtc_resources,
  404. };
  405. static struct resource pxa_ac97_resources[] = {
  406. [0] = {
  407. .start = 0x40500000,
  408. .end = 0x40500000 + 0xfff,
  409. .flags = IORESOURCE_MEM,
  410. },
  411. [1] = {
  412. .start = IRQ_AC97,
  413. .end = IRQ_AC97,
  414. .flags = IORESOURCE_IRQ,
  415. },
  416. };
  417. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  418. struct platform_device pxa_device_ac97 = {
  419. .name = "pxa2xx-ac97",
  420. .id = -1,
  421. .dev = {
  422. .dma_mask = &pxa_ac97_dmamask,
  423. .coherent_dma_mask = 0xffffffff,
  424. },
  425. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  426. .resource = pxa_ac97_resources,
  427. };
  428. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  429. {
  430. pxa_register_device(&pxa_device_ac97, ops);
  431. }
  432. #ifdef CONFIG_PXA25x
  433. static struct resource pxa25x_resource_pwm0[] = {
  434. [0] = {
  435. .start = 0x40b00000,
  436. .end = 0x40b0000f,
  437. .flags = IORESOURCE_MEM,
  438. },
  439. };
  440. struct platform_device pxa25x_device_pwm0 = {
  441. .name = "pxa25x-pwm",
  442. .id = 0,
  443. .resource = pxa25x_resource_pwm0,
  444. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  445. };
  446. static struct resource pxa25x_resource_pwm1[] = {
  447. [0] = {
  448. .start = 0x40c00000,
  449. .end = 0x40c0000f,
  450. .flags = IORESOURCE_MEM,
  451. },
  452. };
  453. struct platform_device pxa25x_device_pwm1 = {
  454. .name = "pxa25x-pwm",
  455. .id = 1,
  456. .resource = pxa25x_resource_pwm1,
  457. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  458. };
  459. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  460. static struct resource pxa25x_resource_ssp[] = {
  461. [0] = {
  462. .start = 0x41000000,
  463. .end = 0x4100001f,
  464. .flags = IORESOURCE_MEM,
  465. },
  466. [1] = {
  467. .start = IRQ_SSP,
  468. .end = IRQ_SSP,
  469. .flags = IORESOURCE_IRQ,
  470. },
  471. [2] = {
  472. /* DRCMR for RX */
  473. .start = 13,
  474. .end = 13,
  475. .flags = IORESOURCE_DMA,
  476. },
  477. [3] = {
  478. /* DRCMR for TX */
  479. .start = 14,
  480. .end = 14,
  481. .flags = IORESOURCE_DMA,
  482. },
  483. };
  484. struct platform_device pxa25x_device_ssp = {
  485. .name = "pxa25x-ssp",
  486. .id = 0,
  487. .dev = {
  488. .dma_mask = &pxa25x_ssp_dma_mask,
  489. .coherent_dma_mask = DMA_BIT_MASK(32),
  490. },
  491. .resource = pxa25x_resource_ssp,
  492. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  493. };
  494. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  495. static struct resource pxa25x_resource_nssp[] = {
  496. [0] = {
  497. .start = 0x41400000,
  498. .end = 0x4140002f,
  499. .flags = IORESOURCE_MEM,
  500. },
  501. [1] = {
  502. .start = IRQ_NSSP,
  503. .end = IRQ_NSSP,
  504. .flags = IORESOURCE_IRQ,
  505. },
  506. [2] = {
  507. /* DRCMR for RX */
  508. .start = 15,
  509. .end = 15,
  510. .flags = IORESOURCE_DMA,
  511. },
  512. [3] = {
  513. /* DRCMR for TX */
  514. .start = 16,
  515. .end = 16,
  516. .flags = IORESOURCE_DMA,
  517. },
  518. };
  519. struct platform_device pxa25x_device_nssp = {
  520. .name = "pxa25x-nssp",
  521. .id = 1,
  522. .dev = {
  523. .dma_mask = &pxa25x_nssp_dma_mask,
  524. .coherent_dma_mask = DMA_BIT_MASK(32),
  525. },
  526. .resource = pxa25x_resource_nssp,
  527. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  528. };
  529. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  530. static struct resource pxa25x_resource_assp[] = {
  531. [0] = {
  532. .start = 0x41500000,
  533. .end = 0x4150002f,
  534. .flags = IORESOURCE_MEM,
  535. },
  536. [1] = {
  537. .start = IRQ_ASSP,
  538. .end = IRQ_ASSP,
  539. .flags = IORESOURCE_IRQ,
  540. },
  541. [2] = {
  542. /* DRCMR for RX */
  543. .start = 23,
  544. .end = 23,
  545. .flags = IORESOURCE_DMA,
  546. },
  547. [3] = {
  548. /* DRCMR for TX */
  549. .start = 24,
  550. .end = 24,
  551. .flags = IORESOURCE_DMA,
  552. },
  553. };
  554. struct platform_device pxa25x_device_assp = {
  555. /* ASSP is basically equivalent to NSSP */
  556. .name = "pxa25x-nssp",
  557. .id = 2,
  558. .dev = {
  559. .dma_mask = &pxa25x_assp_dma_mask,
  560. .coherent_dma_mask = DMA_BIT_MASK(32),
  561. },
  562. .resource = pxa25x_resource_assp,
  563. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  564. };
  565. #endif /* CONFIG_PXA25x */
  566. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  567. static struct resource pxa27x_resource_camera[] = {
  568. [0] = {
  569. .start = 0x50000000,
  570. .end = 0x50000fff,
  571. .flags = IORESOURCE_MEM,
  572. },
  573. [1] = {
  574. .start = IRQ_CAMERA,
  575. .end = IRQ_CAMERA,
  576. .flags = IORESOURCE_IRQ,
  577. },
  578. };
  579. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  580. static struct platform_device pxa27x_device_camera = {
  581. .name = "pxa27x-camera",
  582. .id = 0, /* This is used to put cameras on this interface */
  583. .dev = {
  584. .dma_mask = &pxa27x_dma_mask_camera,
  585. .coherent_dma_mask = 0xffffffff,
  586. },
  587. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  588. .resource = pxa27x_resource_camera,
  589. };
  590. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  591. {
  592. pxa_register_device(&pxa27x_device_camera, info);
  593. }
  594. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  595. static struct resource pxa27x_resource_ohci[] = {
  596. [0] = {
  597. .start = 0x4C000000,
  598. .end = 0x4C00ff6f,
  599. .flags = IORESOURCE_MEM,
  600. },
  601. [1] = {
  602. .start = IRQ_USBH1,
  603. .end = IRQ_USBH1,
  604. .flags = IORESOURCE_IRQ,
  605. },
  606. };
  607. struct platform_device pxa27x_device_ohci = {
  608. .name = "pxa27x-ohci",
  609. .id = -1,
  610. .dev = {
  611. .dma_mask = &pxa27x_ohci_dma_mask,
  612. .coherent_dma_mask = DMA_BIT_MASK(32),
  613. },
  614. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  615. .resource = pxa27x_resource_ohci,
  616. };
  617. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  618. {
  619. pxa_register_device(&pxa27x_device_ohci, info);
  620. }
  621. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  622. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  623. static struct resource pxa27x_resource_keypad[] = {
  624. [0] = {
  625. .start = 0x41500000,
  626. .end = 0x4150004c,
  627. .flags = IORESOURCE_MEM,
  628. },
  629. [1] = {
  630. .start = IRQ_KEYPAD,
  631. .end = IRQ_KEYPAD,
  632. .flags = IORESOURCE_IRQ,
  633. },
  634. };
  635. struct platform_device pxa27x_device_keypad = {
  636. .name = "pxa27x-keypad",
  637. .id = -1,
  638. .resource = pxa27x_resource_keypad,
  639. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  640. };
  641. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  642. {
  643. pxa_register_device(&pxa27x_device_keypad, info);
  644. }
  645. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  646. static struct resource pxa27x_resource_ssp1[] = {
  647. [0] = {
  648. .start = 0x41000000,
  649. .end = 0x4100003f,
  650. .flags = IORESOURCE_MEM,
  651. },
  652. [1] = {
  653. .start = IRQ_SSP,
  654. .end = IRQ_SSP,
  655. .flags = IORESOURCE_IRQ,
  656. },
  657. [2] = {
  658. /* DRCMR for RX */
  659. .start = 13,
  660. .end = 13,
  661. .flags = IORESOURCE_DMA,
  662. },
  663. [3] = {
  664. /* DRCMR for TX */
  665. .start = 14,
  666. .end = 14,
  667. .flags = IORESOURCE_DMA,
  668. },
  669. };
  670. struct platform_device pxa27x_device_ssp1 = {
  671. .name = "pxa27x-ssp",
  672. .id = 0,
  673. .dev = {
  674. .dma_mask = &pxa27x_ssp1_dma_mask,
  675. .coherent_dma_mask = DMA_BIT_MASK(32),
  676. },
  677. .resource = pxa27x_resource_ssp1,
  678. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  679. };
  680. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  681. static struct resource pxa27x_resource_ssp2[] = {
  682. [0] = {
  683. .start = 0x41700000,
  684. .end = 0x4170003f,
  685. .flags = IORESOURCE_MEM,
  686. },
  687. [1] = {
  688. .start = IRQ_SSP2,
  689. .end = IRQ_SSP2,
  690. .flags = IORESOURCE_IRQ,
  691. },
  692. [2] = {
  693. /* DRCMR for RX */
  694. .start = 15,
  695. .end = 15,
  696. .flags = IORESOURCE_DMA,
  697. },
  698. [3] = {
  699. /* DRCMR for TX */
  700. .start = 16,
  701. .end = 16,
  702. .flags = IORESOURCE_DMA,
  703. },
  704. };
  705. struct platform_device pxa27x_device_ssp2 = {
  706. .name = "pxa27x-ssp",
  707. .id = 1,
  708. .dev = {
  709. .dma_mask = &pxa27x_ssp2_dma_mask,
  710. .coherent_dma_mask = DMA_BIT_MASK(32),
  711. },
  712. .resource = pxa27x_resource_ssp2,
  713. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  714. };
  715. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  716. static struct resource pxa27x_resource_ssp3[] = {
  717. [0] = {
  718. .start = 0x41900000,
  719. .end = 0x4190003f,
  720. .flags = IORESOURCE_MEM,
  721. },
  722. [1] = {
  723. .start = IRQ_SSP3,
  724. .end = IRQ_SSP3,
  725. .flags = IORESOURCE_IRQ,
  726. },
  727. [2] = {
  728. /* DRCMR for RX */
  729. .start = 66,
  730. .end = 66,
  731. .flags = IORESOURCE_DMA,
  732. },
  733. [3] = {
  734. /* DRCMR for TX */
  735. .start = 67,
  736. .end = 67,
  737. .flags = IORESOURCE_DMA,
  738. },
  739. };
  740. struct platform_device pxa27x_device_ssp3 = {
  741. .name = "pxa27x-ssp",
  742. .id = 2,
  743. .dev = {
  744. .dma_mask = &pxa27x_ssp3_dma_mask,
  745. .coherent_dma_mask = DMA_BIT_MASK(32),
  746. },
  747. .resource = pxa27x_resource_ssp3,
  748. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  749. };
  750. static struct resource pxa27x_resource_pwm0[] = {
  751. [0] = {
  752. .start = 0x40b00000,
  753. .end = 0x40b0001f,
  754. .flags = IORESOURCE_MEM,
  755. },
  756. };
  757. struct platform_device pxa27x_device_pwm0 = {
  758. .name = "pxa27x-pwm",
  759. .id = 0,
  760. .resource = pxa27x_resource_pwm0,
  761. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  762. };
  763. static struct resource pxa27x_resource_pwm1[] = {
  764. [0] = {
  765. .start = 0x40c00000,
  766. .end = 0x40c0001f,
  767. .flags = IORESOURCE_MEM,
  768. },
  769. };
  770. struct platform_device pxa27x_device_pwm1 = {
  771. .name = "pxa27x-pwm",
  772. .id = 1,
  773. .resource = pxa27x_resource_pwm1,
  774. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  775. };
  776. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  777. #ifdef CONFIG_PXA3xx
  778. static struct resource pxa3xx_resources_mci2[] = {
  779. [0] = {
  780. .start = 0x42000000,
  781. .end = 0x42000fff,
  782. .flags = IORESOURCE_MEM,
  783. },
  784. [1] = {
  785. .start = IRQ_MMC2,
  786. .end = IRQ_MMC2,
  787. .flags = IORESOURCE_IRQ,
  788. },
  789. [2] = {
  790. .start = 93,
  791. .end = 93,
  792. .flags = IORESOURCE_DMA,
  793. },
  794. [3] = {
  795. .start = 94,
  796. .end = 94,
  797. .flags = IORESOURCE_DMA,
  798. },
  799. };
  800. struct platform_device pxa3xx_device_mci2 = {
  801. .name = "pxa2xx-mci",
  802. .id = 1,
  803. .dev = {
  804. .dma_mask = &pxamci_dmamask,
  805. .coherent_dma_mask = 0xffffffff,
  806. },
  807. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  808. .resource = pxa3xx_resources_mci2,
  809. };
  810. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  811. {
  812. pxa_register_device(&pxa3xx_device_mci2, info);
  813. }
  814. static struct resource pxa3xx_resources_mci3[] = {
  815. [0] = {
  816. .start = 0x42500000,
  817. .end = 0x42500fff,
  818. .flags = IORESOURCE_MEM,
  819. },
  820. [1] = {
  821. .start = IRQ_MMC3,
  822. .end = IRQ_MMC3,
  823. .flags = IORESOURCE_IRQ,
  824. },
  825. [2] = {
  826. .start = 100,
  827. .end = 100,
  828. .flags = IORESOURCE_DMA,
  829. },
  830. [3] = {
  831. .start = 101,
  832. .end = 101,
  833. .flags = IORESOURCE_DMA,
  834. },
  835. };
  836. struct platform_device pxa3xx_device_mci3 = {
  837. .name = "pxa2xx-mci",
  838. .id = 2,
  839. .dev = {
  840. .dma_mask = &pxamci_dmamask,
  841. .coherent_dma_mask = 0xffffffff,
  842. },
  843. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  844. .resource = pxa3xx_resources_mci3,
  845. };
  846. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  847. {
  848. pxa_register_device(&pxa3xx_device_mci3, info);
  849. }
  850. static struct resource pxa3xx_resources_gcu[] = {
  851. {
  852. .start = 0x54000000,
  853. .end = 0x54000fff,
  854. .flags = IORESOURCE_MEM,
  855. },
  856. {
  857. .start = IRQ_GCU,
  858. .end = IRQ_GCU,
  859. .flags = IORESOURCE_IRQ,
  860. },
  861. };
  862. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  863. struct platform_device pxa3xx_device_gcu = {
  864. .name = "pxa3xx-gcu",
  865. .id = -1,
  866. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  867. .resource = pxa3xx_resources_gcu,
  868. .dev = {
  869. .dma_mask = &pxa3xx_gcu_dmamask,
  870. .coherent_dma_mask = 0xffffffff,
  871. },
  872. };
  873. #endif /* CONFIG_PXA3xx */
  874. #if defined(CONFIG_PXA3xx)
  875. static struct resource pxa3xx_resources_i2c_power[] = {
  876. {
  877. .start = 0x40f500c0,
  878. .end = 0x40f500d3,
  879. .flags = IORESOURCE_MEM,
  880. }, {
  881. .start = IRQ_PWRI2C,
  882. .end = IRQ_PWRI2C,
  883. .flags = IORESOURCE_IRQ,
  884. },
  885. };
  886. struct platform_device pxa3xx_device_i2c_power = {
  887. .name = "pxa3xx-pwri2c",
  888. .id = 1,
  889. .resource = pxa3xx_resources_i2c_power,
  890. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  891. };
  892. static struct resource pxa3xx_resources_nand[] = {
  893. [0] = {
  894. .start = 0x43100000,
  895. .end = 0x43100053,
  896. .flags = IORESOURCE_MEM,
  897. },
  898. [1] = {
  899. .start = IRQ_NAND,
  900. .end = IRQ_NAND,
  901. .flags = IORESOURCE_IRQ,
  902. },
  903. [2] = {
  904. /* DRCMR for Data DMA */
  905. .start = 97,
  906. .end = 97,
  907. .flags = IORESOURCE_DMA,
  908. },
  909. [3] = {
  910. /* DRCMR for Command DMA */
  911. .start = 99,
  912. .end = 99,
  913. .flags = IORESOURCE_DMA,
  914. },
  915. };
  916. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  917. struct platform_device pxa3xx_device_nand = {
  918. .name = "pxa3xx-nand",
  919. .id = -1,
  920. .dev = {
  921. .dma_mask = &pxa3xx_nand_dma_mask,
  922. .coherent_dma_mask = DMA_BIT_MASK(32),
  923. },
  924. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  925. .resource = pxa3xx_resources_nand,
  926. };
  927. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  928. {
  929. pxa_register_device(&pxa3xx_device_nand, info);
  930. }
  931. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  932. static struct resource pxa3xx_resource_ssp4[] = {
  933. [0] = {
  934. .start = 0x41a00000,
  935. .end = 0x41a0003f,
  936. .flags = IORESOURCE_MEM,
  937. },
  938. [1] = {
  939. .start = IRQ_SSP4,
  940. .end = IRQ_SSP4,
  941. .flags = IORESOURCE_IRQ,
  942. },
  943. [2] = {
  944. /* DRCMR for RX */
  945. .start = 2,
  946. .end = 2,
  947. .flags = IORESOURCE_DMA,
  948. },
  949. [3] = {
  950. /* DRCMR for TX */
  951. .start = 3,
  952. .end = 3,
  953. .flags = IORESOURCE_DMA,
  954. },
  955. };
  956. struct platform_device pxa3xx_device_ssp4 = {
  957. /* PXA3xx SSP is basically equivalent to PXA27x */
  958. .name = "pxa27x-ssp",
  959. .id = 3,
  960. .dev = {
  961. .dma_mask = &pxa3xx_ssp4_dma_mask,
  962. .coherent_dma_mask = DMA_BIT_MASK(32),
  963. },
  964. .resource = pxa3xx_resource_ssp4,
  965. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  966. };
  967. #endif /* CONFIG_PXA3xx */
  968. struct resource pxa_resource_gpio[] = {
  969. {
  970. .start = 0x40e00000,
  971. .end = 0x40e0ffff,
  972. .flags = IORESOURCE_MEM,
  973. }, {
  974. .start = IRQ_GPIO0,
  975. .end = IRQ_GPIO0,
  976. .name = "gpio0",
  977. .flags = IORESOURCE_IRQ,
  978. }, {
  979. .start = IRQ_GPIO1,
  980. .end = IRQ_GPIO1,
  981. .name = "gpio1",
  982. .flags = IORESOURCE_IRQ,
  983. }, {
  984. .start = IRQ_GPIO_2_x,
  985. .end = IRQ_GPIO_2_x,
  986. .name = "gpio_mux",
  987. .flags = IORESOURCE_IRQ,
  988. },
  989. };
  990. struct platform_device pxa_device_gpio = {
  991. .name = "pxa-gpio",
  992. .id = -1,
  993. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  994. .resource = pxa_resource_gpio,
  995. };
  996. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  997. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  998. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  999. {
  1000. struct platform_device *pd;
  1001. pd = platform_device_alloc("pxa2xx-spi", id);
  1002. if (pd == NULL) {
  1003. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  1004. id);
  1005. return;
  1006. }
  1007. pd->dev.platform_data = info;
  1008. platform_device_add(pd);
  1009. }