cpuidle44xx.c 6.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257
  1. /*
  2. * OMAP4 CPU idle Routines
  3. *
  4. * Copyright (C) 2011 Texas Instruments, Inc.
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * Rajendra Nayak <rnayak@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/cpuidle.h>
  14. #include <linux/cpu_pm.h>
  15. #include <linux/export.h>
  16. #include <linux/clockchips.h>
  17. #include <asm/proc-fns.h>
  18. #include "common.h"
  19. #include "pm.h"
  20. #include "prm.h"
  21. #include "clockdomain.h"
  22. /* Machine specific information */
  23. struct omap4_idle_statedata {
  24. u32 cpu_state;
  25. u32 mpu_logic_state;
  26. u32 mpu_state;
  27. };
  28. static struct omap4_idle_statedata omap4_idle_data[] = {
  29. {
  30. .cpu_state = PWRDM_POWER_ON,
  31. .mpu_state = PWRDM_POWER_ON,
  32. .mpu_logic_state = PWRDM_POWER_RET,
  33. },
  34. {
  35. .cpu_state = PWRDM_POWER_OFF,
  36. .mpu_state = PWRDM_POWER_RET,
  37. .mpu_logic_state = PWRDM_POWER_RET,
  38. },
  39. {
  40. .cpu_state = PWRDM_POWER_OFF,
  41. .mpu_state = PWRDM_POWER_RET,
  42. .mpu_logic_state = PWRDM_POWER_OFF,
  43. },
  44. };
  45. static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
  46. static struct clockdomain *cpu_clkdm[NR_CPUS];
  47. static atomic_t abort_barrier;
  48. static bool cpu_done[NR_CPUS];
  49. /* Private functions */
  50. /**
  51. * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  52. * @dev: cpuidle device
  53. * @drv: cpuidle driver
  54. * @index: the index of state to be entered
  55. *
  56. * Called from the CPUidle framework to program the device to the
  57. * specified low power state selected by the governor.
  58. * Returns the amount of time spent in the low power state.
  59. */
  60. static int omap4_enter_idle_simple(struct cpuidle_device *dev,
  61. struct cpuidle_driver *drv,
  62. int index)
  63. {
  64. local_fiq_disable();
  65. omap_do_wfi();
  66. local_fiq_enable();
  67. return index;
  68. }
  69. static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
  70. struct cpuidle_driver *drv,
  71. int index)
  72. {
  73. struct omap4_idle_statedata *cx = &omap4_idle_data[index];
  74. int cpu_id = smp_processor_id();
  75. local_fiq_disable();
  76. /*
  77. * CPU0 has to wait and stay ON until CPU1 is OFF state.
  78. * This is necessary to honour hardware recommondation
  79. * of triggeing all the possible low power modes once CPU1 is
  80. * out of coherency and in OFF mode.
  81. */
  82. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  83. while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
  84. cpu_relax();
  85. /*
  86. * CPU1 could have already entered & exited idle
  87. * without hitting off because of a wakeup
  88. * or a failed attempt to hit off mode. Check for
  89. * that here, otherwise we could spin forever
  90. * waiting for CPU1 off.
  91. */
  92. if (cpu_done[1])
  93. goto fail;
  94. }
  95. }
  96. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  97. /*
  98. * Call idle CPU PM enter notifier chain so that
  99. * VFP and per CPU interrupt context is saved.
  100. */
  101. cpu_pm_enter();
  102. if (dev->cpu == 0) {
  103. pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  104. omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
  105. /*
  106. * Call idle CPU cluster PM enter notifier chain
  107. * to save GIC and wakeupgen context.
  108. */
  109. if ((cx->mpu_state == PWRDM_POWER_RET) &&
  110. (cx->mpu_logic_state == PWRDM_POWER_OFF))
  111. cpu_cluster_pm_enter();
  112. }
  113. omap4_enter_lowpower(dev->cpu, cx->cpu_state);
  114. cpu_done[dev->cpu] = true;
  115. /* Wakeup CPU1 only if it is not offlined */
  116. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  117. clkdm_wakeup(cpu_clkdm[1]);
  118. clkdm_allow_idle(cpu_clkdm[1]);
  119. }
  120. /*
  121. * Call idle CPU PM exit notifier chain to restore
  122. * VFP and per CPU IRQ context.
  123. */
  124. cpu_pm_exit();
  125. /*
  126. * Call idle CPU cluster PM exit notifier chain
  127. * to restore GIC and wakeupgen context.
  128. */
  129. if (omap4_mpuss_read_prev_context_state())
  130. cpu_cluster_pm_exit();
  131. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
  132. fail:
  133. cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
  134. cpu_done[dev->cpu] = false;
  135. local_fiq_enable();
  136. return index;
  137. }
  138. /*
  139. * For each cpu, setup the broadcast timer because local timers
  140. * stops for the states above C1.
  141. */
  142. static void omap_setup_broadcast_timer(void *arg)
  143. {
  144. int cpu = smp_processor_id();
  145. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
  146. }
  147. static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
  148. static struct cpuidle_driver omap4_idle_driver = {
  149. .name = "omap4_idle",
  150. .owner = THIS_MODULE,
  151. .en_core_tk_irqen = 1,
  152. .states = {
  153. {
  154. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  155. .exit_latency = 2 + 2,
  156. .target_residency = 5,
  157. .flags = CPUIDLE_FLAG_TIME_VALID,
  158. .enter = omap4_enter_idle_simple,
  159. .name = "C1",
  160. .desc = "MPUSS ON"
  161. },
  162. {
  163. /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
  164. .exit_latency = 328 + 440,
  165. .target_residency = 960,
  166. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  167. .enter = omap4_enter_idle_coupled,
  168. .name = "C2",
  169. .desc = "MPUSS CSWR",
  170. },
  171. {
  172. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  173. .exit_latency = 460 + 518,
  174. .target_residency = 1100,
  175. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  176. .enter = omap4_enter_idle_coupled,
  177. .name = "C3",
  178. .desc = "MPUSS OSWR",
  179. },
  180. },
  181. .state_count = ARRAY_SIZE(omap4_idle_data),
  182. .safe_state_index = 0,
  183. };
  184. /* Public functions */
  185. /**
  186. * omap4_idle_init - Init routine for OMAP4 idle
  187. *
  188. * Registers the OMAP4 specific cpuidle driver to the cpuidle
  189. * framework with the valid set of states.
  190. */
  191. int __init omap4_idle_init(void)
  192. {
  193. struct cpuidle_device *dev;
  194. unsigned int cpu_id = 0;
  195. mpu_pd = pwrdm_lookup("mpu_pwrdm");
  196. cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
  197. cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
  198. if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
  199. return -ENODEV;
  200. cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
  201. cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
  202. if (!cpu_clkdm[0] || !cpu_clkdm[1])
  203. return -ENODEV;
  204. /* Configure the broadcast timer on each cpu */
  205. on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
  206. for_each_cpu(cpu_id, cpu_online_mask) {
  207. dev = &per_cpu(omap4_idle_dev, cpu_id);
  208. dev->cpu = cpu_id;
  209. #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
  210. dev->coupled_cpus = *cpu_online_mask;
  211. #endif
  212. cpuidle_register_driver(&omap4_idle_driver);
  213. if (cpuidle_register_device(dev)) {
  214. pr_err("%s: CPUidle register failed\n", __func__);
  215. return -EIO;
  216. }
  217. }
  218. return 0;
  219. }