time.c 4.8 KB

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  1. /*
  2. * arch/arm/mach-ks8695/time.c
  3. *
  4. * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
  5. * Copyright (C) 2006 Simtec Electronics
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #include <linux/kernel.h>
  25. #include <linux/sched.h>
  26. #include <linux/io.h>
  27. #include <linux/clockchips.h>
  28. #include <asm/mach/time.h>
  29. #include <asm/system_misc.h>
  30. #include <mach/regs-irq.h>
  31. #include "generic.h"
  32. #define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
  33. #define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
  34. #define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
  35. /*
  36. * Timer registers
  37. */
  38. #define KS8695_TMCON (0x00) /* Timer Control Register */
  39. #define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
  40. #define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
  41. #define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
  42. #define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
  43. /* Timer Control Register */
  44. #define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
  45. #define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
  46. /* Timer0 Timeout Counter Register */
  47. #define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
  48. static void ks8695_set_mode(enum clock_event_mode mode,
  49. struct clock_event_device *evt)
  50. {
  51. u32 tmcon;
  52. if (mode == CLOCK_EVT_FEAT_PERIODIC) {
  53. u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
  54. u32 half = DIV_ROUND_CLOSEST(rate, 2);
  55. /* Disable timer 1 */
  56. tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  57. tmcon &= ~TMCON_T1EN;
  58. writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  59. /* Both registers need to count down */
  60. writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
  61. writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
  62. /* Re-enable timer1 */
  63. tmcon |= TMCON_T1EN;
  64. writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  65. }
  66. }
  67. static int ks8695_set_next_event(unsigned long cycles,
  68. struct clock_event_device *evt)
  69. {
  70. u32 half = DIV_ROUND_CLOSEST(cycles, 2);
  71. u32 tmcon;
  72. /* Disable timer 1 */
  73. tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  74. tmcon &= ~TMCON_T1EN;
  75. writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  76. /* Both registers need to count down */
  77. writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
  78. writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
  79. /* Re-enable timer1 */
  80. tmcon |= TMCON_T1EN;
  81. writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  82. return 0;
  83. }
  84. static struct clock_event_device clockevent_ks8695 = {
  85. .name = "ks8695_t1tc",
  86. .rating = 300, /* Reasonably fast and accurate clock event */
  87. .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
  88. .set_next_event = ks8695_set_next_event,
  89. .set_mode = ks8695_set_mode,
  90. };
  91. /*
  92. * IRQ handler for the timer.
  93. */
  94. static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
  95. {
  96. struct clock_event_device *evt = &clockevent_ks8695;
  97. evt->event_handler(evt);
  98. return IRQ_HANDLED;
  99. }
  100. static struct irqaction ks8695_timer_irq = {
  101. .name = "ks8695_tick",
  102. .flags = IRQF_DISABLED | IRQF_TIMER,
  103. .handler = ks8695_timer_interrupt,
  104. };
  105. static void ks8695_timer_setup(void)
  106. {
  107. unsigned long tmcon;
  108. /* Disable timer 0 and 1 */
  109. tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  110. tmcon &= ~TMCON_T0EN;
  111. tmcon &= ~TMCON_T1EN;
  112. writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
  113. /*
  114. * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
  115. * (one on each counter) maximum 2*2^32, but the API will only
  116. * accept up to a 32bit full word (0xFFFFFFFFU).
  117. */
  118. clockevents_config_and_register(&clockevent_ks8695,
  119. KS8695_CLOCK_RATE, 2,
  120. 0xFFFFFFFFU);
  121. }
  122. void __init ks8695_timer_init(void)
  123. {
  124. ks8695_timer_setup();
  125. /* Enable timer interrupts */
  126. setup_irq(KS8695_IRQ_TIMER1, &ks8695_timer_irq);
  127. }
  128. void ks8695_restart(char mode, const char *cmd)
  129. {
  130. unsigned int reg;
  131. if (mode == 's')
  132. soft_restart(0);
  133. /* disable timer0 */
  134. reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
  135. writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
  136. /* enable watchdog mode */
  137. writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
  138. /* re-enable timer0 */
  139. writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
  140. }