cpu-imx5.c 2.2 KB

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  1. /*
  2. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. *
  11. * This file contains the CPU initialization code.
  12. */
  13. #include <linux/types.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/io.h>
  18. #include "hardware.h"
  19. static int mx5_cpu_rev = -1;
  20. #define IIM_SREV 0x24
  21. static int get_mx51_srev(void)
  22. {
  23. void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
  24. u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  25. switch (rev) {
  26. case 0x0:
  27. return IMX_CHIP_REVISION_2_0;
  28. case 0x10:
  29. return IMX_CHIP_REVISION_3_0;
  30. default:
  31. return IMX_CHIP_REVISION_UNKNOWN;
  32. }
  33. }
  34. /*
  35. * Returns:
  36. * the silicon revision of the cpu
  37. * -EINVAL - not a mx51
  38. */
  39. int mx51_revision(void)
  40. {
  41. if (!cpu_is_mx51())
  42. return -EINVAL;
  43. if (mx5_cpu_rev == -1)
  44. mx5_cpu_rev = get_mx51_srev();
  45. return mx5_cpu_rev;
  46. }
  47. EXPORT_SYMBOL(mx51_revision);
  48. #ifdef CONFIG_NEON
  49. /*
  50. * All versions of the silicon before Rev. 3 have broken NEON implementations.
  51. * Dependent on link order - so the assumption is that vfp_init is called
  52. * before us.
  53. */
  54. int __init mx51_neon_fixup(void)
  55. {
  56. if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
  57. (elf_hwcap & HWCAP_NEON)) {
  58. elf_hwcap &= ~HWCAP_NEON;
  59. pr_info("Turning off NEON support, detected broken NEON implementation\n");
  60. }
  61. return 0;
  62. }
  63. #endif
  64. static int get_mx53_srev(void)
  65. {
  66. void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
  67. u32 rev = readl(iim_base + IIM_SREV) & 0xff;
  68. switch (rev) {
  69. case 0x0:
  70. return IMX_CHIP_REVISION_1_0;
  71. case 0x2:
  72. return IMX_CHIP_REVISION_2_0;
  73. case 0x3:
  74. return IMX_CHIP_REVISION_2_1;
  75. default:
  76. return IMX_CHIP_REVISION_UNKNOWN;
  77. }
  78. }
  79. /*
  80. * Returns:
  81. * the silicon revision of the cpu
  82. * -EINVAL - not a mx53
  83. */
  84. int mx53_revision(void)
  85. {
  86. if (!cpu_is_mx53())
  87. return -EINVAL;
  88. if (mx5_cpu_rev == -1)
  89. mx5_cpu_rev = get_mx53_srev();
  90. return mx5_cpu_rev;
  91. }
  92. EXPORT_SYMBOL(mx53_revision);