common.c 11 KB

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  1. /*
  2. * arch/arm/mach-dove/common.c
  3. *
  4. * Core functions for Marvell Dove 88AP510 System On Chip
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/clk-provider.h>
  11. #include <linux/clk/mvebu.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/init.h>
  14. #include <linux/of.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/platform_data/dma-mv_xor.h>
  17. #include <linux/platform_data/usb-ehci-orion.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/hardware/cache-tauros2.h>
  20. #include <asm/mach/arch.h>
  21. #include <asm/mach/map.h>
  22. #include <asm/mach/time.h>
  23. #include <mach/bridge-regs.h>
  24. #include <mach/pm.h>
  25. #include <plat/common.h>
  26. #include <plat/irq.h>
  27. #include <plat/time.h>
  28. #include "common.h"
  29. /*****************************************************************************
  30. * I/O Address Mapping
  31. ****************************************************************************/
  32. static struct map_desc dove_io_desc[] __initdata = {
  33. {
  34. .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
  35. .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
  36. .length = DOVE_SB_REGS_SIZE,
  37. .type = MT_DEVICE,
  38. }, {
  39. .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
  40. .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
  41. .length = DOVE_NB_REGS_SIZE,
  42. .type = MT_DEVICE,
  43. },
  44. };
  45. void __init dove_map_io(void)
  46. {
  47. iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
  48. }
  49. /*****************************************************************************
  50. * CLK tree
  51. ****************************************************************************/
  52. static int dove_tclk;
  53. static DEFINE_SPINLOCK(gating_lock);
  54. static struct clk *tclk;
  55. static struct clk __init *dove_register_gate(const char *name,
  56. const char *parent, u8 bit_idx)
  57. {
  58. return clk_register_gate(NULL, name, parent, 0,
  59. (void __iomem *)CLOCK_GATING_CONTROL,
  60. bit_idx, 0, &gating_lock);
  61. }
  62. static void __init dove_clk_init(void)
  63. {
  64. struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
  65. struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
  66. struct clk *xor0, *xor1, *ge, *gephy;
  67. tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
  68. dove_tclk);
  69. usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
  70. usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
  71. sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
  72. pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
  73. pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
  74. sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
  75. sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
  76. nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
  77. camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
  78. i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
  79. i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
  80. crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
  81. ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
  82. pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
  83. xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
  84. xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
  85. gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
  86. ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
  87. orion_clkdev_add(NULL, "orion_spi.0", tclk);
  88. orion_clkdev_add(NULL, "orion_spi.1", tclk);
  89. orion_clkdev_add(NULL, "orion_wdt", tclk);
  90. orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
  91. orion_clkdev_add(NULL, "orion-ehci.0", usb0);
  92. orion_clkdev_add(NULL, "orion-ehci.1", usb1);
  93. orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
  94. orion_clkdev_add(NULL, "sata_mv.0", sata);
  95. orion_clkdev_add("0", "pcie", pex0);
  96. orion_clkdev_add("1", "pcie", pex1);
  97. orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
  98. orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
  99. orion_clkdev_add(NULL, "orion_nand", nand);
  100. orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
  101. orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
  102. orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
  103. orion_clkdev_add(NULL, "mv_crypto", crypto);
  104. orion_clkdev_add(NULL, "dove-ac97", ac97);
  105. orion_clkdev_add(NULL, "dove-pdma", pdma);
  106. orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
  107. orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
  108. }
  109. /*****************************************************************************
  110. * EHCI0
  111. ****************************************************************************/
  112. void __init dove_ehci0_init(void)
  113. {
  114. orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
  115. }
  116. /*****************************************************************************
  117. * EHCI1
  118. ****************************************************************************/
  119. void __init dove_ehci1_init(void)
  120. {
  121. orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
  122. }
  123. /*****************************************************************************
  124. * GE00
  125. ****************************************************************************/
  126. void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
  127. {
  128. orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
  129. IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
  130. 1600);
  131. }
  132. /*****************************************************************************
  133. * SoC RTC
  134. ****************************************************************************/
  135. void __init dove_rtc_init(void)
  136. {
  137. orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
  138. }
  139. /*****************************************************************************
  140. * SATA
  141. ****************************************************************************/
  142. void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
  143. {
  144. orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
  145. }
  146. /*****************************************************************************
  147. * UART0
  148. ****************************************************************************/
  149. void __init dove_uart0_init(void)
  150. {
  151. orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
  152. IRQ_DOVE_UART_0, tclk);
  153. }
  154. /*****************************************************************************
  155. * UART1
  156. ****************************************************************************/
  157. void __init dove_uart1_init(void)
  158. {
  159. orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
  160. IRQ_DOVE_UART_1, tclk);
  161. }
  162. /*****************************************************************************
  163. * UART2
  164. ****************************************************************************/
  165. void __init dove_uart2_init(void)
  166. {
  167. orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
  168. IRQ_DOVE_UART_2, tclk);
  169. }
  170. /*****************************************************************************
  171. * UART3
  172. ****************************************************************************/
  173. void __init dove_uart3_init(void)
  174. {
  175. orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
  176. IRQ_DOVE_UART_3, tclk);
  177. }
  178. /*****************************************************************************
  179. * SPI
  180. ****************************************************************************/
  181. void __init dove_spi0_init(void)
  182. {
  183. orion_spi_init(DOVE_SPI0_PHYS_BASE);
  184. }
  185. void __init dove_spi1_init(void)
  186. {
  187. orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
  188. }
  189. /*****************************************************************************
  190. * I2C
  191. ****************************************************************************/
  192. void __init dove_i2c_init(void)
  193. {
  194. orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
  195. }
  196. /*****************************************************************************
  197. * Time handling
  198. ****************************************************************************/
  199. void __init dove_init_early(void)
  200. {
  201. orion_time_set_base(TIMER_VIRT_BASE);
  202. }
  203. static int __init dove_find_tclk(void)
  204. {
  205. return 166666667;
  206. }
  207. void __init dove_timer_init(void)
  208. {
  209. dove_tclk = dove_find_tclk();
  210. orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
  211. IRQ_DOVE_BRIDGE, dove_tclk);
  212. }
  213. /*****************************************************************************
  214. * Cryptographic Engines and Security Accelerator (CESA)
  215. ****************************************************************************/
  216. void __init dove_crypto_init(void)
  217. {
  218. orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
  219. DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
  220. }
  221. /*****************************************************************************
  222. * XOR 0
  223. ****************************************************************************/
  224. void __init dove_xor0_init(void)
  225. {
  226. orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
  227. IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
  228. }
  229. /*****************************************************************************
  230. * XOR 1
  231. ****************************************************************************/
  232. void __init dove_xor1_init(void)
  233. {
  234. orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
  235. IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
  236. }
  237. /*****************************************************************************
  238. * SDIO
  239. ****************************************************************************/
  240. static u64 sdio_dmamask = DMA_BIT_MASK(32);
  241. static struct resource dove_sdio0_resources[] = {
  242. {
  243. .start = DOVE_SDIO0_PHYS_BASE,
  244. .end = DOVE_SDIO0_PHYS_BASE + 0xff,
  245. .flags = IORESOURCE_MEM,
  246. }, {
  247. .start = IRQ_DOVE_SDIO0,
  248. .end = IRQ_DOVE_SDIO0,
  249. .flags = IORESOURCE_IRQ,
  250. },
  251. };
  252. static struct platform_device dove_sdio0 = {
  253. .name = "sdhci-dove",
  254. .id = 0,
  255. .dev = {
  256. .dma_mask = &sdio_dmamask,
  257. .coherent_dma_mask = DMA_BIT_MASK(32),
  258. },
  259. .resource = dove_sdio0_resources,
  260. .num_resources = ARRAY_SIZE(dove_sdio0_resources),
  261. };
  262. void __init dove_sdio0_init(void)
  263. {
  264. platform_device_register(&dove_sdio0);
  265. }
  266. static struct resource dove_sdio1_resources[] = {
  267. {
  268. .start = DOVE_SDIO1_PHYS_BASE,
  269. .end = DOVE_SDIO1_PHYS_BASE + 0xff,
  270. .flags = IORESOURCE_MEM,
  271. }, {
  272. .start = IRQ_DOVE_SDIO1,
  273. .end = IRQ_DOVE_SDIO1,
  274. .flags = IORESOURCE_IRQ,
  275. },
  276. };
  277. static struct platform_device dove_sdio1 = {
  278. .name = "sdhci-dove",
  279. .id = 1,
  280. .dev = {
  281. .dma_mask = &sdio_dmamask,
  282. .coherent_dma_mask = DMA_BIT_MASK(32),
  283. },
  284. .resource = dove_sdio1_resources,
  285. .num_resources = ARRAY_SIZE(dove_sdio1_resources),
  286. };
  287. void __init dove_sdio1_init(void)
  288. {
  289. platform_device_register(&dove_sdio1);
  290. }
  291. void __init dove_init(void)
  292. {
  293. pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
  294. (dove_tclk + 499999) / 1000000);
  295. #ifdef CONFIG_CACHE_TAUROS2
  296. tauros2_init(0);
  297. #endif
  298. dove_setup_cpu_mbus();
  299. /* Setup root of clk tree */
  300. dove_clk_init();
  301. /* internal devices that every board has */
  302. dove_rtc_init();
  303. dove_xor0_init();
  304. dove_xor1_init();
  305. }
  306. void dove_restart(char mode, const char *cmd)
  307. {
  308. /*
  309. * Enable soft reset to assert RSTOUTn.
  310. */
  311. writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
  312. /*
  313. * Assert soft reset.
  314. */
  315. writel(SOFT_RESET, SYSTEM_SOFT_RESET);
  316. while (1)
  317. ;
  318. }