tegra20-trimslice.dts 7.4 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "Compulab TrimSlice board";
  5. compatible = "compulab,trimslice", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
  16. };
  17. };
  18. pinmux {
  19. pinctrl-names = "default";
  20. pinctrl-0 = <&state_default>;
  21. state_default: pinmux {
  22. ata {
  23. nvidia,pins = "ata";
  24. nvidia,function = "ide";
  25. };
  26. atb {
  27. nvidia,pins = "atb", "gma";
  28. nvidia,function = "sdio4";
  29. };
  30. atc {
  31. nvidia,pins = "atc", "gmb";
  32. nvidia,function = "nand";
  33. };
  34. atd {
  35. nvidia,pins = "atd", "ate", "gme", "pta";
  36. nvidia,function = "gmi";
  37. };
  38. cdev1 {
  39. nvidia,pins = "cdev1";
  40. nvidia,function = "plla_out";
  41. };
  42. cdev2 {
  43. nvidia,pins = "cdev2";
  44. nvidia,function = "pllp_out4";
  45. };
  46. crtp {
  47. nvidia,pins = "crtp";
  48. nvidia,function = "crt";
  49. };
  50. csus {
  51. nvidia,pins = "csus";
  52. nvidia,function = "vi_sensor_clk";
  53. };
  54. dap1 {
  55. nvidia,pins = "dap1";
  56. nvidia,function = "dap1";
  57. };
  58. dap2 {
  59. nvidia,pins = "dap2";
  60. nvidia,function = "dap2";
  61. };
  62. dap3 {
  63. nvidia,pins = "dap3";
  64. nvidia,function = "dap3";
  65. };
  66. dap4 {
  67. nvidia,pins = "dap4";
  68. nvidia,function = "dap4";
  69. };
  70. ddc {
  71. nvidia,pins = "ddc";
  72. nvidia,function = "i2c2";
  73. };
  74. dta {
  75. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  76. nvidia,function = "vi";
  77. };
  78. dtf {
  79. nvidia,pins = "dtf";
  80. nvidia,function = "i2c3";
  81. };
  82. gmc {
  83. nvidia,pins = "gmc", "gmd";
  84. nvidia,function = "sflash";
  85. };
  86. gpu {
  87. nvidia,pins = "gpu";
  88. nvidia,function = "uarta";
  89. };
  90. gpu7 {
  91. nvidia,pins = "gpu7";
  92. nvidia,function = "rtck";
  93. };
  94. gpv {
  95. nvidia,pins = "gpv", "slxa", "slxk";
  96. nvidia,function = "pcie";
  97. };
  98. hdint {
  99. nvidia,pins = "hdint";
  100. nvidia,function = "hdmi";
  101. };
  102. i2cp {
  103. nvidia,pins = "i2cp";
  104. nvidia,function = "i2cp";
  105. };
  106. irrx {
  107. nvidia,pins = "irrx", "irtx";
  108. nvidia,function = "uartb";
  109. };
  110. kbca {
  111. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  112. "kbce", "kbcf";
  113. nvidia,function = "kbc";
  114. };
  115. lcsn {
  116. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  117. "ld3", "ld4", "ld5", "ld6", "ld7",
  118. "ld8", "ld9", "ld10", "ld11", "ld12",
  119. "ld13", "ld14", "ld15", "ld16", "ld17",
  120. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  121. "lhs", "lm0", "lm1", "lpp", "lpw0",
  122. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  123. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  124. "lvs";
  125. nvidia,function = "displaya";
  126. };
  127. owc {
  128. nvidia,pins = "owc", "uac";
  129. nvidia,function = "rsvd2";
  130. };
  131. pmc {
  132. nvidia,pins = "pmc";
  133. nvidia,function = "pwr_on";
  134. };
  135. rm {
  136. nvidia,pins = "rm";
  137. nvidia,function = "i2c1";
  138. };
  139. sdb {
  140. nvidia,pins = "sdb", "sdc", "sdd";
  141. nvidia,function = "pwm";
  142. };
  143. sdio1 {
  144. nvidia,pins = "sdio1";
  145. nvidia,function = "sdio1";
  146. };
  147. slxc {
  148. nvidia,pins = "slxc", "slxd";
  149. nvidia,function = "sdio3";
  150. };
  151. spdi {
  152. nvidia,pins = "spdi", "spdo";
  153. nvidia,function = "spdif";
  154. };
  155. spia {
  156. nvidia,pins = "spia", "spib", "spic";
  157. nvidia,function = "spi2";
  158. };
  159. spid {
  160. nvidia,pins = "spid", "spie", "spif";
  161. nvidia,function = "spi1";
  162. };
  163. spig {
  164. nvidia,pins = "spig", "spih";
  165. nvidia,function = "spi2_alt";
  166. };
  167. uaa {
  168. nvidia,pins = "uaa", "uab", "uda";
  169. nvidia,function = "ulpi";
  170. };
  171. uad {
  172. nvidia,pins = "uad";
  173. nvidia,function = "irda";
  174. };
  175. uca {
  176. nvidia,pins = "uca", "ucb";
  177. nvidia,function = "uartc";
  178. };
  179. conf_ata {
  180. nvidia,pins = "ata", "atc", "atd", "ate",
  181. "crtp", "dap2", "dap3", "dap4", "dta",
  182. "dtb", "dtc", "dtd", "dte", "gmb",
  183. "gme", "i2cp", "pta", "slxc", "slxd",
  184. "spdi", "spdo", "uda";
  185. nvidia,pull = <0>;
  186. nvidia,tristate = <1>;
  187. };
  188. conf_atb {
  189. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  190. "gma", "gmc", "gmd", "gpu", "gpu7",
  191. "gpv", "sdio1", "slxa", "slxk", "uac";
  192. nvidia,pull = <0>;
  193. nvidia,tristate = <0>;
  194. };
  195. conf_ck32 {
  196. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  197. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  198. nvidia,pull = <0>;
  199. };
  200. conf_csus {
  201. nvidia,pins = "csus", "spia", "spib",
  202. "spid", "spif";
  203. nvidia,pull = <1>;
  204. nvidia,tristate = <1>;
  205. };
  206. conf_ddc {
  207. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  208. nvidia,pull = <2>;
  209. nvidia,tristate = <0>;
  210. };
  211. conf_hdint {
  212. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  213. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  214. "lvp0", "pmc";
  215. nvidia,tristate = <1>;
  216. };
  217. conf_irrx {
  218. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  219. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  220. "spic", "spie", "spig", "spih", "uaa",
  221. "uab", "uad", "uca", "ucb";
  222. nvidia,pull = <2>;
  223. nvidia,tristate = <1>;
  224. };
  225. conf_lc {
  226. nvidia,pins = "lc", "ls";
  227. nvidia,pull = <2>;
  228. };
  229. conf_ld0 {
  230. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  231. "ld5", "ld6", "ld7", "ld8", "ld9",
  232. "ld10", "ld11", "ld12", "ld13", "ld14",
  233. "ld15", "ld16", "ld17", "ldi", "lhp0",
  234. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  235. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  236. "lvs", "sdb";
  237. nvidia,tristate = <0>;
  238. };
  239. conf_ld17_0 {
  240. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  241. "ld23_22";
  242. nvidia,pull = <1>;
  243. };
  244. conf_spif {
  245. nvidia,pins = "spif";
  246. nvidia,pull = <1>;
  247. nvidia,tristate = <0>;
  248. };
  249. };
  250. };
  251. i2s@70002800 {
  252. status = "okay";
  253. };
  254. serial@70006000 {
  255. status = "okay";
  256. };
  257. dvi_ddc: i2c@7000c000 {
  258. status = "okay";
  259. clock-frequency = <100000>;
  260. };
  261. spi@7000c380 {
  262. status = "okay";
  263. spi-max-frequency = <48000000>;
  264. spi-flash@0 {
  265. compatible = "winbond,w25q80bl";
  266. reg = <0>;
  267. spi-max-frequency = <48000000>;
  268. };
  269. };
  270. hdmi_ddc: i2c@7000c400 {
  271. status = "okay";
  272. clock-frequency = <100000>;
  273. };
  274. i2c@7000c500 {
  275. status = "okay";
  276. clock-frequency = <400000>;
  277. codec: codec@1a {
  278. compatible = "ti,tlv320aic23";
  279. reg = <0x1a>;
  280. };
  281. rtc@56 {
  282. compatible = "emmicro,em3027";
  283. reg = <0x56>;
  284. };
  285. };
  286. usb@c5000000 {
  287. status = "okay";
  288. nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
  289. };
  290. usb@c5004000 {
  291. status = "okay";
  292. nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
  293. };
  294. usb@c5008000 {
  295. status = "okay";
  296. };
  297. usb-phy@c5004400 {
  298. nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
  299. };
  300. sdhci@c8000000 {
  301. status = "okay";
  302. bus-width = <4>;
  303. };
  304. sdhci@c8000600 {
  305. status = "okay";
  306. cd-gpios = <&gpio 121 0>; /* gpio PP1 */
  307. wp-gpios = <&gpio 122 0>; /* gpio PP2 */
  308. bus-width = <4>;
  309. };
  310. poweroff {
  311. compatible = "gpio-poweroff";
  312. gpios = <&gpio 191 1>; /* gpio PX7, active low */
  313. };
  314. regulators {
  315. compatible = "simple-bus";
  316. #address-cells = <1>;
  317. #size-cells = <0>;
  318. hdmi_vdd_reg: regulator@0 {
  319. compatible = "regulator-fixed";
  320. reg = <0>;
  321. regulator-name = "avdd_hdmi";
  322. regulator-min-microvolt = <3300000>;
  323. regulator-max-microvolt = <3300000>;
  324. regulator-always-on;
  325. };
  326. hdmi_pll_reg: regulator@1 {
  327. compatible = "regulator-fixed";
  328. reg = <1>;
  329. regulator-name = "avdd_hdmi_pll";
  330. regulator-min-microvolt = <1800000>;
  331. regulator-max-microvolt = <1800000>;
  332. regulator-always-on;
  333. };
  334. };
  335. sound {
  336. compatible = "nvidia,tegra-audio-trimslice";
  337. nvidia,i2s-controller = <&tegra_i2s1>;
  338. nvidia,audio-codec = <&codec>;
  339. };
  340. };