at91sam9260.dtsi 13 KB

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  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. model = "Atmel AT91SAM9260 family SoC";
  13. compatible = "atmel,at91sam9260";
  14. interrupt-parent = <&aic>;
  15. aliases {
  16. serial0 = &dbgu;
  17. serial1 = &usart0;
  18. serial2 = &usart1;
  19. serial3 = &usart2;
  20. serial4 = &usart3;
  21. serial5 = &uart0;
  22. serial6 = &uart1;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. tcb0 = &tcb0;
  27. tcb1 = &tcb1;
  28. i2c0 = &i2c0;
  29. ssc0 = &ssc0;
  30. };
  31. cpus {
  32. cpu@0 {
  33. compatible = "arm,arm926ejs";
  34. };
  35. };
  36. memory {
  37. reg = <0x20000000 0x04000000>;
  38. };
  39. ahb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. apb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. aic: interrupt-controller@fffff000 {
  50. #interrupt-cells = <3>;
  51. compatible = "atmel,at91rm9200-aic";
  52. interrupt-controller;
  53. reg = <0xfffff000 0x200>;
  54. atmel,external-irqs = <29 30 31>;
  55. };
  56. ramc0: ramc@ffffea00 {
  57. compatible = "atmel,at91sam9260-sdramc";
  58. reg = <0xffffea00 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffd00 {
  65. compatible = "atmel,at91sam9260-rstc";
  66. reg = <0xfffffd00 0x10>;
  67. };
  68. shdwc@fffffd10 {
  69. compatible = "atmel,at91sam9260-shdwc";
  70. reg = <0xfffffd10 0x10>;
  71. };
  72. pit: timer@fffffd30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffd30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. tcb0: timer@fffa0000 {
  78. compatible = "atmel,at91rm9200-tcb";
  79. reg = <0xfffa0000 0x100>;
  80. interrupts = <17 4 0 18 4 0 19 4 0>;
  81. };
  82. tcb1: timer@fffdc000 {
  83. compatible = "atmel,at91rm9200-tcb";
  84. reg = <0xfffdc000 0x100>;
  85. interrupts = <26 4 0 27 4 0 28 4 0>;
  86. };
  87. pinctrl@fffff400 {
  88. #address-cells = <1>;
  89. #size-cells = <1>;
  90. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  91. ranges = <0xfffff400 0xfffff400 0x600>;
  92. atmel,mux-mask = <
  93. /* A B */
  94. 0xffffffff 0xffc00c3b /* pioA */
  95. 0xffffffff 0x7fff3ccf /* pioB */
  96. 0xffffffff 0x007fffff /* pioC */
  97. >;
  98. /* shared pinctrl settings */
  99. dbgu {
  100. pinctrl_dbgu: dbgu-0 {
  101. atmel,pins =
  102. <1 14 0x1 0x0 /* PB14 periph A */
  103. 1 15 0x1 0x1>; /* PB15 periph with pullup */
  104. };
  105. };
  106. usart0 {
  107. pinctrl_usart0: usart0-0 {
  108. atmel,pins =
  109. <1 4 0x1 0x0 /* PB4 periph A */
  110. 1 5 0x1 0x0>; /* PB5 periph A */
  111. };
  112. pinctrl_usart0_rts: usart0_rts-0 {
  113. atmel,pins =
  114. <1 26 0x1 0x0>; /* PB26 periph A */
  115. };
  116. pinctrl_usart0_cts: usart0_cts-0 {
  117. atmel,pins =
  118. <1 27 0x1 0x0>; /* PB27 periph A */
  119. };
  120. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  121. atmel,pins =
  122. <1 24 0x1 0x0 /* PB24 periph A */
  123. 1 22 0x1 0x0>; /* PB22 periph A */
  124. };
  125. pinctrl_usart0_dcd: usart0_dcd-0 {
  126. atmel,pins =
  127. <1 23 0x1 0x0>; /* PB23 periph A */
  128. };
  129. pinctrl_usart0_ri: usart0_ri-0 {
  130. atmel,pins =
  131. <1 25 0x1 0x0>; /* PB25 periph A */
  132. };
  133. };
  134. usart1 {
  135. pinctrl_usart1: usart1-0 {
  136. atmel,pins =
  137. <2 6 0x1 0x1 /* PB6 periph A with pullup */
  138. 2 7 0x1 0x0>; /* PB7 periph A */
  139. };
  140. pinctrl_usart1_rts: usart1_rts-0 {
  141. atmel,pins =
  142. <1 28 0x1 0x0>; /* PB28 periph A */
  143. };
  144. pinctrl_usart1_cts: usart1_cts-0 {
  145. atmel,pins =
  146. <1 29 0x1 0x0>; /* PB29 periph A */
  147. };
  148. };
  149. usart2 {
  150. pinctrl_usart2: usart2-0 {
  151. atmel,pins =
  152. <1 8 0x1 0x1 /* PB8 periph A with pullup */
  153. 1 9 0x1 0x0>; /* PB9 periph A */
  154. };
  155. pinctrl_usart2_rts: usart2_rts-0 {
  156. atmel,pins =
  157. <0 4 0x1 0x0>; /* PA4 periph A */
  158. };
  159. pinctrl_usart2_cts: usart2_cts-0 {
  160. atmel,pins =
  161. <0 5 0x1 0x0>; /* PA5 periph A */
  162. };
  163. };
  164. usart3 {
  165. pinctrl_usart3: usart3-0 {
  166. atmel,pins =
  167. <2 10 0x1 0x1 /* PB10 periph A with pullup */
  168. 2 11 0x1 0x0>; /* PB11 periph A */
  169. };
  170. pinctrl_usart3_rts: usart3_rts-0 {
  171. atmel,pins =
  172. <3 8 0x2 0x0>; /* PB8 periph B */
  173. };
  174. pinctrl_usart3_cts: usart3_cts-0 {
  175. atmel,pins =
  176. <3 10 0x2 0x0>; /* PB10 periph B */
  177. };
  178. };
  179. uart0 {
  180. pinctrl_uart0: uart0-0 {
  181. atmel,pins =
  182. <0 31 0x2 0x1 /* PA31 periph B with pullup */
  183. 0 30 0x2 0x0>; /* PA30 periph B */
  184. };
  185. };
  186. uart1 {
  187. pinctrl_uart1: uart1-0 {
  188. atmel,pins =
  189. <2 12 0x1 0x1 /* PB12 periph A with pullup */
  190. 2 13 0x1 0x0>; /* PB13 periph A */
  191. };
  192. };
  193. nand {
  194. pinctrl_nand: nand-0 {
  195. atmel,pins =
  196. <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
  197. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  198. };
  199. };
  200. macb {
  201. pinctrl_macb_rmii: macb_rmii-0 {
  202. atmel,pins =
  203. <0 12 0x1 0x0 /* PA12 periph A */
  204. 0 13 0x1 0x0 /* PA13 periph A */
  205. 0 14 0x1 0x0 /* PA14 periph A */
  206. 0 15 0x1 0x0 /* PA15 periph A */
  207. 0 16 0x1 0x0 /* PA16 periph A */
  208. 0 17 0x1 0x0 /* PA17 periph A */
  209. 0 18 0x1 0x0 /* PA18 periph A */
  210. 0 19 0x1 0x0 /* PA19 periph A */
  211. 0 20 0x1 0x0 /* PA20 periph A */
  212. 0 21 0x1 0x0>; /* PA21 periph A */
  213. };
  214. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  215. atmel,pins =
  216. <0 22 0x2 0x0 /* PA22 periph B */
  217. 0 23 0x2 0x0 /* PA23 periph B */
  218. 0 24 0x2 0x0 /* PA24 periph B */
  219. 0 25 0x2 0x0 /* PA25 periph B */
  220. 0 26 0x2 0x0 /* PA26 periph B */
  221. 0 27 0x2 0x0 /* PA27 periph B */
  222. 0 28 0x2 0x0 /* PA28 periph B */
  223. 0 29 0x2 0x0>; /* PA29 periph B */
  224. };
  225. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  226. atmel,pins =
  227. <0 10 0x2 0x0 /* PA10 periph B */
  228. 0 11 0x2 0x0 /* PA11 periph B */
  229. 0 24 0x2 0x0 /* PA24 periph B */
  230. 0 25 0x2 0x0 /* PA25 periph B */
  231. 0 26 0x2 0x0 /* PA26 periph B */
  232. 0 27 0x2 0x0 /* PA27 periph B */
  233. 0 28 0x2 0x0 /* PA28 periph B */
  234. 0 29 0x2 0x0>; /* PA29 periph B */
  235. };
  236. };
  237. mmc0 {
  238. pinctrl_mmc0_clk: mmc0_clk-0 {
  239. atmel,pins =
  240. <0 8 0x1 0x0>; /* PA8 periph A */
  241. };
  242. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  243. atmel,pins =
  244. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  245. 0 6 0x1 0x1>; /* PA6 periph A with pullup */
  246. };
  247. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  248. atmel,pins =
  249. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  250. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  251. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  252. };
  253. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  254. atmel,pins =
  255. <0 1 0x2 0x1 /* PA1 periph B with pullup */
  256. 0 0 0x2 0x1>; /* PA0 periph B with pullup */
  257. };
  258. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  259. atmel,pins =
  260. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  261. 0 4 0x2 0x1 /* PA4 periph B with pullup */
  262. 0 3 0x2 0x1>; /* PA3 periph B with pullup */
  263. };
  264. };
  265. ssc0 {
  266. pinctrl_ssc0_tx: ssc0_tx-0 {
  267. atmel,pins =
  268. <1 16 0x1 0x0 /* PB16 periph A */
  269. 1 17 0x1 0x0 /* PB17 periph A */
  270. 1 18 0x1 0x0>; /* PB18 periph A */
  271. };
  272. pinctrl_ssc0_rx: ssc0_rx-0 {
  273. atmel,pins =
  274. <1 19 0x1 0x0 /* PB19 periph A */
  275. 1 20 0x1 0x0 /* PB20 periph A */
  276. 1 21 0x1 0x0>; /* PB21 periph A */
  277. };
  278. };
  279. pioA: gpio@fffff400 {
  280. compatible = "atmel,at91rm9200-gpio";
  281. reg = <0xfffff400 0x200>;
  282. interrupts = <2 4 1>;
  283. #gpio-cells = <2>;
  284. gpio-controller;
  285. interrupt-controller;
  286. #interrupt-cells = <2>;
  287. };
  288. pioB: gpio@fffff600 {
  289. compatible = "atmel,at91rm9200-gpio";
  290. reg = <0xfffff600 0x200>;
  291. interrupts = <3 4 1>;
  292. #gpio-cells = <2>;
  293. gpio-controller;
  294. interrupt-controller;
  295. #interrupt-cells = <2>;
  296. };
  297. pioC: gpio@fffff800 {
  298. compatible = "atmel,at91rm9200-gpio";
  299. reg = <0xfffff800 0x200>;
  300. interrupts = <4 4 1>;
  301. #gpio-cells = <2>;
  302. gpio-controller;
  303. interrupt-controller;
  304. #interrupt-cells = <2>;
  305. };
  306. };
  307. dbgu: serial@fffff200 {
  308. compatible = "atmel,at91sam9260-usart";
  309. reg = <0xfffff200 0x200>;
  310. interrupts = <1 4 7>;
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_dbgu>;
  313. status = "disabled";
  314. };
  315. usart0: serial@fffb0000 {
  316. compatible = "atmel,at91sam9260-usart";
  317. reg = <0xfffb0000 0x200>;
  318. interrupts = <6 4 5>;
  319. atmel,use-dma-rx;
  320. atmel,use-dma-tx;
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_usart0>;
  323. status = "disabled";
  324. };
  325. usart1: serial@fffb4000 {
  326. compatible = "atmel,at91sam9260-usart";
  327. reg = <0xfffb4000 0x200>;
  328. interrupts = <7 4 5>;
  329. atmel,use-dma-rx;
  330. atmel,use-dma-tx;
  331. pinctrl-names = "default";
  332. pinctrl-0 = <&pinctrl_usart1>;
  333. status = "disabled";
  334. };
  335. usart2: serial@fffb8000 {
  336. compatible = "atmel,at91sam9260-usart";
  337. reg = <0xfffb8000 0x200>;
  338. interrupts = <8 4 5>;
  339. atmel,use-dma-rx;
  340. atmel,use-dma-tx;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&pinctrl_usart2>;
  343. status = "disabled";
  344. };
  345. usart3: serial@fffd0000 {
  346. compatible = "atmel,at91sam9260-usart";
  347. reg = <0xfffd0000 0x200>;
  348. interrupts = <23 4 5>;
  349. atmel,use-dma-rx;
  350. atmel,use-dma-tx;
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_usart3>;
  353. status = "disabled";
  354. };
  355. uart0: serial@fffd4000 {
  356. compatible = "atmel,at91sam9260-usart";
  357. reg = <0xfffd4000 0x200>;
  358. interrupts = <24 4 5>;
  359. atmel,use-dma-rx;
  360. atmel,use-dma-tx;
  361. pinctrl-names = "default";
  362. pinctrl-0 = <&pinctrl_uart0>;
  363. status = "disabled";
  364. };
  365. uart1: serial@fffd8000 {
  366. compatible = "atmel,at91sam9260-usart";
  367. reg = <0xfffd8000 0x200>;
  368. interrupts = <25 4 5>;
  369. atmel,use-dma-rx;
  370. atmel,use-dma-tx;
  371. pinctrl-names = "default";
  372. pinctrl-0 = <&pinctrl_uart1>;
  373. status = "disabled";
  374. };
  375. macb0: ethernet@fffc4000 {
  376. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  377. reg = <0xfffc4000 0x100>;
  378. interrupts = <21 4 3>;
  379. pinctrl-names = "default";
  380. pinctrl-0 = <&pinctrl_macb_rmii>;
  381. status = "disabled";
  382. };
  383. usb1: gadget@fffa4000 {
  384. compatible = "atmel,at91rm9200-udc";
  385. reg = <0xfffa4000 0x4000>;
  386. interrupts = <10 4 2>;
  387. status = "disabled";
  388. };
  389. i2c0: i2c@fffac000 {
  390. compatible = "atmel,at91sam9260-i2c";
  391. reg = <0xfffac000 0x100>;
  392. interrupts = <11 4 6>;
  393. #address-cells = <1>;
  394. #size-cells = <0>;
  395. status = "disabled";
  396. };
  397. mmc0: mmc@fffa8000 {
  398. compatible = "atmel,hsmci";
  399. reg = <0xfffa8000 0x600>;
  400. interrupts = <9 4 0>;
  401. #address-cells = <1>;
  402. #size-cells = <0>;
  403. status = "disabled";
  404. };
  405. ssc0: ssc@fffbc000 {
  406. compatible = "atmel,at91rm9200-ssc";
  407. reg = <0xfffbc000 0x4000>;
  408. interrupts = <14 4 5>;
  409. pinctrl-names = "default";
  410. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  411. status = "disabled";
  412. };
  413. adc0: adc@fffe0000 {
  414. compatible = "atmel,at91sam9260-adc";
  415. reg = <0xfffe0000 0x100>;
  416. interrupts = <5 4 0>;
  417. atmel,adc-use-external-triggers;
  418. atmel,adc-channels-used = <0xf>;
  419. atmel,adc-vref = <3300>;
  420. atmel,adc-num-channels = <4>;
  421. atmel,adc-startup-time = <15>;
  422. atmel,adc-channel-base = <0x30>;
  423. atmel,adc-drdy-mask = <0x10000>;
  424. atmel,adc-status-register = <0x1c>;
  425. atmel,adc-trigger-register = <0x04>;
  426. trigger@0 {
  427. trigger-name = "timer-counter-0";
  428. trigger-value = <0x1>;
  429. };
  430. trigger@1 {
  431. trigger-name = "timer-counter-1";
  432. trigger-value = <0x3>;
  433. };
  434. trigger@2 {
  435. trigger-name = "timer-counter-2";
  436. trigger-value = <0x5>;
  437. };
  438. trigger@3 {
  439. trigger-name = "external";
  440. trigger-value = <0x13>;
  441. trigger-external;
  442. };
  443. };
  444. watchdog@fffffd40 {
  445. compatible = "atmel,at91sam9260-wdt";
  446. reg = <0xfffffd40 0x10>;
  447. status = "disabled";
  448. };
  449. };
  450. nand0: nand@40000000 {
  451. compatible = "atmel,at91rm9200-nand";
  452. #address-cells = <1>;
  453. #size-cells = <1>;
  454. reg = <0x40000000 0x10000000
  455. 0xffffe800 0x200
  456. >;
  457. atmel,nand-addr-offset = <21>;
  458. atmel,nand-cmd-offset = <22>;
  459. pinctrl-names = "default";
  460. pinctrl-0 = <&pinctrl_nand>;
  461. gpios = <&pioC 13 0
  462. &pioC 14 0
  463. 0
  464. >;
  465. status = "disabled";
  466. };
  467. usb0: ohci@00500000 {
  468. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  469. reg = <0x00500000 0x100000>;
  470. interrupts = <20 4 2>;
  471. status = "disabled";
  472. };
  473. };
  474. i2c@0 {
  475. compatible = "i2c-gpio";
  476. gpios = <&pioA 23 0 /* sda */
  477. &pioA 24 0 /* scl */
  478. >;
  479. i2c-gpio,sda-open-drain;
  480. i2c-gpio,scl-open-drain;
  481. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  482. #address-cells = <1>;
  483. #size-cells = <0>;
  484. status = "disabled";
  485. };
  486. };