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- #
- # Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
- #
- # This program is free software; you can redistribute it and/or modify
- # it under the terms of the GNU General Public License version 2 as
- # published by the Free Software Foundation.
- #
- menuconfig ARC_PLAT_FPGA_LEGACY
- bool "\"Legacy\" ARC FPGA dev Boards"
- select ISS_SMP_EXTN if SMP
- help
- Support for ARC development boards, provided by Synopsys.
- These are based on FPGA or ISS. e.g.
- - ARCAngel4
- - ML509
- - MetaWare ISS
- if ARC_PLAT_FPGA_LEGACY
- config ARC_BOARD_ANGEL4
- bool "ARC Angel4"
- default y
- help
- ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based)
- config ARC_BOARD_ML509
- bool "ML509"
- help
- ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based)
- config ISS_SMP_EXTN
- bool "ARC SMP Extensions (ISS Models only)"
- default n
- depends on SMP
- select ARC_HAS_COH_RTSC
- help
- SMP Extensions to ARC700, in a "simulation only" Model, supported in
- ARC ISS (Instruction Set Simulator).
- The SMP extensions include:
- -IDU (Interrupt Distribution Unit)
- -XTL (To enable CPU start/stop/set-PC for another CPU)
- It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND)
- config ARC_SERIAL_BAUD
- int "UART Baud rate"
- default "115200"
- depends on SERIAL_ARC || SERIAL_ARC_CONSOLE
- help
- Baud rate for the ARC UART
- menuconfig ARC_HAS_BVCI_LAT_UNIT
- bool "BVCI Bus Latency Unit"
- depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
- help
- IP to add artifical latency to BVCI Bus Based FPGA builds.
- The default latency (even worst case) for FPGA is non-realistic
- (~10 SDRAM, ~5 SSRAM).
- config BVCI_LAT_UNITS
- hex "Latency Unit(s) Bitmap"
- default "0x0"
- depends on ARC_HAS_BVCI_LAT_UNIT
- help
- There are multiple Latency Units corresponding to the many
- interfaces of the system bus arbiter (both CPU side as well as
- the peripheral side).
- To add latency to ALL memory transaction, choose Unit 0, otherwise
- for finer grainer - interface wise latency, specify a bitmap (1 bit
- per unit) of all units. e.g. 1,2,12 will be 0x1003
- Unit 0 - System Arb and Mem Controller
- Unit 1 - I$ and System Bus
- Unit 2 - D$ and System Bus
- ..
- Unit 12 - IDE Disk controller and System Bus
- config BVCI_LAT_CYCLES
- int "Latency Value in cycles"
- range 0 63
- default "30"
- depends on ARC_HAS_BVCI_LAT_UNIT
- endif
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