timer.h 1.8 KB

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  1. /*
  2. * include/asm-sh/cpu-sh3/timer.h
  3. *
  4. * Copyright (C) 2004 Lineo Solutions, Inc.
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #ifndef __ASM_CPU_SH3_TIMER_H
  11. #define __ASM_CPU_SH3_TIMER_H
  12. /*
  13. * ---------------------------------------------------------------------------
  14. * TMU Common definitions for SH3 processors
  15. * SH7706
  16. * SH7709S
  17. * SH7727
  18. * SH7729R
  19. * SH7710
  20. * SH7720
  21. * SH7300
  22. * SH7710
  23. * ---------------------------------------------------------------------------
  24. */
  25. #if !defined(CONFIG_CPU_SUBTYPE_SH7727)
  26. #define TMU_TOCR 0xfffffe90 /* Byte access */
  27. #endif
  28. #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
  29. #define TMU_TSTR 0xa412fe92 /* Byte access */
  30. #define TMU0_TCOR 0xa412fe94 /* Long access */
  31. #define TMU0_TCNT 0xa412fe98 /* Long access */
  32. #define TMU0_TCR 0xa412fe9c /* Word access */
  33. #define TMU1_TCOR 0xa412fea0 /* Long access */
  34. #define TMU1_TCNT 0xa412fea4 /* Long access */
  35. #define TMU1_TCR 0xa412fea8 /* Word access */
  36. #define TMU2_TCOR 0xa412feac /* Long access */
  37. #define TMU2_TCNT 0xa412feb0 /* Long access */
  38. #define TMU2_TCR 0xa412feb4 /* Word access */
  39. #else
  40. #define TMU_TSTR 0xfffffe92 /* Byte access */
  41. #define TMU0_TCOR 0xfffffe94 /* Long access */
  42. #define TMU0_TCNT 0xfffffe98 /* Long access */
  43. #define TMU0_TCR 0xfffffe9c /* Word access */
  44. #define TMU1_TCOR 0xfffffea0 /* Long access */
  45. #define TMU1_TCNT 0xfffffea4 /* Long access */
  46. #define TMU1_TCR 0xfffffea8 /* Word access */
  47. #define TMU2_TCOR 0xfffffeac /* Long access */
  48. #define TMU2_TCNT 0xfffffeb0 /* Long access */
  49. #define TMU2_TCR 0xfffffeb4 /* Word access */
  50. #if !defined(CONFIG_CPU_SUBTYPE_SH7727)
  51. #define TMU2_TCPR2 0xfffffeb8 /* Long access */
  52. #endif
  53. #endif
  54. #endif /* __ASM_CPU_SH3_TIMER_H */