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mappi3_pld.h

mappi3_pld.h 4.5 KB
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  1. /*
    2. 

  2.  * include/asm/mappi3/mappi3_pld.h
    3. 

  3.  *
    4. 

  4.  * Definitions for Extended IO Logic on MAPPI3 board.
    5. 

  5.  *  based on m32700ut_pld.h
    6. 

  6.  *
    7. 

  7.  * This file is subject to the terms and conditions of the GNU General
    8. 

  8.  * Public License.  See the file "COPYING" in the main directory of
    9. 

  9.  * this archive for more details.
    10. 

  10.  *
    11. 

  11.  */
    12. 

  12. 

  13. #ifndef _MAPPI3_PLD_H
    14. 

  14. #define _MAPPI3_PLD_H
    15. 

  15. 

  16. #ifndef __ASSEMBLY__
    17. 

  17. /* FIXME:
    18. 

  18.  * Some C functions use non-cache address, so can't define non-cache address.
    19. 

  19.  */
    20. 

  20. #define PLD_BASE		(0x1c000000 /* + NONCACHE_OFFSET */)
    21. 

  21. #define __reg8			(volatile unsigned char *)
    22. 

  22. #define __reg16			(volatile unsigned short *)
    23. 

  23. #define __reg32			(volatile unsigned int *)
    24. 

  24. #else
    25. 

  25. #define PLD_BASE		(0x1c000000 + NONCACHE_OFFSET)
    26. 

  26. #define __reg8
    27. 

  27. #define __reg16
    28. 

  28. #define __reg32
    29. 

  29. #endif	/* __ASSEMBLY__ */
    30. 

  30. 

  31. /* CFC */
    32. 

  32. #define	PLD_CFRSTCR		__reg16(PLD_BASE + 0x0000)
    33. 

  33. #define PLD_CFSTS		__reg16(PLD_BASE + 0x0002)
    34. 

  34. #define PLD_CFIMASK		__reg16(PLD_BASE + 0x0004)
    35. 

  35. #define PLD_CFBUFCR		__reg16(PLD_BASE + 0x0006)
    36. 

  36. #define PLD_CFCR0		__reg16(PLD_BASE + 0x000a)
    37. 

  37. #define PLD_CFCR1		__reg16(PLD_BASE + 0x000c)
    38. 

  38. 

  39. /* MMC */
    40. 

  40. #define PLD_MMCCR		__reg16(PLD_BASE + 0x4000)
    41. 

  41. #define PLD_MMCMOD		__reg16(PLD_BASE + 0x4002)
    42. 

  42. #define PLD_MMCSTS		__reg16(PLD_BASE + 0x4006)
    43. 

  43. #define PLD_MMCBAUR		__reg16(PLD_BASE + 0x400a)
    44. 

  44. #define PLD_MMCCMDBCUT		__reg16(PLD_BASE + 0x400c)
    45. 

  45. #define PLD_MMCCDTBCUT		__reg16(PLD_BASE + 0x400e)
    46. 

  46. #define PLD_MMCDET		__reg16(PLD_BASE + 0x4010)
    47. 

  47. #define PLD_MMCWP		__reg16(PLD_BASE + 0x4012)
    48. 

  48. #define PLD_MMCWDATA		__reg16(PLD_BASE + 0x5000)
    49. 

  49. #define PLD_MMCRDATA		__reg16(PLD_BASE + 0x6000)
    50. 

  50. #define PLD_MMCCMDDATA		__reg16(PLD_BASE + 0x7000)
    51. 

  51. #define PLD_MMCRSPDATA		__reg16(PLD_BASE + 0x7006)
    52. 

  52. 

  53. /* Power Control of MMC and CF */
    54. 

  54. #define PLD_CPCR		__reg16(PLD_BASE + 0x14000)
    55. 

  55. 

  56. /* ICU */
    57. 

  57. #define M32R_IRQ_PC104		(5)	/* INT4(PC/104) */
    58. 

  58. #define M32R_IRQ_I2C		(28)	/* I2C-BUS */
    59. 

  59. #define PLD_IRQ_CFIREQ		(6)	/* INT5 CFC Card Interrupt */
    60. 

  60. #define PLD_IRQ_CFC_INSERT	(7)	/* INT6 CFC Card Insert & Eject */
    61. 

  61. #define PLD_IRQ_IDEIREQ		(8)	/* INT7 IDE Interrupt */
    62. 

  62. #define PLD_IRQ_MMCCARD		(43)	/* MMC Card Insert */
    63. 

  63. #define PLD_IRQ_MMCIRQ		(44)	/* MMC Transfer Done */
    64. 

  64. 

  65. #if 0
    66. 

  66. /* LED Control
    67. 

  67.  *
    68. 

  68.  * 1: DIP swich side
    69. 

  69.  * 2: Reset switch side
    70. 

  70.  */
    71. 

  71. #define PLD_IOLEDCR		__reg16(PLD_BASE + 0x14002)
    72. 

  72. #define PLD_IOLED_1_ON		0x001
    73. 

  73. #define PLD_IOLED_1_OFF		0x000
    74. 

  74. #define PLD_IOLED_2_ON		0x002
    75. 

  75. #define PLD_IOLED_2_OFF		0x000
    76. 

  76. 

  77. /* DIP Switch
    78. 

  78.  *  0: Write-protect of Flash Memory (0:protected, 1:non-protected)
    79. 

  79.  *  1: -
    80. 

  80.  *  2: -
    81. 

  81.  *  3: -
    82. 

  82.  */
    83. 

  83. #define PLD_IOSWSTS		__reg16(PLD_BASE + 0x14004)
    84. 

  84. #define	PLD_IOSWSTS_IOSW2	0x0200
    85. 

  85. #define	PLD_IOSWSTS_IOSW1	0x0100
    86. 

  86. #define	PLD_IOSWSTS_IOWP0	0x0001
    87. 

  87. 

  88. #endif
    89. 

  89. 

  90. /* CRC */
    91. 

  91. #define PLD_CRC7DATA		__reg16(PLD_BASE + 0x18000)
    92. 

  92. #define PLD_CRC7INDATA		__reg16(PLD_BASE + 0x18002)
    93. 

  93. #define PLD_CRC16DATA		__reg16(PLD_BASE + 0x18004)
    94. 

  94. #define PLD_CRC16INDATA		__reg16(PLD_BASE + 0x18006)
    95. 

  95. #define PLD_CRC16ADATA		__reg16(PLD_BASE + 0x18008)
    96. 

  96. #define PLD_CRC16AINDATA	__reg16(PLD_BASE + 0x1800a)
    97. 

  97. 

  98. #if 0
    99. 

  99. /* RTC */
    100. 

  100. #define PLD_RTCCR		__reg16(PLD_BASE + 0x1c000)
    101. 

  101. #define PLD_RTCBAUR		__reg16(PLD_BASE + 0x1c002)
    102. 

  102. #define PLD_RTCWRDATA		__reg16(PLD_BASE + 0x1c004)
    103. 

  103. #define PLD_RTCRDDATA		__reg16(PLD_BASE + 0x1c006)
    104. 

  104. #define PLD_RTCRSTODT		__reg16(PLD_BASE + 0x1c008)
    105. 

  105. 

  106. /* SIO0 */
    107. 

  107. #define PLD_ESIO0CR		__reg16(PLD_BASE + 0x20000)
    108. 

  108. #define	PLD_ESIO0CR_TXEN	0x0001
    109. 

  109. #define	PLD_ESIO0CR_RXEN	0x0002
    110. 

  110. #define PLD_ESIO0MOD0		__reg16(PLD_BASE + 0x20002)
    111. 

  111. #define	PLD_ESIO0MOD0_CTSS	0x0040
    112. 

  112. #define	PLD_ESIO0MOD0_RTSS	0x0080
    113. 

  113. #define PLD_ESIO0MOD1		__reg16(PLD_BASE + 0x20004)
    114. 

  114. #define	PLD_ESIO0MOD1_LMFS	0x0010
    115. 

  115. #define PLD_ESIO0STS		__reg16(PLD_BASE + 0x20006)
    116. 

  116. #define	PLD_ESIO0STS_TEMP	0x0001
    117. 

  117. #define	PLD_ESIO0STS_TXCP	0x0002
    118. 

  118. #define	PLD_ESIO0STS_RXCP	0x0004
    119. 

  119. #define	PLD_ESIO0STS_TXSC	0x0100
    120. 

  120. #define	PLD_ESIO0STS_RXSC	0x0200
    121. 

  121. #define PLD_ESIO0STS_TXREADY	(PLD_ESIO0STS_TXCP | PLD_ESIO0STS_TEMP)
    122. 

  122. #define PLD_ESIO0INTCR		__reg16(PLD_BASE + 0x20008)
    123. 

  123. #define	PLD_ESIO0INTCR_TXIEN	0x0002
    124. 

  124. #define	PLD_ESIO0INTCR_RXCEN	0x0004
    125. 

  125. #define PLD_ESIO0BAUR		__reg16(PLD_BASE + 0x2000a)
    126. 

  126. #define PLD_ESIO0TXB		__reg16(PLD_BASE + 0x2000c)
    127. 

  127. #define PLD_ESIO0RXB		__reg16(PLD_BASE + 0x2000e)
    128. 

  128. 

  129. /* SIM Card */
    130. 

  130. #define PLD_SCCR		__reg16(PLD_BASE + 0x38000)
    131. 

  131. #define PLD_SCMOD		__reg16(PLD_BASE + 0x38004)
    132. 

  132. #define PLD_SCSTS		__reg16(PLD_BASE + 0x38006)
    133. 

  133. #define PLD_SCINTCR		__reg16(PLD_BASE + 0x38008)
    134. 

  134. #define PLD_SCBAUR		__reg16(PLD_BASE + 0x3800a)
    135. 

  135. #define PLD_SCTXB		__reg16(PLD_BASE + 0x3800c)
    136. 

  136. #define PLD_SCRXB		__reg16(PLD_BASE + 0x3800e)
    137. 

  137. 

  138. #endif
    139. 

  139. 

  140. /* Reset Control */
    141. 

  141. #define PLD_REBOOT		__reg16(PLD_BASE + 0x38000)
    142. 

  142. 

  143. #endif	/* _MAPPI3_PLD.H */
    144.