bitops.h 7.0 KB

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  1. /*
  2. * Copyright (C) 2004-2006 Atmel Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #ifndef __ASM_AVR32_BITOPS_H
  9. #define __ASM_AVR32_BITOPS_H
  10. #include <asm/byteorder.h>
  11. #include <asm/system.h>
  12. /*
  13. * clear_bit() doesn't provide any barrier for the compiler
  14. */
  15. #define smp_mb__before_clear_bit() barrier()
  16. #define smp_mb__after_clear_bit() barrier()
  17. /*
  18. * set_bit - Atomically set a bit in memory
  19. * @nr: the bit to set
  20. * @addr: the address to start counting from
  21. *
  22. * This function is atomic and may not be reordered. See __set_bit()
  23. * if you do not require the atomic guarantees.
  24. *
  25. * Note that @nr may be almost arbitrarily large; this function is not
  26. * restricted to acting on a single-word quantity.
  27. */
  28. static inline void set_bit(int nr, volatile void * addr)
  29. {
  30. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  31. unsigned long tmp;
  32. if (__builtin_constant_p(nr)) {
  33. asm volatile(
  34. "1: ssrf 5\n"
  35. " ld.w %0, %2\n"
  36. " sbr %0, %3\n"
  37. " stcond %1, %0\n"
  38. " brne 1b"
  39. : "=&r"(tmp), "=o"(*p)
  40. : "m"(*p), "i"(nr)
  41. : "cc");
  42. } else {
  43. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  44. asm volatile(
  45. "1: ssrf 5\n"
  46. " ld.w %0, %2\n"
  47. " or %0, %3\n"
  48. " stcond %1, %0\n"
  49. " brne 1b"
  50. : "=&r"(tmp), "=o"(*p)
  51. : "m"(*p), "r"(mask)
  52. : "cc");
  53. }
  54. }
  55. /*
  56. * clear_bit - Clears a bit in memory
  57. * @nr: Bit to clear
  58. * @addr: Address to start counting from
  59. *
  60. * clear_bit() is atomic and may not be reordered. However, it does
  61. * not contain a memory barrier, so if it is used for locking purposes,
  62. * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
  63. * in order to ensure changes are visible on other processors.
  64. */
  65. static inline void clear_bit(int nr, volatile void * addr)
  66. {
  67. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  68. unsigned long tmp;
  69. if (__builtin_constant_p(nr)) {
  70. asm volatile(
  71. "1: ssrf 5\n"
  72. " ld.w %0, %2\n"
  73. " cbr %0, %3\n"
  74. " stcond %1, %0\n"
  75. " brne 1b"
  76. : "=&r"(tmp), "=o"(*p)
  77. : "m"(*p), "i"(nr)
  78. : "cc");
  79. } else {
  80. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  81. asm volatile(
  82. "1: ssrf 5\n"
  83. " ld.w %0, %2\n"
  84. " andn %0, %3\n"
  85. " stcond %1, %0\n"
  86. " brne 1b"
  87. : "=&r"(tmp), "=o"(*p)
  88. : "m"(*p), "r"(mask)
  89. : "cc");
  90. }
  91. }
  92. /*
  93. * change_bit - Toggle a bit in memory
  94. * @nr: Bit to change
  95. * @addr: Address to start counting from
  96. *
  97. * change_bit() is atomic and may not be reordered.
  98. * Note that @nr may be almost arbitrarily large; this function is not
  99. * restricted to acting on a single-word quantity.
  100. */
  101. static inline void change_bit(int nr, volatile void * addr)
  102. {
  103. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  104. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  105. unsigned long tmp;
  106. asm volatile(
  107. "1: ssrf 5\n"
  108. " ld.w %0, %2\n"
  109. " eor %0, %3\n"
  110. " stcond %1, %0\n"
  111. " brne 1b"
  112. : "=&r"(tmp), "=o"(*p)
  113. : "m"(*p), "r"(mask)
  114. : "cc");
  115. }
  116. /*
  117. * test_and_set_bit - Set a bit and return its old value
  118. * @nr: Bit to set
  119. * @addr: Address to count from
  120. *
  121. * This operation is atomic and cannot be reordered.
  122. * It also implies a memory barrier.
  123. */
  124. static inline int test_and_set_bit(int nr, volatile void * addr)
  125. {
  126. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  127. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  128. unsigned long tmp, old;
  129. if (__builtin_constant_p(nr)) {
  130. asm volatile(
  131. "1: ssrf 5\n"
  132. " ld.w %0, %3\n"
  133. " mov %2, %0\n"
  134. " sbr %0, %4\n"
  135. " stcond %1, %0\n"
  136. " brne 1b"
  137. : "=&r"(tmp), "=o"(*p), "=&r"(old)
  138. : "m"(*p), "i"(nr)
  139. : "memory", "cc");
  140. } else {
  141. asm volatile(
  142. "1: ssrf 5\n"
  143. " ld.w %2, %3\n"
  144. " or %0, %2, %4\n"
  145. " stcond %1, %0\n"
  146. " brne 1b"
  147. : "=&r"(tmp), "=o"(*p), "=&r"(old)
  148. : "m"(*p), "r"(mask)
  149. : "memory", "cc");
  150. }
  151. return (old & mask) != 0;
  152. }
  153. /*
  154. * test_and_clear_bit - Clear a bit and return its old value
  155. * @nr: Bit to clear
  156. * @addr: Address to count from
  157. *
  158. * This operation is atomic and cannot be reordered.
  159. * It also implies a memory barrier.
  160. */
  161. static inline int test_and_clear_bit(int nr, volatile void * addr)
  162. {
  163. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  164. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  165. unsigned long tmp, old;
  166. if (__builtin_constant_p(nr)) {
  167. asm volatile(
  168. "1: ssrf 5\n"
  169. " ld.w %0, %3\n"
  170. " mov %2, %0\n"
  171. " cbr %0, %4\n"
  172. " stcond %1, %0\n"
  173. " brne 1b"
  174. : "=&r"(tmp), "=o"(*p), "=&r"(old)
  175. : "m"(*p), "i"(nr)
  176. : "memory", "cc");
  177. } else {
  178. asm volatile(
  179. "1: ssrf 5\n"
  180. " ld.w %0, %3\n"
  181. " mov %2, %0\n"
  182. " andn %0, %4\n"
  183. " stcond %1, %0\n"
  184. " brne 1b"
  185. : "=&r"(tmp), "=o"(*p), "=&r"(old)
  186. : "m"(*p), "r"(mask)
  187. : "memory", "cc");
  188. }
  189. return (old & mask) != 0;
  190. }
  191. /*
  192. * test_and_change_bit - Change a bit and return its old value
  193. * @nr: Bit to change
  194. * @addr: Address to count from
  195. *
  196. * This operation is atomic and cannot be reordered.
  197. * It also implies a memory barrier.
  198. */
  199. static inline int test_and_change_bit(int nr, volatile void * addr)
  200. {
  201. unsigned long *p = ((unsigned long *)addr) + nr / BITS_PER_LONG;
  202. unsigned long mask = 1UL << (nr % BITS_PER_LONG);
  203. unsigned long tmp, old;
  204. asm volatile(
  205. "1: ssrf 5\n"
  206. " ld.w %2, %3\n"
  207. " eor %0, %2, %4\n"
  208. " stcond %1, %0\n"
  209. " brne 1b"
  210. : "=&r"(tmp), "=o"(*p), "=&r"(old)
  211. : "m"(*p), "r"(mask)
  212. : "memory", "cc");
  213. return (old & mask) != 0;
  214. }
  215. #include <asm-generic/bitops/non-atomic.h>
  216. /* Find First bit Set */
  217. static inline unsigned long __ffs(unsigned long word)
  218. {
  219. unsigned long result;
  220. asm("brev %1\n\t"
  221. "clz %0,%1"
  222. : "=r"(result), "=&r"(word)
  223. : "1"(word));
  224. return result;
  225. }
  226. /* Find First Zero */
  227. static inline unsigned long ffz(unsigned long word)
  228. {
  229. return __ffs(~word);
  230. }
  231. /* Find Last bit Set */
  232. static inline int fls(unsigned long word)
  233. {
  234. unsigned long result;
  235. asm("clz %0,%1" : "=r"(result) : "r"(word));
  236. return 32 - result;
  237. }
  238. unsigned long find_first_zero_bit(const unsigned long *addr,
  239. unsigned long size);
  240. unsigned long find_next_zero_bit(const unsigned long *addr,
  241. unsigned long size,
  242. unsigned long offset);
  243. unsigned long find_first_bit(const unsigned long *addr,
  244. unsigned long size);
  245. unsigned long find_next_bit(const unsigned long *addr,
  246. unsigned long size,
  247. unsigned long offset);
  248. /*
  249. * ffs: find first bit set. This is defined the same way as
  250. * the libc and compiler builtin ffs routines, therefore
  251. * differs in spirit from the above ffz (man ffs).
  252. *
  253. * The difference is that bit numbering starts at 1, and if no bit is set,
  254. * the function returns 0.
  255. */
  256. static inline int ffs(unsigned long word)
  257. {
  258. if(word == 0)
  259. return 0;
  260. return __ffs(word) + 1;
  261. }
  262. #include <asm-generic/bitops/fls64.h>
  263. #include <asm-generic/bitops/sched.h>
  264. #include <asm-generic/bitops/hweight.h>
  265. #include <asm-generic/bitops/ext2-non-atomic.h>
  266. #include <asm-generic/bitops/ext2-atomic.h>
  267. #include <asm-generic/bitops/minix-le.h>
  268. #endif /* __ASM_AVR32_BITOPS_H */