via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  80. struct pt_regs *regs);
  81. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  82. static int via_ircc_read_dongle_id(int iobase);
  83. static int via_ircc_net_open(struct net_device *dev);
  84. static int via_ircc_net_close(struct net_device *dev);
  85. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  86. int cmd);
  87. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  88. *dev);
  89. static void via_ircc_change_dongle_speed(int iobase, int speed,
  90. int dongle_id);
  91. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  92. static void hwreset(struct via_ircc_cb *self);
  93. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  94. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  95. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  96. static void __devexit via_remove_one (struct pci_dev *pdev);
  97. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  98. static void iodelay(int udelay)
  99. {
  100. u8 data;
  101. int i;
  102. for (i = 0; i < udelay; i++) {
  103. data = inb(0x80);
  104. }
  105. }
  106. static struct pci_device_id via_pci_tbl[] = {
  107. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  108. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  109. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  110. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  111. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  112. { 0, }
  113. };
  114. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  115. static struct pci_driver via_driver = {
  116. .name = VIA_MODULE_NAME,
  117. .id_table = via_pci_tbl,
  118. .probe = via_init_one,
  119. .remove = __devexit_p(via_remove_one),
  120. };
  121. /*
  122. * Function via_ircc_init ()
  123. *
  124. * Initialize chip. Just find out chip type and resource.
  125. */
  126. static int __init via_ircc_init(void)
  127. {
  128. int rc;
  129. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  130. rc = pci_register_driver(&via_driver);
  131. if (rc < 0) {
  132. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  133. __FUNCTION__, rc);
  134. return -ENODEV;
  135. }
  136. return 0;
  137. }
  138. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  139. {
  140. int rc;
  141. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  142. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  143. chipio_t info;
  144. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __FUNCTION__, id->device);
  145. rc = pci_enable_device (pcidev);
  146. if (rc) {
  147. IRDA_DEBUG(0, "%s(): error rc = %d\n", __FUNCTION__, rc);
  148. return -ENODEV;
  149. }
  150. // South Bridge exist
  151. if ( ReadLPCReg(0x20) != 0x3C )
  152. Chipset=0x3096;
  153. else
  154. Chipset=0x3076;
  155. if (Chipset==0x3076) {
  156. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __FUNCTION__);
  157. WriteLPCReg(7,0x0c );
  158. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  159. if((temp&0x01)==1) { // BIOS close or no FIR
  160. WriteLPCReg(0x1d, 0x82 );
  161. WriteLPCReg(0x23,0x18);
  162. temp=ReadLPCReg(0xF0);
  163. if((temp&0x01)==0) {
  164. temp=(ReadLPCReg(0x74)&0x03); //DMA
  165. FirDRQ0=temp + 4;
  166. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  167. FirDRQ1=temp + 4;
  168. } else {
  169. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  170. FirDRQ0=temp + 4;
  171. FirDRQ1=FirDRQ0;
  172. }
  173. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  174. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  175. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  176. FirIOBase=FirIOBase ;
  177. info.fir_base=FirIOBase;
  178. info.irq=FirIRQ;
  179. info.dma=FirDRQ1;
  180. info.dma2=FirDRQ0;
  181. pci_read_config_byte(pcidev,0x40,&bTmp);
  182. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  183. pci_read_config_byte(pcidev,0x42,&bTmp);
  184. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  185. pci_write_config_byte(pcidev,0x5a,0xc0);
  186. WriteLPCReg(0x28, 0x70 );
  187. if (via_ircc_open(0, &info,0x3076) == 0)
  188. rc=0;
  189. } else
  190. rc = -ENODEV; //IR not turn on
  191. } else { //Not VT1211
  192. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __FUNCTION__);
  193. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  194. if((bTmp&0x01)==1) { // BIOS enable FIR
  195. //Enable Double DMA clock
  196. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  197. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  198. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  199. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  200. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  201. pci_write_config_byte(pcidev,0x44,0x4e);
  202. //---------- read configuration from Function0 of south bridge
  203. if((bTmp&0x02)==0) {
  204. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  205. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  206. pci_read_config_byte(pcidev,0x44,&bTmp1);
  207. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  208. } else {
  209. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  210. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  211. FirDRQ1=0;
  212. }
  213. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  214. FirIRQ = bTmp1 & 0x0f;
  215. pci_read_config_byte(pcidev,0x69,&bTmp);
  216. FirIOBase = bTmp << 8;//hight byte
  217. pci_read_config_byte(pcidev,0x68,&bTmp);
  218. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  219. //-------------------------
  220. info.fir_base=FirIOBase;
  221. info.irq=FirIRQ;
  222. info.dma=FirDRQ1;
  223. info.dma2=FirDRQ0;
  224. if (via_ircc_open(0, &info,0x3096) == 0)
  225. rc=0;
  226. } else
  227. rc = -ENODEV; //IR not turn on !!!!!
  228. }//Not VT1211
  229. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __FUNCTION__, rc);
  230. return rc;
  231. }
  232. /*
  233. * Function via_ircc_clean ()
  234. *
  235. * Close all configured chips
  236. *
  237. */
  238. static void via_ircc_clean(void)
  239. {
  240. int i;
  241. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  242. for (i=0; i < ARRAY_SIZE(dev_self); i++) {
  243. if (dev_self[i])
  244. via_ircc_close(dev_self[i]);
  245. }
  246. }
  247. static void __devexit via_remove_one (struct pci_dev *pdev)
  248. {
  249. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  250. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  251. * to get our driver instance and call directly via_ircc_close().
  252. * See vlsi_ir for details...
  253. * Jean II */
  254. via_ircc_clean();
  255. /* FIXME : This should be in via_ircc_close(), because here we may
  256. * theoritically disable still configured devices :-( - Jean II */
  257. pci_disable_device(pdev);
  258. }
  259. static void __exit via_ircc_cleanup(void)
  260. {
  261. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  262. /* FIXME : This should be redundant, as pci_unregister_driver()
  263. * should call via_remove_one() on each device.
  264. * Jean II */
  265. via_ircc_clean();
  266. /* Cleanup all instances of the driver */
  267. pci_unregister_driver (&via_driver);
  268. }
  269. /*
  270. * Function via_ircc_open (iobase, irq)
  271. *
  272. * Open driver instance
  273. *
  274. */
  275. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  276. {
  277. struct net_device *dev;
  278. struct via_ircc_cb *self;
  279. int err;
  280. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  281. if (i >= ARRAY_SIZE(dev_self))
  282. return -ENOMEM;
  283. /* Allocate new instance of the driver */
  284. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  285. if (dev == NULL)
  286. return -ENOMEM;
  287. self = dev->priv;
  288. self->netdev = dev;
  289. spin_lock_init(&self->lock);
  290. /* FIXME : We should store our driver instance in the PCI layer,
  291. * using pci_set_drvdata(), not in this array.
  292. * See vlsi_ir for details... - Jean II */
  293. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  294. /* Need to store self somewhere */
  295. dev_self[i] = self;
  296. self->index = i;
  297. /* Initialize Resource */
  298. self->io.cfg_base = info->cfg_base;
  299. self->io.fir_base = info->fir_base;
  300. self->io.irq = info->irq;
  301. self->io.fir_ext = CHIP_IO_EXTENT;
  302. self->io.dma = info->dma;
  303. self->io.dma2 = info->dma2;
  304. self->io.fifo_size = 32;
  305. self->chip_id = id;
  306. self->st_fifo.len = 0;
  307. self->RxDataReady = 0;
  308. /* Reserve the ioports that we need */
  309. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  310. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  311. __FUNCTION__, self->io.fir_base);
  312. err = -ENODEV;
  313. goto err_out1;
  314. }
  315. /* Initialize QoS for this device */
  316. irda_init_max_qos_capabilies(&self->qos);
  317. /* Check if user has supplied the dongle id or not */
  318. if (!dongle_id)
  319. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  320. self->io.dongle_id = dongle_id;
  321. /* The only value we must override it the baudrate */
  322. /* Maximum speeds and capabilities are dongle-dependant. */
  323. switch( self->io.dongle_id ){
  324. case 0x0d:
  325. self->qos.baud_rate.bits =
  326. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  327. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  328. break;
  329. default:
  330. self->qos.baud_rate.bits =
  331. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  332. break;
  333. }
  334. /* Following was used for testing:
  335. *
  336. * self->qos.baud_rate.bits = IR_9600;
  337. *
  338. * Is is no good, as it prohibits (error-prone) speed-changes.
  339. */
  340. self->qos.min_turn_time.bits = qos_mtt_bits;
  341. irda_qos_bits_to_value(&self->qos);
  342. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  343. self->rx_buff.truesize = 14384 + 2048;
  344. self->tx_buff.truesize = 14384 + 2048;
  345. /* Allocate memory if needed */
  346. self->rx_buff.head =
  347. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  348. &self->rx_buff_dma, GFP_KERNEL);
  349. if (self->rx_buff.head == NULL) {
  350. err = -ENOMEM;
  351. goto err_out2;
  352. }
  353. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  354. self->tx_buff.head =
  355. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  356. &self->tx_buff_dma, GFP_KERNEL);
  357. if (self->tx_buff.head == NULL) {
  358. err = -ENOMEM;
  359. goto err_out3;
  360. }
  361. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  362. self->rx_buff.in_frame = FALSE;
  363. self->rx_buff.state = OUTSIDE_FRAME;
  364. self->tx_buff.data = self->tx_buff.head;
  365. self->rx_buff.data = self->rx_buff.head;
  366. /* Reset Tx queue info */
  367. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  368. self->tx_fifo.tail = self->tx_buff.head;
  369. /* Keep track of module usage */
  370. SET_MODULE_OWNER(dev);
  371. /* Override the network functions we need to use */
  372. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  373. dev->open = via_ircc_net_open;
  374. dev->stop = via_ircc_net_close;
  375. dev->do_ioctl = via_ircc_net_ioctl;
  376. dev->get_stats = via_ircc_net_get_stats;
  377. err = register_netdev(dev);
  378. if (err)
  379. goto err_out4;
  380. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  381. /* Initialise the hardware..
  382. */
  383. self->io.speed = 9600;
  384. via_hw_init(self);
  385. return 0;
  386. err_out4:
  387. dma_free_coherent(NULL, self->tx_buff.truesize,
  388. self->tx_buff.head, self->tx_buff_dma);
  389. err_out3:
  390. dma_free_coherent(NULL, self->rx_buff.truesize,
  391. self->rx_buff.head, self->rx_buff_dma);
  392. err_out2:
  393. release_region(self->io.fir_base, self->io.fir_ext);
  394. err_out1:
  395. free_netdev(dev);
  396. dev_self[i] = NULL;
  397. return err;
  398. }
  399. /*
  400. * Function via_ircc_close (self)
  401. *
  402. * Close driver instance
  403. *
  404. */
  405. static int via_ircc_close(struct via_ircc_cb *self)
  406. {
  407. int iobase;
  408. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  409. IRDA_ASSERT(self != NULL, return -1;);
  410. iobase = self->io.fir_base;
  411. ResetChip(iobase, 5); //hardware reset.
  412. /* Remove netdevice */
  413. unregister_netdev(self->netdev);
  414. /* Release the PORT that this driver is using */
  415. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  416. __FUNCTION__, self->io.fir_base);
  417. release_region(self->io.fir_base, self->io.fir_ext);
  418. if (self->tx_buff.head)
  419. dma_free_coherent(NULL, self->tx_buff.truesize,
  420. self->tx_buff.head, self->tx_buff_dma);
  421. if (self->rx_buff.head)
  422. dma_free_coherent(NULL, self->rx_buff.truesize,
  423. self->rx_buff.head, self->rx_buff_dma);
  424. dev_self[self->index] = NULL;
  425. free_netdev(self->netdev);
  426. return 0;
  427. }
  428. /*
  429. * Function via_hw_init(self)
  430. *
  431. * Returns non-negative on success.
  432. *
  433. * Formerly via_ircc_setup
  434. */
  435. static void via_hw_init(struct via_ircc_cb *self)
  436. {
  437. int iobase = self->io.fir_base;
  438. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  439. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  440. // FIFO Init
  441. EnRXFIFOReadyInt(iobase, OFF);
  442. EnRXFIFOHalfLevelInt(iobase, OFF);
  443. EnTXFIFOHalfLevelInt(iobase, OFF);
  444. EnTXFIFOUnderrunEOMInt(iobase, ON);
  445. EnTXFIFOReadyInt(iobase, OFF);
  446. InvertTX(iobase, OFF);
  447. InvertRX(iobase, OFF);
  448. if (ReadLPCReg(0x20) == 0x3c)
  449. WriteLPCReg(0xF0, 0); // for VT1211
  450. /* Int Init */
  451. EnRXSpecInt(iobase, ON);
  452. /* The following is basically hwreset */
  453. /* If this is the case, why not just call hwreset() ? Jean II */
  454. ResetChip(iobase, 5);
  455. EnableDMA(iobase, OFF);
  456. EnableTX(iobase, OFF);
  457. EnableRX(iobase, OFF);
  458. EnRXDMA(iobase, OFF);
  459. EnTXDMA(iobase, OFF);
  460. RXStart(iobase, OFF);
  461. TXStart(iobase, OFF);
  462. InitCard(iobase);
  463. CommonInit(iobase);
  464. SIRFilter(iobase, ON);
  465. SetSIR(iobase, ON);
  466. CRC16(iobase, ON);
  467. EnTXCRC(iobase, 0);
  468. WriteReg(iobase, I_ST_CT_0, 0x00);
  469. SetBaudRate(iobase, 9600);
  470. SetPulseWidth(iobase, 12);
  471. SetSendPreambleCount(iobase, 0);
  472. self->io.speed = 9600;
  473. self->st_fifo.len = 0;
  474. via_ircc_change_dongle_speed(iobase, self->io.speed,
  475. self->io.dongle_id);
  476. WriteReg(iobase, I_ST_CT_0, 0x80);
  477. }
  478. /*
  479. * Function via_ircc_read_dongle_id (void)
  480. *
  481. */
  482. static int via_ircc_read_dongle_id(int iobase)
  483. {
  484. int dongle_id = 9; /* Default to IBM */
  485. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  486. return dongle_id;
  487. }
  488. /*
  489. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  490. * Change speed of the attach dongle
  491. * only implement two type of dongle currently.
  492. */
  493. static void via_ircc_change_dongle_speed(int iobase, int speed,
  494. int dongle_id)
  495. {
  496. u8 mode = 0;
  497. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  498. speed = speed;
  499. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  500. __FUNCTION__, speed, iobase, dongle_id);
  501. switch (dongle_id) {
  502. /* Note: The dongle_id's listed here are derived from
  503. * nsc-ircc.c */
  504. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  505. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  506. InvertTX(iobase, OFF);
  507. InvertRX(iobase, OFF);
  508. EnRX2(iobase, ON); //sir to rx2
  509. EnGPIOtoRX2(iobase, OFF);
  510. if (IsSIROn(iobase)) { //sir
  511. // Mode select Off
  512. SlowIRRXLowActive(iobase, ON);
  513. udelay(1000);
  514. SlowIRRXLowActive(iobase, OFF);
  515. } else {
  516. if (IsMIROn(iobase)) { //mir
  517. // Mode select On
  518. SlowIRRXLowActive(iobase, OFF);
  519. udelay(20);
  520. } else { // fir
  521. if (IsFIROn(iobase)) { //fir
  522. // Mode select On
  523. SlowIRRXLowActive(iobase, OFF);
  524. udelay(20);
  525. }
  526. }
  527. }
  528. break;
  529. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  530. UseOneRX(iobase, ON); //use ONE RX....RX1
  531. InvertTX(iobase, OFF);
  532. InvertRX(iobase, OFF); // invert RX pin
  533. EnRX2(iobase, ON);
  534. EnGPIOtoRX2(iobase, OFF);
  535. if (IsSIROn(iobase)) { //sir
  536. // Mode select On
  537. SlowIRRXLowActive(iobase, ON);
  538. udelay(20);
  539. // Mode select Off
  540. SlowIRRXLowActive(iobase, OFF);
  541. }
  542. if (IsMIROn(iobase)) { //mir
  543. // Mode select On
  544. SlowIRRXLowActive(iobase, OFF);
  545. udelay(20);
  546. // Mode select Off
  547. SlowIRRXLowActive(iobase, ON);
  548. } else { // fir
  549. if (IsFIROn(iobase)) { //fir
  550. // Mode select On
  551. SlowIRRXLowActive(iobase, OFF);
  552. // TX On
  553. WriteTX(iobase, ON);
  554. udelay(20);
  555. // Mode select OFF
  556. SlowIRRXLowActive(iobase, ON);
  557. udelay(20);
  558. // TX Off
  559. WriteTX(iobase, OFF);
  560. }
  561. }
  562. break;
  563. case 0x0d:
  564. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  565. InvertTX(iobase, OFF);
  566. InvertRX(iobase, OFF);
  567. SlowIRRXLowActive(iobase, OFF);
  568. if (IsSIROn(iobase)) { //sir
  569. EnGPIOtoRX2(iobase, OFF);
  570. WriteGIO(iobase, OFF);
  571. EnRX2(iobase, OFF); //sir to rx2
  572. } else { // fir mir
  573. EnGPIOtoRX2(iobase, OFF);
  574. WriteGIO(iobase, OFF);
  575. EnRX2(iobase, OFF); //fir to rx
  576. }
  577. break;
  578. case 0x11: /* Temic TFDS4500 */
  579. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __FUNCTION__);
  580. UseOneRX(iobase, ON); //use ONE RX....RX1
  581. InvertTX(iobase, OFF);
  582. InvertRX(iobase, ON); // invert RX pin
  583. EnRX2(iobase, ON); //sir to rx2
  584. EnGPIOtoRX2(iobase, OFF);
  585. if( IsSIROn(iobase) ){ //sir
  586. // Mode select On
  587. SlowIRRXLowActive(iobase, ON);
  588. udelay(20);
  589. // Mode select Off
  590. SlowIRRXLowActive(iobase, OFF);
  591. } else{
  592. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __FUNCTION__);
  593. }
  594. break;
  595. case 0x0ff: /* Vishay */
  596. if (IsSIROn(iobase))
  597. mode = 0;
  598. else if (IsMIROn(iobase))
  599. mode = 1;
  600. else if (IsFIROn(iobase))
  601. mode = 2;
  602. else if (IsVFIROn(iobase))
  603. mode = 5; //VFIR-16
  604. SI_SetMode(iobase, mode);
  605. break;
  606. default:
  607. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  608. __FUNCTION__, dongle_id);
  609. }
  610. }
  611. /*
  612. * Function via_ircc_change_speed (self, baud)
  613. *
  614. * Change the speed of the device
  615. *
  616. */
  617. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  618. {
  619. struct net_device *dev = self->netdev;
  620. u16 iobase;
  621. u8 value = 0, bTmp;
  622. iobase = self->io.fir_base;
  623. /* Update accounting for new speed */
  624. self->io.speed = speed;
  625. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __FUNCTION__, speed);
  626. WriteReg(iobase, I_ST_CT_0, 0x0);
  627. /* Controller mode sellection */
  628. switch (speed) {
  629. case 2400:
  630. case 9600:
  631. case 19200:
  632. case 38400:
  633. case 57600:
  634. case 115200:
  635. value = (115200/speed)-1;
  636. SetSIR(iobase, ON);
  637. CRC16(iobase, ON);
  638. break;
  639. case 576000:
  640. /* FIXME: this can't be right, as it's the same as 115200,
  641. * and 576000 is MIR, not SIR. */
  642. value = 0;
  643. SetSIR(iobase, ON);
  644. CRC16(iobase, ON);
  645. break;
  646. case 1152000:
  647. value = 0;
  648. SetMIR(iobase, ON);
  649. /* FIXME: CRC ??? */
  650. break;
  651. case 4000000:
  652. value = 0;
  653. SetFIR(iobase, ON);
  654. SetPulseWidth(iobase, 0);
  655. SetSendPreambleCount(iobase, 14);
  656. CRC16(iobase, OFF);
  657. EnTXCRC(iobase, ON);
  658. break;
  659. case 16000000:
  660. value = 0;
  661. SetVFIR(iobase, ON);
  662. /* FIXME: CRC ??? */
  663. break;
  664. default:
  665. value = 0;
  666. break;
  667. }
  668. /* Set baudrate to 0x19[2..7] */
  669. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  670. bTmp |= value << 2;
  671. WriteReg(iobase, I_CF_H_1, bTmp);
  672. /* Some dongles may need to be informed about speed changes. */
  673. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  674. /* Set FIFO size to 64 */
  675. SetFIFO(iobase, 64);
  676. /* Enable IR */
  677. WriteReg(iobase, I_ST_CT_0, 0x80);
  678. // EnTXFIFOHalfLevelInt(iobase,ON);
  679. /* Enable some interrupts so we can receive frames */
  680. //EnAllInt(iobase,ON);
  681. if (IsSIROn(iobase)) {
  682. SIRFilter(iobase, ON);
  683. SIRRecvAny(iobase, ON);
  684. } else {
  685. SIRFilter(iobase, OFF);
  686. SIRRecvAny(iobase, OFF);
  687. }
  688. if (speed > 115200) {
  689. /* Install FIR xmit handler */
  690. dev->hard_start_xmit = via_ircc_hard_xmit_fir;
  691. via_ircc_dma_receive(self);
  692. } else {
  693. /* Install SIR xmit handler */
  694. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  695. }
  696. netif_wake_queue(dev);
  697. }
  698. /*
  699. * Function via_ircc_hard_xmit (skb, dev)
  700. *
  701. * Transmit the frame!
  702. *
  703. */
  704. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  705. struct net_device *dev)
  706. {
  707. struct via_ircc_cb *self;
  708. unsigned long flags;
  709. u16 iobase;
  710. __u32 speed;
  711. self = (struct via_ircc_cb *) dev->priv;
  712. IRDA_ASSERT(self != NULL, return 0;);
  713. iobase = self->io.fir_base;
  714. netif_stop_queue(dev);
  715. /* Check if we need to change the speed */
  716. speed = irda_get_next_speed(skb);
  717. if ((speed != self->io.speed) && (speed != -1)) {
  718. /* Check for empty frame */
  719. if (!skb->len) {
  720. via_ircc_change_speed(self, speed);
  721. dev->trans_start = jiffies;
  722. dev_kfree_skb(skb);
  723. return 0;
  724. } else
  725. self->new_speed = speed;
  726. }
  727. InitCard(iobase);
  728. CommonInit(iobase);
  729. SIRFilter(iobase, ON);
  730. SetSIR(iobase, ON);
  731. CRC16(iobase, ON);
  732. EnTXCRC(iobase, 0);
  733. WriteReg(iobase, I_ST_CT_0, 0x00);
  734. spin_lock_irqsave(&self->lock, flags);
  735. self->tx_buff.data = self->tx_buff.head;
  736. self->tx_buff.len =
  737. async_wrap_skb(skb, self->tx_buff.data,
  738. self->tx_buff.truesize);
  739. self->stats.tx_bytes += self->tx_buff.len;
  740. /* Send this frame with old speed */
  741. SetBaudRate(iobase, self->io.speed);
  742. SetPulseWidth(iobase, 12);
  743. SetSendPreambleCount(iobase, 0);
  744. WriteReg(iobase, I_ST_CT_0, 0x80);
  745. EnableTX(iobase, ON);
  746. EnableRX(iobase, OFF);
  747. ResetChip(iobase, 0);
  748. ResetChip(iobase, 1);
  749. ResetChip(iobase, 2);
  750. ResetChip(iobase, 3);
  751. ResetChip(iobase, 4);
  752. EnAllInt(iobase, ON);
  753. EnTXDMA(iobase, ON);
  754. EnRXDMA(iobase, OFF);
  755. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  756. DMA_TX_MODE);
  757. SetSendByte(iobase, self->tx_buff.len);
  758. RXStart(iobase, OFF);
  759. TXStart(iobase, ON);
  760. dev->trans_start = jiffies;
  761. spin_unlock_irqrestore(&self->lock, flags);
  762. dev_kfree_skb(skb);
  763. return 0;
  764. }
  765. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  766. struct net_device *dev)
  767. {
  768. struct via_ircc_cb *self;
  769. u16 iobase;
  770. __u32 speed;
  771. unsigned long flags;
  772. self = (struct via_ircc_cb *) dev->priv;
  773. iobase = self->io.fir_base;
  774. if (self->st_fifo.len)
  775. return 0;
  776. if (self->chip_id == 0x3076)
  777. iodelay(1500);
  778. else
  779. udelay(1500);
  780. netif_stop_queue(dev);
  781. speed = irda_get_next_speed(skb);
  782. if ((speed != self->io.speed) && (speed != -1)) {
  783. if (!skb->len) {
  784. via_ircc_change_speed(self, speed);
  785. dev->trans_start = jiffies;
  786. dev_kfree_skb(skb);
  787. return 0;
  788. } else
  789. self->new_speed = speed;
  790. }
  791. spin_lock_irqsave(&self->lock, flags);
  792. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  793. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  794. self->tx_fifo.tail += skb->len;
  795. self->stats.tx_bytes += skb->len;
  796. memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
  797. skb->len);
  798. self->tx_fifo.len++;
  799. self->tx_fifo.free++;
  800. //F01 if (self->tx_fifo.len == 1) {
  801. via_ircc_dma_xmit(self, iobase);
  802. //F01 }
  803. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  804. dev->trans_start = jiffies;
  805. dev_kfree_skb(skb);
  806. spin_unlock_irqrestore(&self->lock, flags);
  807. return 0;
  808. }
  809. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  810. {
  811. EnTXDMA(iobase, OFF);
  812. self->io.direction = IO_XMIT;
  813. EnPhys(iobase, ON);
  814. EnableTX(iobase, ON);
  815. EnableRX(iobase, OFF);
  816. ResetChip(iobase, 0);
  817. ResetChip(iobase, 1);
  818. ResetChip(iobase, 2);
  819. ResetChip(iobase, 3);
  820. ResetChip(iobase, 4);
  821. EnAllInt(iobase, ON);
  822. EnTXDMA(iobase, ON);
  823. EnRXDMA(iobase, OFF);
  824. irda_setup_dma(self->io.dma,
  825. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  826. self->tx_buff.head) + self->tx_buff_dma,
  827. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  828. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  829. __FUNCTION__, self->tx_fifo.ptr,
  830. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  831. self->tx_fifo.len);
  832. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  833. RXStart(iobase, OFF);
  834. TXStart(iobase, ON);
  835. return 0;
  836. }
  837. /*
  838. * Function via_ircc_dma_xmit_complete (self)
  839. *
  840. * The transfer of a frame in finished. This function will only be called
  841. * by the interrupt handler
  842. *
  843. */
  844. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  845. {
  846. int iobase;
  847. int ret = TRUE;
  848. u8 Tx_status;
  849. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  850. iobase = self->io.fir_base;
  851. /* Disable DMA */
  852. // DisableDmaChannel(self->io.dma);
  853. /* Check for underrrun! */
  854. /* Clear bit, by writing 1 into it */
  855. Tx_status = GetTXStatus(iobase);
  856. if (Tx_status & 0x08) {
  857. self->stats.tx_errors++;
  858. self->stats.tx_fifo_errors++;
  859. hwreset(self);
  860. // how to clear underrrun ?
  861. } else {
  862. self->stats.tx_packets++;
  863. ResetChip(iobase, 3);
  864. ResetChip(iobase, 4);
  865. }
  866. /* Check if we need to change the speed */
  867. if (self->new_speed) {
  868. via_ircc_change_speed(self, self->new_speed);
  869. self->new_speed = 0;
  870. }
  871. /* Finished with this frame, so prepare for next */
  872. if (IsFIROn(iobase)) {
  873. if (self->tx_fifo.len) {
  874. self->tx_fifo.len--;
  875. self->tx_fifo.ptr++;
  876. }
  877. }
  878. IRDA_DEBUG(1,
  879. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  880. __FUNCTION__,
  881. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  882. /* F01_S
  883. // Any frames to be sent back-to-back?
  884. if (self->tx_fifo.len) {
  885. // Not finished yet!
  886. via_ircc_dma_xmit(self, iobase);
  887. ret = FALSE;
  888. } else {
  889. F01_E*/
  890. // Reset Tx FIFO info
  891. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  892. self->tx_fifo.tail = self->tx_buff.head;
  893. //F01 }
  894. // Make sure we have room for more frames
  895. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  896. // Not busy transmitting anymore
  897. // Tell the network layer, that we can accept more frames
  898. netif_wake_queue(self->netdev);
  899. //F01 }
  900. return ret;
  901. }
  902. /*
  903. * Function via_ircc_dma_receive (self)
  904. *
  905. * Set configuration for receive a frame.
  906. *
  907. */
  908. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  909. {
  910. int iobase;
  911. iobase = self->io.fir_base;
  912. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  913. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  914. self->tx_fifo.tail = self->tx_buff.head;
  915. self->RxDataReady = 0;
  916. self->io.direction = IO_RECV;
  917. self->rx_buff.data = self->rx_buff.head;
  918. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  919. self->st_fifo.tail = self->st_fifo.head = 0;
  920. EnPhys(iobase, ON);
  921. EnableTX(iobase, OFF);
  922. EnableRX(iobase, ON);
  923. ResetChip(iobase, 0);
  924. ResetChip(iobase, 1);
  925. ResetChip(iobase, 2);
  926. ResetChip(iobase, 3);
  927. ResetChip(iobase, 4);
  928. EnAllInt(iobase, ON);
  929. EnTXDMA(iobase, OFF);
  930. EnRXDMA(iobase, ON);
  931. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  932. self->rx_buff.truesize, DMA_RX_MODE);
  933. TXStart(iobase, OFF);
  934. RXStart(iobase, ON);
  935. return 0;
  936. }
  937. /*
  938. * Function via_ircc_dma_receive_complete (self)
  939. *
  940. * Controller Finished with receiving frames,
  941. * and this routine is call by ISR
  942. *
  943. */
  944. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  945. int iobase)
  946. {
  947. struct st_fifo *st_fifo;
  948. struct sk_buff *skb;
  949. int len, i;
  950. u8 status = 0;
  951. iobase = self->io.fir_base;
  952. st_fifo = &self->st_fifo;
  953. if (self->io.speed < 4000000) { //Speed below FIR
  954. len = GetRecvByte(iobase, self);
  955. skb = dev_alloc_skb(len + 1);
  956. if (skb == NULL)
  957. return FALSE;
  958. // Make sure IP header gets aligned
  959. skb_reserve(skb, 1);
  960. skb_put(skb, len - 2);
  961. if (self->chip_id == 0x3076) {
  962. for (i = 0; i < len - 2; i++)
  963. skb->data[i] = self->rx_buff.data[i * 2];
  964. } else {
  965. if (self->chip_id == 0x3096) {
  966. for (i = 0; i < len - 2; i++)
  967. skb->data[i] =
  968. self->rx_buff.data[i];
  969. }
  970. }
  971. // Move to next frame
  972. self->rx_buff.data += len;
  973. self->stats.rx_bytes += len;
  974. self->stats.rx_packets++;
  975. skb->dev = self->netdev;
  976. skb->mac.raw = skb->data;
  977. skb->protocol = htons(ETH_P_IRDA);
  978. netif_rx(skb);
  979. return TRUE;
  980. }
  981. else { //FIR mode
  982. len = GetRecvByte(iobase, self);
  983. if (len == 0)
  984. return TRUE; //interrupt only, data maybe move by RxT
  985. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  986. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  987. __FUNCTION__, len, RxCurCount(iobase, self),
  988. self->RxLastCount);
  989. hwreset(self);
  990. return FALSE;
  991. }
  992. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  993. __FUNCTION__,
  994. st_fifo->len, len - 4, RxCurCount(iobase, self));
  995. st_fifo->entries[st_fifo->tail].status = status;
  996. st_fifo->entries[st_fifo->tail].len = len;
  997. st_fifo->pending_bytes += len;
  998. st_fifo->tail++;
  999. st_fifo->len++;
  1000. if (st_fifo->tail > MAX_RX_WINDOW)
  1001. st_fifo->tail = 0;
  1002. self->RxDataReady = 0;
  1003. // It maybe have MAX_RX_WINDOW package receive by
  1004. // receive_complete before Timer IRQ
  1005. /* F01_S
  1006. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1007. RXStart(iobase,ON);
  1008. SetTimer(iobase,4);
  1009. }
  1010. else {
  1011. F01_E */
  1012. EnableRX(iobase, OFF);
  1013. EnRXDMA(iobase, OFF);
  1014. RXStart(iobase, OFF);
  1015. //F01_S
  1016. // Put this entry back in fifo
  1017. if (st_fifo->head > MAX_RX_WINDOW)
  1018. st_fifo->head = 0;
  1019. status = st_fifo->entries[st_fifo->head].status;
  1020. len = st_fifo->entries[st_fifo->head].len;
  1021. st_fifo->head++;
  1022. st_fifo->len--;
  1023. skb = dev_alloc_skb(len + 1 - 4);
  1024. /*
  1025. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1026. * entry.
  1027. */
  1028. if ((skb == NULL) || (skb->data == NULL)
  1029. || (self->rx_buff.data == NULL) || (len < 6)) {
  1030. self->stats.rx_dropped++;
  1031. return TRUE;
  1032. }
  1033. skb_reserve(skb, 1);
  1034. skb_put(skb, len - 4);
  1035. memcpy(skb->data, self->rx_buff.data, len - 4);
  1036. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __FUNCTION__,
  1037. len - 4, self->rx_buff.data);
  1038. // Move to next frame
  1039. self->rx_buff.data += len;
  1040. self->stats.rx_bytes += len;
  1041. self->stats.rx_packets++;
  1042. skb->dev = self->netdev;
  1043. skb->mac.raw = skb->data;
  1044. skb->protocol = htons(ETH_P_IRDA);
  1045. netif_rx(skb);
  1046. //F01_E
  1047. } //FIR
  1048. return TRUE;
  1049. }
  1050. /*
  1051. * if frame is received , but no INT ,then use this routine to upload frame.
  1052. */
  1053. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1054. {
  1055. struct sk_buff *skb;
  1056. int len;
  1057. struct st_fifo *st_fifo;
  1058. st_fifo = &self->st_fifo;
  1059. len = GetRecvByte(iobase, self);
  1060. IRDA_DEBUG(2, "%s(): len=%x\n", __FUNCTION__, len);
  1061. skb = dev_alloc_skb(len + 1);
  1062. if ((skb == NULL) || ((len - 4) < 2)) {
  1063. self->stats.rx_dropped++;
  1064. return FALSE;
  1065. }
  1066. skb_reserve(skb, 1);
  1067. skb_put(skb, len - 4 + 1);
  1068. memcpy(skb->data, self->rx_buff.data, len - 4 + 1);
  1069. st_fifo->tail++;
  1070. st_fifo->len++;
  1071. if (st_fifo->tail > MAX_RX_WINDOW)
  1072. st_fifo->tail = 0;
  1073. // Move to next frame
  1074. self->rx_buff.data += len;
  1075. self->stats.rx_bytes += len;
  1076. self->stats.rx_packets++;
  1077. skb->dev = self->netdev;
  1078. skb->mac.raw = skb->data;
  1079. skb->protocol = htons(ETH_P_IRDA);
  1080. netif_rx(skb);
  1081. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1082. RXStart(iobase, ON);
  1083. } else {
  1084. EnableRX(iobase, OFF);
  1085. EnRXDMA(iobase, OFF);
  1086. RXStart(iobase, OFF);
  1087. }
  1088. return TRUE;
  1089. }
  1090. /*
  1091. * Implement back to back receive , use this routine to upload data.
  1092. */
  1093. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1094. {
  1095. struct st_fifo *st_fifo;
  1096. struct sk_buff *skb;
  1097. int len;
  1098. u8 status;
  1099. st_fifo = &self->st_fifo;
  1100. if (CkRxRecv(iobase, self)) {
  1101. // if still receiving ,then return ,don't upload frame
  1102. self->RetryCount = 0;
  1103. SetTimer(iobase, 20);
  1104. self->RxDataReady++;
  1105. return FALSE;
  1106. } else
  1107. self->RetryCount++;
  1108. if ((self->RetryCount >= 1) ||
  1109. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1110. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1111. while (st_fifo->len > 0) { //upload frame
  1112. // Put this entry back in fifo
  1113. if (st_fifo->head > MAX_RX_WINDOW)
  1114. st_fifo->head = 0;
  1115. status = st_fifo->entries[st_fifo->head].status;
  1116. len = st_fifo->entries[st_fifo->head].len;
  1117. st_fifo->head++;
  1118. st_fifo->len--;
  1119. skb = dev_alloc_skb(len + 1 - 4);
  1120. /*
  1121. * if frame size, data ptr, or skb ptr are wrong,
  1122. * then get next entry.
  1123. */
  1124. if ((skb == NULL) || (skb->data == NULL)
  1125. || (self->rx_buff.data == NULL) || (len < 6)) {
  1126. self->stats.rx_dropped++;
  1127. continue;
  1128. }
  1129. skb_reserve(skb, 1);
  1130. skb_put(skb, len - 4);
  1131. memcpy(skb->data, self->rx_buff.data, len - 4);
  1132. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __FUNCTION__,
  1133. len - 4, st_fifo->head);
  1134. // Move to next frame
  1135. self->rx_buff.data += len;
  1136. self->stats.rx_bytes += len;
  1137. self->stats.rx_packets++;
  1138. skb->dev = self->netdev;
  1139. skb->mac.raw = skb->data;
  1140. skb->protocol = htons(ETH_P_IRDA);
  1141. netif_rx(skb);
  1142. } //while
  1143. self->RetryCount = 0;
  1144. IRDA_DEBUG(2,
  1145. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1146. __FUNCTION__,
  1147. GetHostStatus(iobase), GetRXStatus(iobase));
  1148. /*
  1149. * if frame is receive complete at this routine ,then upload
  1150. * frame.
  1151. */
  1152. if ((GetRXStatus(iobase) & 0x10)
  1153. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1154. upload_rxdata(self, iobase);
  1155. if (irda_device_txqueue_empty(self->netdev))
  1156. via_ircc_dma_receive(self);
  1157. }
  1158. } // timer detect complete
  1159. else
  1160. SetTimer(iobase, 4);
  1161. return TRUE;
  1162. }
  1163. /*
  1164. * Function via_ircc_interrupt (irq, dev_id, regs)
  1165. *
  1166. * An interrupt from the chip has arrived. Time to do some work
  1167. *
  1168. */
  1169. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  1170. struct pt_regs *regs)
  1171. {
  1172. struct net_device *dev = (struct net_device *) dev_id;
  1173. struct via_ircc_cb *self;
  1174. int iobase;
  1175. u8 iHostIntType, iRxIntType, iTxIntType;
  1176. if (!dev) {
  1177. IRDA_WARNING("%s: irq %d for unknown device.\n", driver_name,
  1178. irq);
  1179. return IRQ_NONE;
  1180. }
  1181. self = (struct via_ircc_cb *) dev->priv;
  1182. iobase = self->io.fir_base;
  1183. spin_lock(&self->lock);
  1184. iHostIntType = GetHostStatus(iobase);
  1185. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1186. __FUNCTION__, iHostIntType,
  1187. (iHostIntType & 0x40) ? "Timer" : "",
  1188. (iHostIntType & 0x20) ? "Tx" : "",
  1189. (iHostIntType & 0x10) ? "Rx" : "",
  1190. (iHostIntType & 0x0e) >> 1);
  1191. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1192. self->EventFlag.TimeOut++;
  1193. ClearTimerInt(iobase, 1);
  1194. if (self->io.direction == IO_XMIT) {
  1195. via_ircc_dma_xmit(self, iobase);
  1196. }
  1197. if (self->io.direction == IO_RECV) {
  1198. /*
  1199. * frame ready hold too long, must reset.
  1200. */
  1201. if (self->RxDataReady > 30) {
  1202. hwreset(self);
  1203. if (irda_device_txqueue_empty(self->netdev)) {
  1204. via_ircc_dma_receive(self);
  1205. }
  1206. } else { // call this to upload frame.
  1207. RxTimerHandler(self, iobase);
  1208. }
  1209. } //RECV
  1210. } //Timer Event
  1211. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1212. iTxIntType = GetTXStatus(iobase);
  1213. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1214. __FUNCTION__, iTxIntType,
  1215. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1216. (iTxIntType & 0x04) ? "EOM" : "",
  1217. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1218. (iTxIntType & 0x01) ? "Early EOM" : "");
  1219. if (iTxIntType & 0x4) {
  1220. self->EventFlag.EOMessage++; // read and will auto clean
  1221. if (via_ircc_dma_xmit_complete(self)) {
  1222. if (irda_device_txqueue_empty
  1223. (self->netdev)) {
  1224. via_ircc_dma_receive(self);
  1225. }
  1226. } else {
  1227. self->EventFlag.Unknown++;
  1228. }
  1229. } //EOP
  1230. } //Tx Event
  1231. //----------------------------------------
  1232. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1233. /* Check if DMA has finished */
  1234. iRxIntType = GetRXStatus(iobase);
  1235. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1236. __FUNCTION__, iRxIntType,
  1237. (iRxIntType & 0x80) ? "PHY err." : "",
  1238. (iRxIntType & 0x40) ? "CRC err" : "",
  1239. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1240. (iRxIntType & 0x10) ? "EOF" : "",
  1241. (iRxIntType & 0x08) ? "RxData" : "",
  1242. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1243. (iRxIntType & 0x01) ? "SIR bad" : "");
  1244. if (!iRxIntType)
  1245. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __FUNCTION__);
  1246. if (iRxIntType & 0x10) {
  1247. if (via_ircc_dma_receive_complete(self, iobase)) {
  1248. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1249. via_ircc_dma_receive(self);
  1250. }
  1251. } // No ERR
  1252. else { //ERR
  1253. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1254. __FUNCTION__, iRxIntType, iHostIntType,
  1255. RxCurCount(iobase, self),
  1256. self->RxLastCount);
  1257. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1258. ResetChip(iobase, 0);
  1259. ResetChip(iobase, 1);
  1260. } else { //PHY,CRC ERR
  1261. if (iRxIntType != 0x08)
  1262. hwreset(self); //F01
  1263. }
  1264. via_ircc_dma_receive(self);
  1265. } //ERR
  1266. } //Rx Event
  1267. spin_unlock(&self->lock);
  1268. return IRQ_RETVAL(iHostIntType);
  1269. }
  1270. static void hwreset(struct via_ircc_cb *self)
  1271. {
  1272. int iobase;
  1273. iobase = self->io.fir_base;
  1274. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1275. ResetChip(iobase, 5);
  1276. EnableDMA(iobase, OFF);
  1277. EnableTX(iobase, OFF);
  1278. EnableRX(iobase, OFF);
  1279. EnRXDMA(iobase, OFF);
  1280. EnTXDMA(iobase, OFF);
  1281. RXStart(iobase, OFF);
  1282. TXStart(iobase, OFF);
  1283. InitCard(iobase);
  1284. CommonInit(iobase);
  1285. SIRFilter(iobase, ON);
  1286. SetSIR(iobase, ON);
  1287. CRC16(iobase, ON);
  1288. EnTXCRC(iobase, 0);
  1289. WriteReg(iobase, I_ST_CT_0, 0x00);
  1290. SetBaudRate(iobase, 9600);
  1291. SetPulseWidth(iobase, 12);
  1292. SetSendPreambleCount(iobase, 0);
  1293. WriteReg(iobase, I_ST_CT_0, 0x80);
  1294. /* Restore speed. */
  1295. via_ircc_change_speed(self, self->io.speed);
  1296. self->st_fifo.len = 0;
  1297. }
  1298. /*
  1299. * Function via_ircc_is_receiving (self)
  1300. *
  1301. * Return TRUE is we are currently receiving a frame
  1302. *
  1303. */
  1304. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1305. {
  1306. int status = FALSE;
  1307. int iobase;
  1308. IRDA_ASSERT(self != NULL, return FALSE;);
  1309. iobase = self->io.fir_base;
  1310. if (CkRxRecv(iobase, self))
  1311. status = TRUE;
  1312. IRDA_DEBUG(2, "%s(): status=%x....\n", __FUNCTION__, status);
  1313. return status;
  1314. }
  1315. /*
  1316. * Function via_ircc_net_open (dev)
  1317. *
  1318. * Start the device
  1319. *
  1320. */
  1321. static int via_ircc_net_open(struct net_device *dev)
  1322. {
  1323. struct via_ircc_cb *self;
  1324. int iobase;
  1325. char hwname[32];
  1326. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1327. IRDA_ASSERT(dev != NULL, return -1;);
  1328. self = (struct via_ircc_cb *) dev->priv;
  1329. self->stats.rx_packets = 0;
  1330. IRDA_ASSERT(self != NULL, return 0;);
  1331. iobase = self->io.fir_base;
  1332. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1333. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1334. self->io.irq);
  1335. return -EAGAIN;
  1336. }
  1337. /*
  1338. * Always allocate the DMA channel after the IRQ, and clean up on
  1339. * failure.
  1340. */
  1341. if (request_dma(self->io.dma, dev->name)) {
  1342. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1343. self->io.dma);
  1344. free_irq(self->io.irq, self);
  1345. return -EAGAIN;
  1346. }
  1347. if (self->io.dma2 != self->io.dma) {
  1348. if (request_dma(self->io.dma2, dev->name)) {
  1349. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1350. driver_name, self->io.dma2);
  1351. free_irq(self->io.irq, self);
  1352. return -EAGAIN;
  1353. }
  1354. }
  1355. /* turn on interrupts */
  1356. EnAllInt(iobase, ON);
  1357. EnInternalLoop(iobase, OFF);
  1358. EnExternalLoop(iobase, OFF);
  1359. /* */
  1360. via_ircc_dma_receive(self);
  1361. /* Ready to play! */
  1362. netif_start_queue(dev);
  1363. /*
  1364. * Open new IrLAP layer instance, now that everything should be
  1365. * initialized properly
  1366. */
  1367. sprintf(hwname, "VIA @ 0x%x", iobase);
  1368. self->irlap = irlap_open(dev, &self->qos, hwname);
  1369. self->RxLastCount = 0;
  1370. return 0;
  1371. }
  1372. /*
  1373. * Function via_ircc_net_close (dev)
  1374. *
  1375. * Stop the device
  1376. *
  1377. */
  1378. static int via_ircc_net_close(struct net_device *dev)
  1379. {
  1380. struct via_ircc_cb *self;
  1381. int iobase;
  1382. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1383. IRDA_ASSERT(dev != NULL, return -1;);
  1384. self = (struct via_ircc_cb *) dev->priv;
  1385. IRDA_ASSERT(self != NULL, return 0;);
  1386. /* Stop device */
  1387. netif_stop_queue(dev);
  1388. /* Stop and remove instance of IrLAP */
  1389. if (self->irlap)
  1390. irlap_close(self->irlap);
  1391. self->irlap = NULL;
  1392. iobase = self->io.fir_base;
  1393. EnTXDMA(iobase, OFF);
  1394. EnRXDMA(iobase, OFF);
  1395. DisableDmaChannel(self->io.dma);
  1396. /* Disable interrupts */
  1397. EnAllInt(iobase, OFF);
  1398. free_irq(self->io.irq, dev);
  1399. free_dma(self->io.dma);
  1400. return 0;
  1401. }
  1402. /*
  1403. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1404. *
  1405. * Process IOCTL commands for this device
  1406. *
  1407. */
  1408. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1409. int cmd)
  1410. {
  1411. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1412. struct via_ircc_cb *self;
  1413. unsigned long flags;
  1414. int ret = 0;
  1415. IRDA_ASSERT(dev != NULL, return -1;);
  1416. self = dev->priv;
  1417. IRDA_ASSERT(self != NULL, return -1;);
  1418. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
  1419. cmd);
  1420. /* Disable interrupts & save flags */
  1421. spin_lock_irqsave(&self->lock, flags);
  1422. switch (cmd) {
  1423. case SIOCSBANDWIDTH: /* Set bandwidth */
  1424. if (!capable(CAP_NET_ADMIN)) {
  1425. ret = -EPERM;
  1426. goto out;
  1427. }
  1428. via_ircc_change_speed(self, irq->ifr_baudrate);
  1429. break;
  1430. case SIOCSMEDIABUSY: /* Set media busy */
  1431. if (!capable(CAP_NET_ADMIN)) {
  1432. ret = -EPERM;
  1433. goto out;
  1434. }
  1435. irda_device_set_media_busy(self->netdev, TRUE);
  1436. break;
  1437. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1438. irq->ifr_receiving = via_ircc_is_receiving(self);
  1439. break;
  1440. default:
  1441. ret = -EOPNOTSUPP;
  1442. }
  1443. out:
  1444. spin_unlock_irqrestore(&self->lock, flags);
  1445. return ret;
  1446. }
  1447. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  1448. *dev)
  1449. {
  1450. struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
  1451. return &self->stats;
  1452. }
  1453. MODULE_AUTHOR("VIA Technologies,inc");
  1454. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1455. MODULE_LICENSE("GPL");
  1456. module_init(via_ircc_init);
  1457. module_exit(via_ircc_cleanup);