i8042.h 2.9 KB

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  1. #ifndef _I8042_H
  2. #define _I8042_H
  3. /*
  4. * Copyright (c) 1999-2002 Vojtech Pavlik
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. /*
  11. * Arch-dependent inline functions and defines.
  12. */
  13. #if defined(CONFIG_MACH_JAZZ)
  14. #include "i8042-jazzio.h"
  15. #elif defined(CONFIG_SGI_IP22)
  16. #include "i8042-ip22io.h"
  17. #elif defined(CONFIG_PPC)
  18. #include "i8042-ppcio.h"
  19. #elif defined(CONFIG_SPARC)
  20. #include "i8042-sparcio.h"
  21. #elif defined(CONFIG_X86) || defined(CONFIG_IA64)
  22. #include "i8042-x86ia64io.h"
  23. #else
  24. #include "i8042-io.h"
  25. #endif
  26. /*
  27. * This is in 50us units, the time we wait for the i8042 to react. This
  28. * has to be long enough for the i8042 itself to timeout on sending a byte
  29. * to a non-existent mouse.
  30. */
  31. #define I8042_CTL_TIMEOUT 10000
  32. /*
  33. * When the device isn't opened and it's interrupts aren't used, we poll it at
  34. * regular intervals to see if any characters arrived. If yes, we can start
  35. * probing for any mouse / keyboard connected. This is the period of the
  36. * polling.
  37. */
  38. #define I8042_POLL_PERIOD HZ/20
  39. /*
  40. * Status register bits.
  41. */
  42. #define I8042_STR_PARITY 0x80
  43. #define I8042_STR_TIMEOUT 0x40
  44. #define I8042_STR_AUXDATA 0x20
  45. #define I8042_STR_KEYLOCK 0x10
  46. #define I8042_STR_CMDDAT 0x08
  47. #define I8042_STR_MUXERR 0x04
  48. #define I8042_STR_IBF 0x02
  49. #define I8042_STR_OBF 0x01
  50. /*
  51. * Control register bits.
  52. */
  53. #define I8042_CTR_KBDINT 0x01
  54. #define I8042_CTR_AUXINT 0x02
  55. #define I8042_CTR_IGNKEYLOCK 0x08
  56. #define I8042_CTR_KBDDIS 0x10
  57. #define I8042_CTR_AUXDIS 0x20
  58. #define I8042_CTR_XLATE 0x40
  59. /*
  60. * Commands.
  61. */
  62. #define I8042_CMD_CTL_RCTR 0x0120
  63. #define I8042_CMD_CTL_WCTR 0x1060
  64. #define I8042_CMD_CTL_TEST 0x01aa
  65. #define I8042_CMD_KBD_DISABLE 0x00ad
  66. #define I8042_CMD_KBD_ENABLE 0x00ae
  67. #define I8042_CMD_KBD_TEST 0x01ab
  68. #define I8042_CMD_KBD_LOOP 0x11d2
  69. #define I8042_CMD_AUX_DISABLE 0x00a7
  70. #define I8042_CMD_AUX_ENABLE 0x00a8
  71. #define I8042_CMD_AUX_TEST 0x01a9
  72. #define I8042_CMD_AUX_SEND 0x10d4
  73. #define I8042_CMD_AUX_LOOP 0x11d3
  74. #define I8042_CMD_MUX_PFX 0x0090
  75. #define I8042_CMD_MUX_SEND 0x1090
  76. /*
  77. * Return codes.
  78. */
  79. #define I8042_RET_CTL_TEST 0x55
  80. /*
  81. * Expected maximum internal i8042 buffer size. This is used for flushing
  82. * the i8042 buffers.
  83. */
  84. #define I8042_BUFFER_SIZE 16
  85. /*
  86. * Number of AUX ports on controllers supporting active multiplexing
  87. * specification
  88. */
  89. #define I8042_NUM_MUX_PORTS 4
  90. /*
  91. * Debug.
  92. */
  93. #ifdef DEBUG
  94. static unsigned long i8042_start_time;
  95. #define dbg_init() do { i8042_start_time = jiffies; } while (0)
  96. #define dbg(format, arg...) \
  97. do { \
  98. if (i8042_debug) \
  99. printk(KERN_DEBUG __FILE__ ": " format " [%d]\n" , \
  100. ## arg, (int) (jiffies - i8042_start_time)); \
  101. } while (0)
  102. #else
  103. #define dbg_init() do { } while (0)
  104. #define dbg(format, arg...) do {} while (0)
  105. #endif
  106. #endif /* _I8042_H */