synclink_cs.c 116 KB

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  1. /*
  2. * linux/drivers/char/pcmcia/synclink_cs.c
  3. *
  4. * $Id: synclink_cs.c,v 4.34 2005/09/08 13:20:54 paulkf Exp $
  5. *
  6. * Device driver for Microgate SyncLink PC Card
  7. * multiprotocol serial adapter.
  8. *
  9. * written by Paul Fulghum for Microgate Corporation
  10. * paulkf@microgate.com
  11. *
  12. * Microgate and SyncLink are trademarks of Microgate Corporation
  13. *
  14. * This code is released under the GNU General Public License (GPL)
  15. *
  16. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  17. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19. * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  20. * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  24. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  26. * OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29. #if defined(__i386__)
  30. # define BREAKPOINT() asm(" int $3");
  31. #else
  32. # define BREAKPOINT() { }
  33. #endif
  34. #define MAX_DEVICE_COUNT 4
  35. #include <linux/config.h>
  36. #include <linux/module.h>
  37. #include <linux/errno.h>
  38. #include <linux/signal.h>
  39. #include <linux/sched.h>
  40. #include <linux/timer.h>
  41. #include <linux/time.h>
  42. #include <linux/interrupt.h>
  43. #include <linux/pci.h>
  44. #include <linux/tty.h>
  45. #include <linux/tty_flip.h>
  46. #include <linux/serial.h>
  47. #include <linux/major.h>
  48. #include <linux/string.h>
  49. #include <linux/fcntl.h>
  50. #include <linux/ptrace.h>
  51. #include <linux/ioport.h>
  52. #include <linux/mm.h>
  53. #include <linux/slab.h>
  54. #include <linux/netdevice.h>
  55. #include <linux/vmalloc.h>
  56. #include <linux/init.h>
  57. #include <asm/serial.h>
  58. #include <linux/delay.h>
  59. #include <linux/ioctl.h>
  60. #include <asm/system.h>
  61. #include <asm/io.h>
  62. #include <asm/irq.h>
  63. #include <asm/dma.h>
  64. #include <linux/bitops.h>
  65. #include <asm/types.h>
  66. #include <linux/termios.h>
  67. #include <linux/workqueue.h>
  68. #include <linux/hdlc.h>
  69. #include <pcmcia/cs_types.h>
  70. #include <pcmcia/cs.h>
  71. #include <pcmcia/cistpl.h>
  72. #include <pcmcia/cisreg.h>
  73. #include <pcmcia/ds.h>
  74. #ifdef CONFIG_HDLC_MODULE
  75. #define CONFIG_HDLC 1
  76. #endif
  77. #define GET_USER(error,value,addr) error = get_user(value,addr)
  78. #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79. #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80. #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81. #include <asm/uaccess.h>
  82. #include "linux/synclink.h"
  83. static MGSL_PARAMS default_params = {
  84. MGSL_MODE_HDLC, /* unsigned long mode */
  85. 0, /* unsigned char loopback; */
  86. HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
  87. HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
  88. 0, /* unsigned long clock_speed; */
  89. 0xff, /* unsigned char addr_filter; */
  90. HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
  91. HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
  92. HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
  93. 9600, /* unsigned long data_rate; */
  94. 8, /* unsigned char data_bits; */
  95. 1, /* unsigned char stop_bits; */
  96. ASYNC_PARITY_NONE /* unsigned char parity; */
  97. };
  98. typedef struct
  99. {
  100. int count;
  101. unsigned char status;
  102. char data[1];
  103. } RXBUF;
  104. /* The queue of BH actions to be performed */
  105. #define BH_RECEIVE 1
  106. #define BH_TRANSMIT 2
  107. #define BH_STATUS 4
  108. #define IO_PIN_SHUTDOWN_LIMIT 100
  109. #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
  110. struct _input_signal_events {
  111. int ri_up;
  112. int ri_down;
  113. int dsr_up;
  114. int dsr_down;
  115. int dcd_up;
  116. int dcd_down;
  117. int cts_up;
  118. int cts_down;
  119. };
  120. /*
  121. * Device instance data structure
  122. */
  123. typedef struct _mgslpc_info {
  124. void *if_ptr; /* General purpose pointer (used by SPPP) */
  125. int magic;
  126. int flags;
  127. int count; /* count of opens */
  128. int line;
  129. unsigned short close_delay;
  130. unsigned short closing_wait; /* time to wait before closing */
  131. struct mgsl_icount icount;
  132. struct tty_struct *tty;
  133. int timeout;
  134. int x_char; /* xon/xoff character */
  135. int blocked_open; /* # of blocked opens */
  136. unsigned char read_status_mask;
  137. unsigned char ignore_status_mask;
  138. unsigned char *tx_buf;
  139. int tx_put;
  140. int tx_get;
  141. int tx_count;
  142. /* circular list of fixed length rx buffers */
  143. unsigned char *rx_buf; /* memory allocated for all rx buffers */
  144. int rx_buf_total_size; /* size of memory allocated for rx buffers */
  145. int rx_put; /* index of next empty rx buffer */
  146. int rx_get; /* index of next full rx buffer */
  147. int rx_buf_size; /* size in bytes of single rx buffer */
  148. int rx_buf_count; /* total number of rx buffers */
  149. int rx_frame_count; /* number of full rx buffers */
  150. wait_queue_head_t open_wait;
  151. wait_queue_head_t close_wait;
  152. wait_queue_head_t status_event_wait_q;
  153. wait_queue_head_t event_wait_q;
  154. struct timer_list tx_timer; /* HDLC transmit timeout timer */
  155. struct _mgslpc_info *next_device; /* device list link */
  156. unsigned short imra_value;
  157. unsigned short imrb_value;
  158. unsigned char pim_value;
  159. spinlock_t lock;
  160. struct work_struct task; /* task structure for scheduling bh */
  161. u32 max_frame_size;
  162. u32 pending_bh;
  163. int bh_running;
  164. int bh_requested;
  165. int dcd_chkcount; /* check counts to prevent */
  166. int cts_chkcount; /* too many IRQs if a signal */
  167. int dsr_chkcount; /* is floating */
  168. int ri_chkcount;
  169. int rx_enabled;
  170. int rx_overflow;
  171. int tx_enabled;
  172. int tx_active;
  173. int tx_aborting;
  174. u32 idle_mode;
  175. int if_mode; /* serial interface selection (RS-232, v.35 etc) */
  176. char device_name[25]; /* device instance name */
  177. unsigned int io_base; /* base I/O address of adapter */
  178. unsigned int irq_level;
  179. MGSL_PARAMS params; /* communications parameters */
  180. unsigned char serial_signals; /* current serial signal states */
  181. char irq_occurred; /* for diagnostics use */
  182. char testing_irq;
  183. unsigned int init_error; /* startup error (DIAGS) */
  184. char flag_buf[MAX_ASYNC_BUFFER_SIZE];
  185. BOOLEAN drop_rts_on_tx_done;
  186. struct _input_signal_events input_signal_events;
  187. /* PCMCIA support */
  188. struct pcmcia_device *p_dev;
  189. dev_node_t node;
  190. int stop;
  191. /* SPPP/Cisco HDLC device parts */
  192. int netcount;
  193. int dosyncppp;
  194. spinlock_t netlock;
  195. #ifdef CONFIG_HDLC
  196. struct net_device *netdev;
  197. #endif
  198. } MGSLPC_INFO;
  199. #define MGSLPC_MAGIC 0x5402
  200. /*
  201. * The size of the serial xmit buffer is 1 page, or 4096 bytes
  202. */
  203. #define TXBUFSIZE 4096
  204. #define CHA 0x00 /* channel A offset */
  205. #define CHB 0x40 /* channel B offset */
  206. /*
  207. * FIXME: PPC has PVR defined in asm/reg.h. For now we just undef it.
  208. */
  209. #undef PVR
  210. #define RXFIFO 0
  211. #define TXFIFO 0
  212. #define STAR 0x20
  213. #define CMDR 0x20
  214. #define RSTA 0x21
  215. #define PRE 0x21
  216. #define MODE 0x22
  217. #define TIMR 0x23
  218. #define XAD1 0x24
  219. #define XAD2 0x25
  220. #define RAH1 0x26
  221. #define RAH2 0x27
  222. #define DAFO 0x27
  223. #define RAL1 0x28
  224. #define RFC 0x28
  225. #define RHCR 0x29
  226. #define RAL2 0x29
  227. #define RBCL 0x2a
  228. #define XBCL 0x2a
  229. #define RBCH 0x2b
  230. #define XBCH 0x2b
  231. #define CCR0 0x2c
  232. #define CCR1 0x2d
  233. #define CCR2 0x2e
  234. #define CCR3 0x2f
  235. #define VSTR 0x34
  236. #define BGR 0x34
  237. #define RLCR 0x35
  238. #define AML 0x36
  239. #define AMH 0x37
  240. #define GIS 0x38
  241. #define IVA 0x38
  242. #define IPC 0x39
  243. #define ISR 0x3a
  244. #define IMR 0x3a
  245. #define PVR 0x3c
  246. #define PIS 0x3d
  247. #define PIM 0x3d
  248. #define PCR 0x3e
  249. #define CCR4 0x3f
  250. // IMR/ISR
  251. #define IRQ_BREAK_ON BIT15 // rx break detected
  252. #define IRQ_DATAOVERRUN BIT14 // receive data overflow
  253. #define IRQ_ALLSENT BIT13 // all sent
  254. #define IRQ_UNDERRUN BIT12 // transmit data underrun
  255. #define IRQ_TIMER BIT11 // timer interrupt
  256. #define IRQ_CTS BIT10 // CTS status change
  257. #define IRQ_TXREPEAT BIT9 // tx message repeat
  258. #define IRQ_TXFIFO BIT8 // transmit pool ready
  259. #define IRQ_RXEOM BIT7 // receive message end
  260. #define IRQ_EXITHUNT BIT6 // receive frame start
  261. #define IRQ_RXTIME BIT6 // rx char timeout
  262. #define IRQ_DCD BIT2 // carrier detect status change
  263. #define IRQ_OVERRUN BIT1 // receive frame overflow
  264. #define IRQ_RXFIFO BIT0 // receive pool full
  265. // STAR
  266. #define XFW BIT6 // transmit FIFO write enable
  267. #define CEC BIT2 // command executing
  268. #define CTS BIT1 // CTS state
  269. #define PVR_DTR BIT0
  270. #define PVR_DSR BIT1
  271. #define PVR_RI BIT2
  272. #define PVR_AUTOCTS BIT3
  273. #define PVR_RS232 0x20 /* 0010b */
  274. #define PVR_V35 0xe0 /* 1110b */
  275. #define PVR_RS422 0x40 /* 0100b */
  276. /* Register access functions */
  277. #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
  278. #define read_reg(info, reg) inb((info)->io_base + (reg))
  279. #define read_reg16(info, reg) inw((info)->io_base + (reg))
  280. #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
  281. #define set_reg_bits(info, reg, mask) \
  282. write_reg(info, (reg), \
  283. (unsigned char) (read_reg(info, (reg)) | (mask)))
  284. #define clear_reg_bits(info, reg, mask) \
  285. write_reg(info, (reg), \
  286. (unsigned char) (read_reg(info, (reg)) & ~(mask)))
  287. /*
  288. * interrupt enable/disable routines
  289. */
  290. static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  291. {
  292. if (channel == CHA) {
  293. info->imra_value |= mask;
  294. write_reg16(info, CHA + IMR, info->imra_value);
  295. } else {
  296. info->imrb_value |= mask;
  297. write_reg16(info, CHB + IMR, info->imrb_value);
  298. }
  299. }
  300. static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
  301. {
  302. if (channel == CHA) {
  303. info->imra_value &= ~mask;
  304. write_reg16(info, CHA + IMR, info->imra_value);
  305. } else {
  306. info->imrb_value &= ~mask;
  307. write_reg16(info, CHB + IMR, info->imrb_value);
  308. }
  309. }
  310. #define port_irq_disable(info, mask) \
  311. { info->pim_value |= (mask); write_reg(info, PIM, info->pim_value); }
  312. #define port_irq_enable(info, mask) \
  313. { info->pim_value &= ~(mask); write_reg(info, PIM, info->pim_value); }
  314. static void rx_start(MGSLPC_INFO *info);
  315. static void rx_stop(MGSLPC_INFO *info);
  316. static void tx_start(MGSLPC_INFO *info);
  317. static void tx_stop(MGSLPC_INFO *info);
  318. static void tx_set_idle(MGSLPC_INFO *info);
  319. static void get_signals(MGSLPC_INFO *info);
  320. static void set_signals(MGSLPC_INFO *info);
  321. static void reset_device(MGSLPC_INFO *info);
  322. static void hdlc_mode(MGSLPC_INFO *info);
  323. static void async_mode(MGSLPC_INFO *info);
  324. static void tx_timeout(unsigned long context);
  325. static int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg);
  326. #ifdef CONFIG_HDLC
  327. #define dev_to_port(D) (dev_to_hdlc(D)->priv)
  328. static void hdlcdev_tx_done(MGSLPC_INFO *info);
  329. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size);
  330. static int hdlcdev_init(MGSLPC_INFO *info);
  331. static void hdlcdev_exit(MGSLPC_INFO *info);
  332. #endif
  333. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit);
  334. static BOOLEAN register_test(MGSLPC_INFO *info);
  335. static BOOLEAN irq_test(MGSLPC_INFO *info);
  336. static int adapter_test(MGSLPC_INFO *info);
  337. static int claim_resources(MGSLPC_INFO *info);
  338. static void release_resources(MGSLPC_INFO *info);
  339. static void mgslpc_add_device(MGSLPC_INFO *info);
  340. static void mgslpc_remove_device(MGSLPC_INFO *info);
  341. static int rx_get_frame(MGSLPC_INFO *info);
  342. static void rx_reset_buffers(MGSLPC_INFO *info);
  343. static int rx_alloc_buffers(MGSLPC_INFO *info);
  344. static void rx_free_buffers(MGSLPC_INFO *info);
  345. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs);
  346. /*
  347. * Bottom half interrupt handlers
  348. */
  349. static void bh_handler(void* Context);
  350. static void bh_transmit(MGSLPC_INFO *info);
  351. static void bh_status(MGSLPC_INFO *info);
  352. /*
  353. * ioctl handlers
  354. */
  355. static int tiocmget(struct tty_struct *tty, struct file *file);
  356. static int tiocmset(struct tty_struct *tty, struct file *file,
  357. unsigned int set, unsigned int clear);
  358. static int get_stats(MGSLPC_INFO *info, struct mgsl_icount __user *user_icount);
  359. static int get_params(MGSLPC_INFO *info, MGSL_PARAMS __user *user_params);
  360. static int set_params(MGSLPC_INFO *info, MGSL_PARAMS __user *new_params);
  361. static int get_txidle(MGSLPC_INFO *info, int __user *idle_mode);
  362. static int set_txidle(MGSLPC_INFO *info, int idle_mode);
  363. static int set_txenable(MGSLPC_INFO *info, int enable);
  364. static int tx_abort(MGSLPC_INFO *info);
  365. static int set_rxenable(MGSLPC_INFO *info, int enable);
  366. static int wait_events(MGSLPC_INFO *info, int __user *mask);
  367. static MGSLPC_INFO *mgslpc_device_list = NULL;
  368. static int mgslpc_device_count = 0;
  369. /*
  370. * Set this param to non-zero to load eax with the
  371. * .text section address and breakpoint on module load.
  372. * This is useful for use with gdb and add-symbol-file command.
  373. */
  374. static int break_on_load=0;
  375. /*
  376. * Driver major number, defaults to zero to get auto
  377. * assigned major number. May be forced as module parameter.
  378. */
  379. static int ttymajor=0;
  380. static int debug_level = 0;
  381. static int maxframe[MAX_DEVICE_COUNT] = {0,};
  382. static int dosyncppp[MAX_DEVICE_COUNT] = {1,1,1,1};
  383. module_param(break_on_load, bool, 0);
  384. module_param(ttymajor, int, 0);
  385. module_param(debug_level, int, 0);
  386. module_param_array(maxframe, int, NULL, 0);
  387. module_param_array(dosyncppp, int, NULL, 0);
  388. MODULE_LICENSE("GPL");
  389. static char *driver_name = "SyncLink PC Card driver";
  390. static char *driver_version = "$Revision: 4.34 $";
  391. static struct tty_driver *serial_driver;
  392. /* number of characters left in xmit buffer before we ask for more */
  393. #define WAKEUP_CHARS 256
  394. static void mgslpc_change_params(MGSLPC_INFO *info);
  395. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout);
  396. /* PCMCIA prototypes */
  397. static int mgslpc_config(struct pcmcia_device *link);
  398. static void mgslpc_release(u_long arg);
  399. static void mgslpc_detach(struct pcmcia_device *p_dev);
  400. /*
  401. * 1st function defined in .text section. Calling this function in
  402. * init_module() followed by a breakpoint allows a remote debugger
  403. * (gdb) to get the .text address for the add-symbol-file command.
  404. * This allows remote debugging of dynamically loadable modules.
  405. */
  406. static void* mgslpc_get_text_ptr(void)
  407. {
  408. return mgslpc_get_text_ptr;
  409. }
  410. /**
  411. * line discipline callback wrappers
  412. *
  413. * The wrappers maintain line discipline references
  414. * while calling into the line discipline.
  415. *
  416. * ldisc_flush_buffer - flush line discipline receive buffers
  417. * ldisc_receive_buf - pass receive data to line discipline
  418. */
  419. static void ldisc_flush_buffer(struct tty_struct *tty)
  420. {
  421. struct tty_ldisc *ld = tty_ldisc_ref(tty);
  422. if (ld) {
  423. if (ld->flush_buffer)
  424. ld->flush_buffer(tty);
  425. tty_ldisc_deref(ld);
  426. }
  427. }
  428. static void ldisc_receive_buf(struct tty_struct *tty,
  429. const __u8 *data, char *flags, int count)
  430. {
  431. struct tty_ldisc *ld;
  432. if (!tty)
  433. return;
  434. ld = tty_ldisc_ref(tty);
  435. if (ld) {
  436. if (ld->receive_buf)
  437. ld->receive_buf(tty, data, flags, count);
  438. tty_ldisc_deref(ld);
  439. }
  440. }
  441. static int mgslpc_probe(struct pcmcia_device *link)
  442. {
  443. MGSLPC_INFO *info;
  444. int ret;
  445. if (debug_level >= DEBUG_LEVEL_INFO)
  446. printk("mgslpc_attach\n");
  447. info = (MGSLPC_INFO *)kmalloc(sizeof(MGSLPC_INFO), GFP_KERNEL);
  448. if (!info) {
  449. printk("Error can't allocate device instance data\n");
  450. return -ENOMEM;
  451. }
  452. memset(info, 0, sizeof(MGSLPC_INFO));
  453. info->magic = MGSLPC_MAGIC;
  454. INIT_WORK(&info->task, bh_handler, info);
  455. info->max_frame_size = 4096;
  456. info->close_delay = 5*HZ/10;
  457. info->closing_wait = 30*HZ;
  458. init_waitqueue_head(&info->open_wait);
  459. init_waitqueue_head(&info->close_wait);
  460. init_waitqueue_head(&info->status_event_wait_q);
  461. init_waitqueue_head(&info->event_wait_q);
  462. spin_lock_init(&info->lock);
  463. spin_lock_init(&info->netlock);
  464. memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
  465. info->idle_mode = HDLC_TXIDLE_FLAGS;
  466. info->imra_value = 0xffff;
  467. info->imrb_value = 0xffff;
  468. info->pim_value = 0xff;
  469. info->p_dev = link;
  470. link->priv = info;
  471. /* Initialize the struct pcmcia_device structure */
  472. /* Interrupt setup */
  473. link->irq.Attributes = IRQ_TYPE_EXCLUSIVE;
  474. link->irq.IRQInfo1 = IRQ_LEVEL_ID;
  475. link->irq.Handler = NULL;
  476. link->conf.Attributes = 0;
  477. link->conf.IntType = INT_MEMORY_AND_IO;
  478. ret = mgslpc_config(link);
  479. if (ret)
  480. return ret;
  481. mgslpc_add_device(info);
  482. return 0;
  483. }
  484. /* Card has been inserted.
  485. */
  486. #define CS_CHECK(fn, ret) \
  487. do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
  488. static int mgslpc_config(struct pcmcia_device *link)
  489. {
  490. MGSLPC_INFO *info = link->priv;
  491. tuple_t tuple;
  492. cisparse_t parse;
  493. int last_fn, last_ret;
  494. u_char buf[64];
  495. cistpl_cftable_entry_t dflt = { 0 };
  496. cistpl_cftable_entry_t *cfg;
  497. if (debug_level >= DEBUG_LEVEL_INFO)
  498. printk("mgslpc_config(0x%p)\n", link);
  499. /* read CONFIG tuple to find its configuration registers */
  500. tuple.DesiredTuple = CISTPL_CONFIG;
  501. tuple.Attributes = 0;
  502. tuple.TupleData = buf;
  503. tuple.TupleDataMax = sizeof(buf);
  504. tuple.TupleOffset = 0;
  505. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
  506. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
  507. CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
  508. link->conf.ConfigBase = parse.config.base;
  509. link->conf.Present = parse.config.rmask[0];
  510. /* get CIS configuration entry */
  511. tuple.DesiredTuple = CISTPL_CFTABLE_ENTRY;
  512. CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
  513. cfg = &(parse.cftable_entry);
  514. CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
  515. CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
  516. if (cfg->flags & CISTPL_CFTABLE_DEFAULT) dflt = *cfg;
  517. if (cfg->index == 0)
  518. goto cs_failed;
  519. link->conf.ConfigIndex = cfg->index;
  520. link->conf.Attributes |= CONF_ENABLE_IRQ;
  521. /* IO window settings */
  522. link->io.NumPorts1 = 0;
  523. if ((cfg->io.nwin > 0) || (dflt.io.nwin > 0)) {
  524. cistpl_io_t *io = (cfg->io.nwin) ? &cfg->io : &dflt.io;
  525. link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
  526. if (!(io->flags & CISTPL_IO_8BIT))
  527. link->io.Attributes1 = IO_DATA_PATH_WIDTH_16;
  528. if (!(io->flags & CISTPL_IO_16BIT))
  529. link->io.Attributes1 = IO_DATA_PATH_WIDTH_8;
  530. link->io.IOAddrLines = io->flags & CISTPL_IO_LINES_MASK;
  531. link->io.BasePort1 = io->win[0].base;
  532. link->io.NumPorts1 = io->win[0].len;
  533. CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
  534. }
  535. link->conf.Attributes = CONF_ENABLE_IRQ;
  536. link->conf.IntType = INT_MEMORY_AND_IO;
  537. link->conf.ConfigIndex = 8;
  538. link->conf.Present = PRESENT_OPTION;
  539. link->irq.Attributes |= IRQ_HANDLE_PRESENT;
  540. link->irq.Handler = mgslpc_isr;
  541. link->irq.Instance = info;
  542. CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
  543. CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
  544. info->io_base = link->io.BasePort1;
  545. info->irq_level = link->irq.AssignedIRQ;
  546. /* add to linked list of devices */
  547. sprintf(info->node.dev_name, "mgslpc0");
  548. info->node.major = info->node.minor = 0;
  549. link->dev_node = &info->node;
  550. printk(KERN_INFO "%s: index 0x%02x:",
  551. info->node.dev_name, link->conf.ConfigIndex);
  552. if (link->conf.Attributes & CONF_ENABLE_IRQ)
  553. printk(", irq %d", link->irq.AssignedIRQ);
  554. if (link->io.NumPorts1)
  555. printk(", io 0x%04x-0x%04x", link->io.BasePort1,
  556. link->io.BasePort1+link->io.NumPorts1-1);
  557. printk("\n");
  558. return 0;
  559. cs_failed:
  560. cs_error(link, last_fn, last_ret);
  561. mgslpc_release((u_long)link);
  562. return -ENODEV;
  563. }
  564. /* Card has been removed.
  565. * Unregister device and release PCMCIA configuration.
  566. * If device is open, postpone until it is closed.
  567. */
  568. static void mgslpc_release(u_long arg)
  569. {
  570. struct pcmcia_device *link = (struct pcmcia_device *)arg;
  571. if (debug_level >= DEBUG_LEVEL_INFO)
  572. printk("mgslpc_release(0x%p)\n", link);
  573. pcmcia_disable_device(link);
  574. }
  575. static void mgslpc_detach(struct pcmcia_device *link)
  576. {
  577. if (debug_level >= DEBUG_LEVEL_INFO)
  578. printk("mgslpc_detach(0x%p)\n", link);
  579. ((MGSLPC_INFO *)link->priv)->stop = 1;
  580. mgslpc_release((u_long)link);
  581. mgslpc_remove_device((MGSLPC_INFO *)link->priv);
  582. }
  583. static int mgslpc_suspend(struct pcmcia_device *link)
  584. {
  585. MGSLPC_INFO *info = link->priv;
  586. info->stop = 1;
  587. return 0;
  588. }
  589. static int mgslpc_resume(struct pcmcia_device *link)
  590. {
  591. MGSLPC_INFO *info = link->priv;
  592. info->stop = 0;
  593. return 0;
  594. }
  595. static inline int mgslpc_paranoia_check(MGSLPC_INFO *info,
  596. char *name, const char *routine)
  597. {
  598. #ifdef MGSLPC_PARANOIA_CHECK
  599. static const char *badmagic =
  600. "Warning: bad magic number for mgsl struct (%s) in %s\n";
  601. static const char *badinfo =
  602. "Warning: null mgslpc_info for (%s) in %s\n";
  603. if (!info) {
  604. printk(badinfo, name, routine);
  605. return 1;
  606. }
  607. if (info->magic != MGSLPC_MAGIC) {
  608. printk(badmagic, name, routine);
  609. return 1;
  610. }
  611. #else
  612. if (!info)
  613. return 1;
  614. #endif
  615. return 0;
  616. }
  617. #define CMD_RXFIFO BIT7 // release current rx FIFO
  618. #define CMD_RXRESET BIT6 // receiver reset
  619. #define CMD_RXFIFO_READ BIT5
  620. #define CMD_START_TIMER BIT4
  621. #define CMD_TXFIFO BIT3 // release current tx FIFO
  622. #define CMD_TXEOM BIT1 // transmit end message
  623. #define CMD_TXRESET BIT0 // transmit reset
  624. static BOOLEAN wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
  625. {
  626. int i = 0;
  627. /* wait for command completion */
  628. while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
  629. udelay(1);
  630. if (i++ == 1000)
  631. return FALSE;
  632. }
  633. return TRUE;
  634. }
  635. static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
  636. {
  637. wait_command_complete(info, channel);
  638. write_reg(info, (unsigned char) (channel + CMDR), cmd);
  639. }
  640. static void tx_pause(struct tty_struct *tty)
  641. {
  642. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  643. unsigned long flags;
  644. if (mgslpc_paranoia_check(info, tty->name, "tx_pause"))
  645. return;
  646. if (debug_level >= DEBUG_LEVEL_INFO)
  647. printk("tx_pause(%s)\n",info->device_name);
  648. spin_lock_irqsave(&info->lock,flags);
  649. if (info->tx_enabled)
  650. tx_stop(info);
  651. spin_unlock_irqrestore(&info->lock,flags);
  652. }
  653. static void tx_release(struct tty_struct *tty)
  654. {
  655. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  656. unsigned long flags;
  657. if (mgslpc_paranoia_check(info, tty->name, "tx_release"))
  658. return;
  659. if (debug_level >= DEBUG_LEVEL_INFO)
  660. printk("tx_release(%s)\n",info->device_name);
  661. spin_lock_irqsave(&info->lock,flags);
  662. if (!info->tx_enabled)
  663. tx_start(info);
  664. spin_unlock_irqrestore(&info->lock,flags);
  665. }
  666. /* Return next bottom half action to perform.
  667. * or 0 if nothing to do.
  668. */
  669. static int bh_action(MGSLPC_INFO *info)
  670. {
  671. unsigned long flags;
  672. int rc = 0;
  673. spin_lock_irqsave(&info->lock,flags);
  674. if (info->pending_bh & BH_RECEIVE) {
  675. info->pending_bh &= ~BH_RECEIVE;
  676. rc = BH_RECEIVE;
  677. } else if (info->pending_bh & BH_TRANSMIT) {
  678. info->pending_bh &= ~BH_TRANSMIT;
  679. rc = BH_TRANSMIT;
  680. } else if (info->pending_bh & BH_STATUS) {
  681. info->pending_bh &= ~BH_STATUS;
  682. rc = BH_STATUS;
  683. }
  684. if (!rc) {
  685. /* Mark BH routine as complete */
  686. info->bh_running = 0;
  687. info->bh_requested = 0;
  688. }
  689. spin_unlock_irqrestore(&info->lock,flags);
  690. return rc;
  691. }
  692. static void bh_handler(void* Context)
  693. {
  694. MGSLPC_INFO *info = (MGSLPC_INFO*)Context;
  695. int action;
  696. if (!info)
  697. return;
  698. if (debug_level >= DEBUG_LEVEL_BH)
  699. printk( "%s(%d):bh_handler(%s) entry\n",
  700. __FILE__,__LINE__,info->device_name);
  701. info->bh_running = 1;
  702. while((action = bh_action(info)) != 0) {
  703. /* Process work item */
  704. if ( debug_level >= DEBUG_LEVEL_BH )
  705. printk( "%s(%d):bh_handler() work item action=%d\n",
  706. __FILE__,__LINE__,action);
  707. switch (action) {
  708. case BH_RECEIVE:
  709. while(rx_get_frame(info));
  710. break;
  711. case BH_TRANSMIT:
  712. bh_transmit(info);
  713. break;
  714. case BH_STATUS:
  715. bh_status(info);
  716. break;
  717. default:
  718. /* unknown work item ID */
  719. printk("Unknown work item ID=%08X!\n", action);
  720. break;
  721. }
  722. }
  723. if (debug_level >= DEBUG_LEVEL_BH)
  724. printk( "%s(%d):bh_handler(%s) exit\n",
  725. __FILE__,__LINE__,info->device_name);
  726. }
  727. static void bh_transmit(MGSLPC_INFO *info)
  728. {
  729. struct tty_struct *tty = info->tty;
  730. if (debug_level >= DEBUG_LEVEL_BH)
  731. printk("bh_transmit() entry on %s\n", info->device_name);
  732. if (tty) {
  733. tty_wakeup(tty);
  734. wake_up_interruptible(&tty->write_wait);
  735. }
  736. }
  737. static void bh_status(MGSLPC_INFO *info)
  738. {
  739. info->ri_chkcount = 0;
  740. info->dsr_chkcount = 0;
  741. info->dcd_chkcount = 0;
  742. info->cts_chkcount = 0;
  743. }
  744. /* eom: non-zero = end of frame */
  745. static void rx_ready_hdlc(MGSLPC_INFO *info, int eom)
  746. {
  747. unsigned char data[2];
  748. unsigned char fifo_count, read_count, i;
  749. RXBUF *buf = (RXBUF*)(info->rx_buf + (info->rx_put * info->rx_buf_size));
  750. if (debug_level >= DEBUG_LEVEL_ISR)
  751. printk("%s(%d):rx_ready_hdlc(eom=%d)\n",__FILE__,__LINE__,eom);
  752. if (!info->rx_enabled)
  753. return;
  754. if (info->rx_frame_count >= info->rx_buf_count) {
  755. /* no more free buffers */
  756. issue_command(info, CHA, CMD_RXRESET);
  757. info->pending_bh |= BH_RECEIVE;
  758. info->rx_overflow = 1;
  759. info->icount.buf_overrun++;
  760. return;
  761. }
  762. if (eom) {
  763. /* end of frame, get FIFO count from RBCL register */
  764. if (!(fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f)))
  765. fifo_count = 32;
  766. } else
  767. fifo_count = 32;
  768. do {
  769. if (fifo_count == 1) {
  770. read_count = 1;
  771. data[0] = read_reg(info, CHA + RXFIFO);
  772. } else {
  773. read_count = 2;
  774. *((unsigned short *) data) = read_reg16(info, CHA + RXFIFO);
  775. }
  776. fifo_count -= read_count;
  777. if (!fifo_count && eom)
  778. buf->status = data[--read_count];
  779. for (i = 0; i < read_count; i++) {
  780. if (buf->count >= info->max_frame_size) {
  781. /* frame too large, reset receiver and reset current buffer */
  782. issue_command(info, CHA, CMD_RXRESET);
  783. buf->count = 0;
  784. return;
  785. }
  786. *(buf->data + buf->count) = data[i];
  787. buf->count++;
  788. }
  789. } while (fifo_count);
  790. if (eom) {
  791. info->pending_bh |= BH_RECEIVE;
  792. info->rx_frame_count++;
  793. info->rx_put++;
  794. if (info->rx_put >= info->rx_buf_count)
  795. info->rx_put = 0;
  796. }
  797. issue_command(info, CHA, CMD_RXFIFO);
  798. }
  799. static void rx_ready_async(MGSLPC_INFO *info, int tcd)
  800. {
  801. unsigned char data, status, flag;
  802. int fifo_count;
  803. int work = 0;
  804. struct tty_struct *tty = info->tty;
  805. struct mgsl_icount *icount = &info->icount;
  806. if (tcd) {
  807. /* early termination, get FIFO count from RBCL register */
  808. fifo_count = (unsigned char)(read_reg(info, CHA+RBCL) & 0x1f);
  809. /* Zero fifo count could mean 0 or 32 bytes available.
  810. * If BIT5 of STAR is set then at least 1 byte is available.
  811. */
  812. if (!fifo_count && (read_reg(info,CHA+STAR) & BIT5))
  813. fifo_count = 32;
  814. } else
  815. fifo_count = 32;
  816. tty_buffer_request_room(tty, fifo_count);
  817. /* Flush received async data to receive data buffer. */
  818. while (fifo_count) {
  819. data = read_reg(info, CHA + RXFIFO);
  820. status = read_reg(info, CHA + RXFIFO);
  821. fifo_count -= 2;
  822. icount->rx++;
  823. flag = TTY_NORMAL;
  824. // if no frameing/crc error then save data
  825. // BIT7:parity error
  826. // BIT6:framing error
  827. if (status & (BIT7 + BIT6)) {
  828. if (status & BIT7)
  829. icount->parity++;
  830. else
  831. icount->frame++;
  832. /* discard char if tty control flags say so */
  833. if (status & info->ignore_status_mask)
  834. continue;
  835. status &= info->read_status_mask;
  836. if (status & BIT7)
  837. flag = TTY_PARITY;
  838. else if (status & BIT6)
  839. flag = TTY_FRAME;
  840. }
  841. work += tty_insert_flip_char(tty, data, flag);
  842. }
  843. issue_command(info, CHA, CMD_RXFIFO);
  844. if (debug_level >= DEBUG_LEVEL_ISR) {
  845. printk("%s(%d):rx_ready_async",
  846. __FILE__,__LINE__);
  847. printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
  848. __FILE__,__LINE__,icount->rx,icount->brk,
  849. icount->parity,icount->frame,icount->overrun);
  850. }
  851. if (work)
  852. tty_flip_buffer_push(tty);
  853. }
  854. static void tx_done(MGSLPC_INFO *info)
  855. {
  856. if (!info->tx_active)
  857. return;
  858. info->tx_active = 0;
  859. info->tx_aborting = 0;
  860. if (info->params.mode == MGSL_MODE_ASYNC)
  861. return;
  862. info->tx_count = info->tx_put = info->tx_get = 0;
  863. del_timer(&info->tx_timer);
  864. if (info->drop_rts_on_tx_done) {
  865. get_signals(info);
  866. if (info->serial_signals & SerialSignal_RTS) {
  867. info->serial_signals &= ~SerialSignal_RTS;
  868. set_signals(info);
  869. }
  870. info->drop_rts_on_tx_done = 0;
  871. }
  872. #ifdef CONFIG_HDLC
  873. if (info->netcount)
  874. hdlcdev_tx_done(info);
  875. else
  876. #endif
  877. {
  878. if (info->tty->stopped || info->tty->hw_stopped) {
  879. tx_stop(info);
  880. return;
  881. }
  882. info->pending_bh |= BH_TRANSMIT;
  883. }
  884. }
  885. static void tx_ready(MGSLPC_INFO *info)
  886. {
  887. unsigned char fifo_count = 32;
  888. int c;
  889. if (debug_level >= DEBUG_LEVEL_ISR)
  890. printk("%s(%d):tx_ready(%s)\n", __FILE__,__LINE__,info->device_name);
  891. if (info->params.mode == MGSL_MODE_HDLC) {
  892. if (!info->tx_active)
  893. return;
  894. } else {
  895. if (info->tty->stopped || info->tty->hw_stopped) {
  896. tx_stop(info);
  897. return;
  898. }
  899. if (!info->tx_count)
  900. info->tx_active = 0;
  901. }
  902. if (!info->tx_count)
  903. return;
  904. while (info->tx_count && fifo_count) {
  905. c = min(2, min_t(int, fifo_count, min(info->tx_count, TXBUFSIZE - info->tx_get)));
  906. if (c == 1) {
  907. write_reg(info, CHA + TXFIFO, *(info->tx_buf + info->tx_get));
  908. } else {
  909. write_reg16(info, CHA + TXFIFO,
  910. *((unsigned short*)(info->tx_buf + info->tx_get)));
  911. }
  912. info->tx_count -= c;
  913. info->tx_get = (info->tx_get + c) & (TXBUFSIZE - 1);
  914. fifo_count -= c;
  915. }
  916. if (info->params.mode == MGSL_MODE_ASYNC) {
  917. if (info->tx_count < WAKEUP_CHARS)
  918. info->pending_bh |= BH_TRANSMIT;
  919. issue_command(info, CHA, CMD_TXFIFO);
  920. } else {
  921. if (info->tx_count)
  922. issue_command(info, CHA, CMD_TXFIFO);
  923. else
  924. issue_command(info, CHA, CMD_TXFIFO + CMD_TXEOM);
  925. }
  926. }
  927. static void cts_change(MGSLPC_INFO *info)
  928. {
  929. get_signals(info);
  930. if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  931. irq_disable(info, CHB, IRQ_CTS);
  932. info->icount.cts++;
  933. if (info->serial_signals & SerialSignal_CTS)
  934. info->input_signal_events.cts_up++;
  935. else
  936. info->input_signal_events.cts_down++;
  937. wake_up_interruptible(&info->status_event_wait_q);
  938. wake_up_interruptible(&info->event_wait_q);
  939. if (info->flags & ASYNC_CTS_FLOW) {
  940. if (info->tty->hw_stopped) {
  941. if (info->serial_signals & SerialSignal_CTS) {
  942. if (debug_level >= DEBUG_LEVEL_ISR)
  943. printk("CTS tx start...");
  944. if (info->tty)
  945. info->tty->hw_stopped = 0;
  946. tx_start(info);
  947. info->pending_bh |= BH_TRANSMIT;
  948. return;
  949. }
  950. } else {
  951. if (!(info->serial_signals & SerialSignal_CTS)) {
  952. if (debug_level >= DEBUG_LEVEL_ISR)
  953. printk("CTS tx stop...");
  954. if (info->tty)
  955. info->tty->hw_stopped = 1;
  956. tx_stop(info);
  957. }
  958. }
  959. }
  960. info->pending_bh |= BH_STATUS;
  961. }
  962. static void dcd_change(MGSLPC_INFO *info)
  963. {
  964. get_signals(info);
  965. if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  966. irq_disable(info, CHB, IRQ_DCD);
  967. info->icount.dcd++;
  968. if (info->serial_signals & SerialSignal_DCD) {
  969. info->input_signal_events.dcd_up++;
  970. }
  971. else
  972. info->input_signal_events.dcd_down++;
  973. #ifdef CONFIG_HDLC
  974. if (info->netcount) {
  975. if (info->serial_signals & SerialSignal_DCD)
  976. netif_carrier_on(info->netdev);
  977. else
  978. netif_carrier_off(info->netdev);
  979. }
  980. #endif
  981. wake_up_interruptible(&info->status_event_wait_q);
  982. wake_up_interruptible(&info->event_wait_q);
  983. if (info->flags & ASYNC_CHECK_CD) {
  984. if (debug_level >= DEBUG_LEVEL_ISR)
  985. printk("%s CD now %s...", info->device_name,
  986. (info->serial_signals & SerialSignal_DCD) ? "on" : "off");
  987. if (info->serial_signals & SerialSignal_DCD)
  988. wake_up_interruptible(&info->open_wait);
  989. else {
  990. if (debug_level >= DEBUG_LEVEL_ISR)
  991. printk("doing serial hangup...");
  992. if (info->tty)
  993. tty_hangup(info->tty);
  994. }
  995. }
  996. info->pending_bh |= BH_STATUS;
  997. }
  998. static void dsr_change(MGSLPC_INFO *info)
  999. {
  1000. get_signals(info);
  1001. if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1002. port_irq_disable(info, PVR_DSR);
  1003. info->icount.dsr++;
  1004. if (info->serial_signals & SerialSignal_DSR)
  1005. info->input_signal_events.dsr_up++;
  1006. else
  1007. info->input_signal_events.dsr_down++;
  1008. wake_up_interruptible(&info->status_event_wait_q);
  1009. wake_up_interruptible(&info->event_wait_q);
  1010. info->pending_bh |= BH_STATUS;
  1011. }
  1012. static void ri_change(MGSLPC_INFO *info)
  1013. {
  1014. get_signals(info);
  1015. if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
  1016. port_irq_disable(info, PVR_RI);
  1017. info->icount.rng++;
  1018. if (info->serial_signals & SerialSignal_RI)
  1019. info->input_signal_events.ri_up++;
  1020. else
  1021. info->input_signal_events.ri_down++;
  1022. wake_up_interruptible(&info->status_event_wait_q);
  1023. wake_up_interruptible(&info->event_wait_q);
  1024. info->pending_bh |= BH_STATUS;
  1025. }
  1026. /* Interrupt service routine entry point.
  1027. *
  1028. * Arguments:
  1029. *
  1030. * irq interrupt number that caused interrupt
  1031. * dev_id device ID supplied during interrupt registration
  1032. * regs interrupted processor context
  1033. */
  1034. static irqreturn_t mgslpc_isr(int irq, void *dev_id, struct pt_regs * regs)
  1035. {
  1036. MGSLPC_INFO * info = (MGSLPC_INFO *)dev_id;
  1037. unsigned short isr;
  1038. unsigned char gis, pis;
  1039. int count=0;
  1040. if (debug_level >= DEBUG_LEVEL_ISR)
  1041. printk("mgslpc_isr(%d) entry.\n", irq);
  1042. if (!info)
  1043. return IRQ_NONE;
  1044. if (!(info->p_dev->_locked))
  1045. return IRQ_HANDLED;
  1046. spin_lock(&info->lock);
  1047. while ((gis = read_reg(info, CHA + GIS))) {
  1048. if (debug_level >= DEBUG_LEVEL_ISR)
  1049. printk("mgslpc_isr %s gis=%04X\n", info->device_name,gis);
  1050. if ((gis & 0x70) || count > 1000) {
  1051. printk("synclink_cs:hardware failed or ejected\n");
  1052. break;
  1053. }
  1054. count++;
  1055. if (gis & (BIT1 + BIT0)) {
  1056. isr = read_reg16(info, CHB + ISR);
  1057. if (isr & IRQ_DCD)
  1058. dcd_change(info);
  1059. if (isr & IRQ_CTS)
  1060. cts_change(info);
  1061. }
  1062. if (gis & (BIT3 + BIT2))
  1063. {
  1064. isr = read_reg16(info, CHA + ISR);
  1065. if (isr & IRQ_TIMER) {
  1066. info->irq_occurred = 1;
  1067. irq_disable(info, CHA, IRQ_TIMER);
  1068. }
  1069. /* receive IRQs */
  1070. if (isr & IRQ_EXITHUNT) {
  1071. info->icount.exithunt++;
  1072. wake_up_interruptible(&info->event_wait_q);
  1073. }
  1074. if (isr & IRQ_BREAK_ON) {
  1075. info->icount.brk++;
  1076. if (info->flags & ASYNC_SAK)
  1077. do_SAK(info->tty);
  1078. }
  1079. if (isr & IRQ_RXTIME) {
  1080. issue_command(info, CHA, CMD_RXFIFO_READ);
  1081. }
  1082. if (isr & (IRQ_RXEOM + IRQ_RXFIFO)) {
  1083. if (info->params.mode == MGSL_MODE_HDLC)
  1084. rx_ready_hdlc(info, isr & IRQ_RXEOM);
  1085. else
  1086. rx_ready_async(info, isr & IRQ_RXEOM);
  1087. }
  1088. /* transmit IRQs */
  1089. if (isr & IRQ_UNDERRUN) {
  1090. if (info->tx_aborting)
  1091. info->icount.txabort++;
  1092. else
  1093. info->icount.txunder++;
  1094. tx_done(info);
  1095. }
  1096. else if (isr & IRQ_ALLSENT) {
  1097. info->icount.txok++;
  1098. tx_done(info);
  1099. }
  1100. else if (isr & IRQ_TXFIFO)
  1101. tx_ready(info);
  1102. }
  1103. if (gis & BIT7) {
  1104. pis = read_reg(info, CHA + PIS);
  1105. if (pis & BIT1)
  1106. dsr_change(info);
  1107. if (pis & BIT2)
  1108. ri_change(info);
  1109. }
  1110. }
  1111. /* Request bottom half processing if there's something
  1112. * for it to do and the bh is not already running
  1113. */
  1114. if (info->pending_bh && !info->bh_running && !info->bh_requested) {
  1115. if ( debug_level >= DEBUG_LEVEL_ISR )
  1116. printk("%s(%d):%s queueing bh task.\n",
  1117. __FILE__,__LINE__,info->device_name);
  1118. schedule_work(&info->task);
  1119. info->bh_requested = 1;
  1120. }
  1121. spin_unlock(&info->lock);
  1122. if (debug_level >= DEBUG_LEVEL_ISR)
  1123. printk("%s(%d):mgslpc_isr(%d)exit.\n",
  1124. __FILE__,__LINE__,irq);
  1125. return IRQ_HANDLED;
  1126. }
  1127. /* Initialize and start device.
  1128. */
  1129. static int startup(MGSLPC_INFO * info)
  1130. {
  1131. int retval = 0;
  1132. if (debug_level >= DEBUG_LEVEL_INFO)
  1133. printk("%s(%d):startup(%s)\n",__FILE__,__LINE__,info->device_name);
  1134. if (info->flags & ASYNC_INITIALIZED)
  1135. return 0;
  1136. if (!info->tx_buf) {
  1137. /* allocate a page of memory for a transmit buffer */
  1138. info->tx_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
  1139. if (!info->tx_buf) {
  1140. printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
  1141. __FILE__,__LINE__,info->device_name);
  1142. return -ENOMEM;
  1143. }
  1144. }
  1145. info->pending_bh = 0;
  1146. memset(&info->icount, 0, sizeof(info->icount));
  1147. init_timer(&info->tx_timer);
  1148. info->tx_timer.data = (unsigned long)info;
  1149. info->tx_timer.function = tx_timeout;
  1150. /* Allocate and claim adapter resources */
  1151. retval = claim_resources(info);
  1152. /* perform existance check and diagnostics */
  1153. if ( !retval )
  1154. retval = adapter_test(info);
  1155. if ( retval ) {
  1156. if (capable(CAP_SYS_ADMIN) && info->tty)
  1157. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1158. release_resources(info);
  1159. return retval;
  1160. }
  1161. /* program hardware for current parameters */
  1162. mgslpc_change_params(info);
  1163. if (info->tty)
  1164. clear_bit(TTY_IO_ERROR, &info->tty->flags);
  1165. info->flags |= ASYNC_INITIALIZED;
  1166. return 0;
  1167. }
  1168. /* Called by mgslpc_close() and mgslpc_hangup() to shutdown hardware
  1169. */
  1170. static void shutdown(MGSLPC_INFO * info)
  1171. {
  1172. unsigned long flags;
  1173. if (!(info->flags & ASYNC_INITIALIZED))
  1174. return;
  1175. if (debug_level >= DEBUG_LEVEL_INFO)
  1176. printk("%s(%d):mgslpc_shutdown(%s)\n",
  1177. __FILE__,__LINE__, info->device_name );
  1178. /* clear status wait queue because status changes */
  1179. /* can't happen after shutting down the hardware */
  1180. wake_up_interruptible(&info->status_event_wait_q);
  1181. wake_up_interruptible(&info->event_wait_q);
  1182. del_timer(&info->tx_timer);
  1183. if (info->tx_buf) {
  1184. free_page((unsigned long) info->tx_buf);
  1185. info->tx_buf = NULL;
  1186. }
  1187. spin_lock_irqsave(&info->lock,flags);
  1188. rx_stop(info);
  1189. tx_stop(info);
  1190. /* TODO:disable interrupts instead of reset to preserve signal states */
  1191. reset_device(info);
  1192. if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
  1193. info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
  1194. set_signals(info);
  1195. }
  1196. spin_unlock_irqrestore(&info->lock,flags);
  1197. release_resources(info);
  1198. if (info->tty)
  1199. set_bit(TTY_IO_ERROR, &info->tty->flags);
  1200. info->flags &= ~ASYNC_INITIALIZED;
  1201. }
  1202. static void mgslpc_program_hw(MGSLPC_INFO *info)
  1203. {
  1204. unsigned long flags;
  1205. spin_lock_irqsave(&info->lock,flags);
  1206. rx_stop(info);
  1207. tx_stop(info);
  1208. info->tx_count = info->tx_put = info->tx_get = 0;
  1209. if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
  1210. hdlc_mode(info);
  1211. else
  1212. async_mode(info);
  1213. set_signals(info);
  1214. info->dcd_chkcount = 0;
  1215. info->cts_chkcount = 0;
  1216. info->ri_chkcount = 0;
  1217. info->dsr_chkcount = 0;
  1218. irq_enable(info, CHB, IRQ_DCD | IRQ_CTS);
  1219. port_irq_enable(info, (unsigned char) PVR_DSR | PVR_RI);
  1220. get_signals(info);
  1221. if (info->netcount || info->tty->termios->c_cflag & CREAD)
  1222. rx_start(info);
  1223. spin_unlock_irqrestore(&info->lock,flags);
  1224. }
  1225. /* Reconfigure adapter based on new parameters
  1226. */
  1227. static void mgslpc_change_params(MGSLPC_INFO *info)
  1228. {
  1229. unsigned cflag;
  1230. int bits_per_char;
  1231. if (!info->tty || !info->tty->termios)
  1232. return;
  1233. if (debug_level >= DEBUG_LEVEL_INFO)
  1234. printk("%s(%d):mgslpc_change_params(%s)\n",
  1235. __FILE__,__LINE__, info->device_name );
  1236. cflag = info->tty->termios->c_cflag;
  1237. /* if B0 rate (hangup) specified then negate DTR and RTS */
  1238. /* otherwise assert DTR and RTS */
  1239. if (cflag & CBAUD)
  1240. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  1241. else
  1242. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  1243. /* byte size and parity */
  1244. switch (cflag & CSIZE) {
  1245. case CS5: info->params.data_bits = 5; break;
  1246. case CS6: info->params.data_bits = 6; break;
  1247. case CS7: info->params.data_bits = 7; break;
  1248. case CS8: info->params.data_bits = 8; break;
  1249. default: info->params.data_bits = 7; break;
  1250. }
  1251. if (cflag & CSTOPB)
  1252. info->params.stop_bits = 2;
  1253. else
  1254. info->params.stop_bits = 1;
  1255. info->params.parity = ASYNC_PARITY_NONE;
  1256. if (cflag & PARENB) {
  1257. if (cflag & PARODD)
  1258. info->params.parity = ASYNC_PARITY_ODD;
  1259. else
  1260. info->params.parity = ASYNC_PARITY_EVEN;
  1261. #ifdef CMSPAR
  1262. if (cflag & CMSPAR)
  1263. info->params.parity = ASYNC_PARITY_SPACE;
  1264. #endif
  1265. }
  1266. /* calculate number of jiffies to transmit a full
  1267. * FIFO (32 bytes) at specified data rate
  1268. */
  1269. bits_per_char = info->params.data_bits +
  1270. info->params.stop_bits + 1;
  1271. /* if port data rate is set to 460800 or less then
  1272. * allow tty settings to override, otherwise keep the
  1273. * current data rate.
  1274. */
  1275. if (info->params.data_rate <= 460800) {
  1276. info->params.data_rate = tty_get_baud_rate(info->tty);
  1277. }
  1278. if ( info->params.data_rate ) {
  1279. info->timeout = (32*HZ*bits_per_char) /
  1280. info->params.data_rate;
  1281. }
  1282. info->timeout += HZ/50; /* Add .02 seconds of slop */
  1283. if (cflag & CRTSCTS)
  1284. info->flags |= ASYNC_CTS_FLOW;
  1285. else
  1286. info->flags &= ~ASYNC_CTS_FLOW;
  1287. if (cflag & CLOCAL)
  1288. info->flags &= ~ASYNC_CHECK_CD;
  1289. else
  1290. info->flags |= ASYNC_CHECK_CD;
  1291. /* process tty input control flags */
  1292. info->read_status_mask = 0;
  1293. if (I_INPCK(info->tty))
  1294. info->read_status_mask |= BIT7 | BIT6;
  1295. if (I_IGNPAR(info->tty))
  1296. info->ignore_status_mask |= BIT7 | BIT6;
  1297. mgslpc_program_hw(info);
  1298. }
  1299. /* Add a character to the transmit buffer
  1300. */
  1301. static void mgslpc_put_char(struct tty_struct *tty, unsigned char ch)
  1302. {
  1303. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1304. unsigned long flags;
  1305. if (debug_level >= DEBUG_LEVEL_INFO) {
  1306. printk( "%s(%d):mgslpc_put_char(%d) on %s\n",
  1307. __FILE__,__LINE__,ch,info->device_name);
  1308. }
  1309. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_put_char"))
  1310. return;
  1311. if (!info->tx_buf)
  1312. return;
  1313. spin_lock_irqsave(&info->lock,flags);
  1314. if (info->params.mode == MGSL_MODE_ASYNC || !info->tx_active) {
  1315. if (info->tx_count < TXBUFSIZE - 1) {
  1316. info->tx_buf[info->tx_put++] = ch;
  1317. info->tx_put &= TXBUFSIZE-1;
  1318. info->tx_count++;
  1319. }
  1320. }
  1321. spin_unlock_irqrestore(&info->lock,flags);
  1322. }
  1323. /* Enable transmitter so remaining characters in the
  1324. * transmit buffer are sent.
  1325. */
  1326. static void mgslpc_flush_chars(struct tty_struct *tty)
  1327. {
  1328. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1329. unsigned long flags;
  1330. if (debug_level >= DEBUG_LEVEL_INFO)
  1331. printk( "%s(%d):mgslpc_flush_chars() entry on %s tx_count=%d\n",
  1332. __FILE__,__LINE__,info->device_name,info->tx_count);
  1333. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_chars"))
  1334. return;
  1335. if (info->tx_count <= 0 || tty->stopped ||
  1336. tty->hw_stopped || !info->tx_buf)
  1337. return;
  1338. if (debug_level >= DEBUG_LEVEL_INFO)
  1339. printk( "%s(%d):mgslpc_flush_chars() entry on %s starting transmitter\n",
  1340. __FILE__,__LINE__,info->device_name);
  1341. spin_lock_irqsave(&info->lock,flags);
  1342. if (!info->tx_active)
  1343. tx_start(info);
  1344. spin_unlock_irqrestore(&info->lock,flags);
  1345. }
  1346. /* Send a block of data
  1347. *
  1348. * Arguments:
  1349. *
  1350. * tty pointer to tty information structure
  1351. * buf pointer to buffer containing send data
  1352. * count size of send data in bytes
  1353. *
  1354. * Returns: number of characters written
  1355. */
  1356. static int mgslpc_write(struct tty_struct * tty,
  1357. const unsigned char *buf, int count)
  1358. {
  1359. int c, ret = 0;
  1360. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1361. unsigned long flags;
  1362. if (debug_level >= DEBUG_LEVEL_INFO)
  1363. printk( "%s(%d):mgslpc_write(%s) count=%d\n",
  1364. __FILE__,__LINE__,info->device_name,count);
  1365. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write") ||
  1366. !info->tx_buf)
  1367. goto cleanup;
  1368. if (info->params.mode == MGSL_MODE_HDLC) {
  1369. if (count > TXBUFSIZE) {
  1370. ret = -EIO;
  1371. goto cleanup;
  1372. }
  1373. if (info->tx_active)
  1374. goto cleanup;
  1375. else if (info->tx_count)
  1376. goto start;
  1377. }
  1378. for (;;) {
  1379. c = min(count,
  1380. min(TXBUFSIZE - info->tx_count - 1,
  1381. TXBUFSIZE - info->tx_put));
  1382. if (c <= 0)
  1383. break;
  1384. memcpy(info->tx_buf + info->tx_put, buf, c);
  1385. spin_lock_irqsave(&info->lock,flags);
  1386. info->tx_put = (info->tx_put + c) & (TXBUFSIZE-1);
  1387. info->tx_count += c;
  1388. spin_unlock_irqrestore(&info->lock,flags);
  1389. buf += c;
  1390. count -= c;
  1391. ret += c;
  1392. }
  1393. start:
  1394. if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
  1395. spin_lock_irqsave(&info->lock,flags);
  1396. if (!info->tx_active)
  1397. tx_start(info);
  1398. spin_unlock_irqrestore(&info->lock,flags);
  1399. }
  1400. cleanup:
  1401. if (debug_level >= DEBUG_LEVEL_INFO)
  1402. printk( "%s(%d):mgslpc_write(%s) returning=%d\n",
  1403. __FILE__,__LINE__,info->device_name,ret);
  1404. return ret;
  1405. }
  1406. /* Return the count of free bytes in transmit buffer
  1407. */
  1408. static int mgslpc_write_room(struct tty_struct *tty)
  1409. {
  1410. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1411. int ret;
  1412. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_write_room"))
  1413. return 0;
  1414. if (info->params.mode == MGSL_MODE_HDLC) {
  1415. /* HDLC (frame oriented) mode */
  1416. if (info->tx_active)
  1417. return 0;
  1418. else
  1419. return HDLC_MAX_FRAME_SIZE;
  1420. } else {
  1421. ret = TXBUFSIZE - info->tx_count - 1;
  1422. if (ret < 0)
  1423. ret = 0;
  1424. }
  1425. if (debug_level >= DEBUG_LEVEL_INFO)
  1426. printk("%s(%d):mgslpc_write_room(%s)=%d\n",
  1427. __FILE__,__LINE__, info->device_name, ret);
  1428. return ret;
  1429. }
  1430. /* Return the count of bytes in transmit buffer
  1431. */
  1432. static int mgslpc_chars_in_buffer(struct tty_struct *tty)
  1433. {
  1434. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1435. int rc;
  1436. if (debug_level >= DEBUG_LEVEL_INFO)
  1437. printk("%s(%d):mgslpc_chars_in_buffer(%s)\n",
  1438. __FILE__,__LINE__, info->device_name );
  1439. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_chars_in_buffer"))
  1440. return 0;
  1441. if (info->params.mode == MGSL_MODE_HDLC)
  1442. rc = info->tx_active ? info->max_frame_size : 0;
  1443. else
  1444. rc = info->tx_count;
  1445. if (debug_level >= DEBUG_LEVEL_INFO)
  1446. printk("%s(%d):mgslpc_chars_in_buffer(%s)=%d\n",
  1447. __FILE__,__LINE__, info->device_name, rc);
  1448. return rc;
  1449. }
  1450. /* Discard all data in the send buffer
  1451. */
  1452. static void mgslpc_flush_buffer(struct tty_struct *tty)
  1453. {
  1454. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1455. unsigned long flags;
  1456. if (debug_level >= DEBUG_LEVEL_INFO)
  1457. printk("%s(%d):mgslpc_flush_buffer(%s) entry\n",
  1458. __FILE__,__LINE__, info->device_name );
  1459. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_flush_buffer"))
  1460. return;
  1461. spin_lock_irqsave(&info->lock,flags);
  1462. info->tx_count = info->tx_put = info->tx_get = 0;
  1463. del_timer(&info->tx_timer);
  1464. spin_unlock_irqrestore(&info->lock,flags);
  1465. wake_up_interruptible(&tty->write_wait);
  1466. tty_wakeup(tty);
  1467. }
  1468. /* Send a high-priority XON/XOFF character
  1469. */
  1470. static void mgslpc_send_xchar(struct tty_struct *tty, char ch)
  1471. {
  1472. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1473. unsigned long flags;
  1474. if (debug_level >= DEBUG_LEVEL_INFO)
  1475. printk("%s(%d):mgslpc_send_xchar(%s,%d)\n",
  1476. __FILE__,__LINE__, info->device_name, ch );
  1477. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_send_xchar"))
  1478. return;
  1479. info->x_char = ch;
  1480. if (ch) {
  1481. spin_lock_irqsave(&info->lock,flags);
  1482. if (!info->tx_enabled)
  1483. tx_start(info);
  1484. spin_unlock_irqrestore(&info->lock,flags);
  1485. }
  1486. }
  1487. /* Signal remote device to throttle send data (our receive data)
  1488. */
  1489. static void mgslpc_throttle(struct tty_struct * tty)
  1490. {
  1491. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1492. unsigned long flags;
  1493. if (debug_level >= DEBUG_LEVEL_INFO)
  1494. printk("%s(%d):mgslpc_throttle(%s) entry\n",
  1495. __FILE__,__LINE__, info->device_name );
  1496. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_throttle"))
  1497. return;
  1498. if (I_IXOFF(tty))
  1499. mgslpc_send_xchar(tty, STOP_CHAR(tty));
  1500. if (tty->termios->c_cflag & CRTSCTS) {
  1501. spin_lock_irqsave(&info->lock,flags);
  1502. info->serial_signals &= ~SerialSignal_RTS;
  1503. set_signals(info);
  1504. spin_unlock_irqrestore(&info->lock,flags);
  1505. }
  1506. }
  1507. /* Signal remote device to stop throttling send data (our receive data)
  1508. */
  1509. static void mgslpc_unthrottle(struct tty_struct * tty)
  1510. {
  1511. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1512. unsigned long flags;
  1513. if (debug_level >= DEBUG_LEVEL_INFO)
  1514. printk("%s(%d):mgslpc_unthrottle(%s) entry\n",
  1515. __FILE__,__LINE__, info->device_name );
  1516. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_unthrottle"))
  1517. return;
  1518. if (I_IXOFF(tty)) {
  1519. if (info->x_char)
  1520. info->x_char = 0;
  1521. else
  1522. mgslpc_send_xchar(tty, START_CHAR(tty));
  1523. }
  1524. if (tty->termios->c_cflag & CRTSCTS) {
  1525. spin_lock_irqsave(&info->lock,flags);
  1526. info->serial_signals |= SerialSignal_RTS;
  1527. set_signals(info);
  1528. spin_unlock_irqrestore(&info->lock,flags);
  1529. }
  1530. }
  1531. /* get the current serial statistics
  1532. */
  1533. static int get_stats(MGSLPC_INFO * info, struct mgsl_icount __user *user_icount)
  1534. {
  1535. int err;
  1536. if (debug_level >= DEBUG_LEVEL_INFO)
  1537. printk("get_params(%s)\n", info->device_name);
  1538. if (!user_icount) {
  1539. memset(&info->icount, 0, sizeof(info->icount));
  1540. } else {
  1541. COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
  1542. if (err)
  1543. return -EFAULT;
  1544. }
  1545. return 0;
  1546. }
  1547. /* get the current serial parameters
  1548. */
  1549. static int get_params(MGSLPC_INFO * info, MGSL_PARAMS __user *user_params)
  1550. {
  1551. int err;
  1552. if (debug_level >= DEBUG_LEVEL_INFO)
  1553. printk("get_params(%s)\n", info->device_name);
  1554. COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
  1555. if (err)
  1556. return -EFAULT;
  1557. return 0;
  1558. }
  1559. /* set the serial parameters
  1560. *
  1561. * Arguments:
  1562. *
  1563. * info pointer to device instance data
  1564. * new_params user buffer containing new serial params
  1565. *
  1566. * Returns: 0 if success, otherwise error code
  1567. */
  1568. static int set_params(MGSLPC_INFO * info, MGSL_PARAMS __user *new_params)
  1569. {
  1570. unsigned long flags;
  1571. MGSL_PARAMS tmp_params;
  1572. int err;
  1573. if (debug_level >= DEBUG_LEVEL_INFO)
  1574. printk("%s(%d):set_params %s\n", __FILE__,__LINE__,
  1575. info->device_name );
  1576. COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
  1577. if (err) {
  1578. if ( debug_level >= DEBUG_LEVEL_INFO )
  1579. printk( "%s(%d):set_params(%s) user buffer copy failed\n",
  1580. __FILE__,__LINE__,info->device_name);
  1581. return -EFAULT;
  1582. }
  1583. spin_lock_irqsave(&info->lock,flags);
  1584. memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
  1585. spin_unlock_irqrestore(&info->lock,flags);
  1586. mgslpc_change_params(info);
  1587. return 0;
  1588. }
  1589. static int get_txidle(MGSLPC_INFO * info, int __user *idle_mode)
  1590. {
  1591. int err;
  1592. if (debug_level >= DEBUG_LEVEL_INFO)
  1593. printk("get_txidle(%s)=%d\n", info->device_name, info->idle_mode);
  1594. COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
  1595. if (err)
  1596. return -EFAULT;
  1597. return 0;
  1598. }
  1599. static int set_txidle(MGSLPC_INFO * info, int idle_mode)
  1600. {
  1601. unsigned long flags;
  1602. if (debug_level >= DEBUG_LEVEL_INFO)
  1603. printk("set_txidle(%s,%d)\n", info->device_name, idle_mode);
  1604. spin_lock_irqsave(&info->lock,flags);
  1605. info->idle_mode = idle_mode;
  1606. tx_set_idle(info);
  1607. spin_unlock_irqrestore(&info->lock,flags);
  1608. return 0;
  1609. }
  1610. static int get_interface(MGSLPC_INFO * info, int __user *if_mode)
  1611. {
  1612. int err;
  1613. if (debug_level >= DEBUG_LEVEL_INFO)
  1614. printk("get_interface(%s)=%d\n", info->device_name, info->if_mode);
  1615. COPY_TO_USER(err,if_mode, &info->if_mode, sizeof(int));
  1616. if (err)
  1617. return -EFAULT;
  1618. return 0;
  1619. }
  1620. static int set_interface(MGSLPC_INFO * info, int if_mode)
  1621. {
  1622. unsigned long flags;
  1623. unsigned char val;
  1624. if (debug_level >= DEBUG_LEVEL_INFO)
  1625. printk("set_interface(%s,%d)\n", info->device_name, if_mode);
  1626. spin_lock_irqsave(&info->lock,flags);
  1627. info->if_mode = if_mode;
  1628. val = read_reg(info, PVR) & 0x0f;
  1629. switch (info->if_mode)
  1630. {
  1631. case MGSL_INTERFACE_RS232: val |= PVR_RS232; break;
  1632. case MGSL_INTERFACE_V35: val |= PVR_V35; break;
  1633. case MGSL_INTERFACE_RS422: val |= PVR_RS422; break;
  1634. }
  1635. write_reg(info, PVR, val);
  1636. spin_unlock_irqrestore(&info->lock,flags);
  1637. return 0;
  1638. }
  1639. static int set_txenable(MGSLPC_INFO * info, int enable)
  1640. {
  1641. unsigned long flags;
  1642. if (debug_level >= DEBUG_LEVEL_INFO)
  1643. printk("set_txenable(%s,%d)\n", info->device_name, enable);
  1644. spin_lock_irqsave(&info->lock,flags);
  1645. if (enable) {
  1646. if (!info->tx_enabled)
  1647. tx_start(info);
  1648. } else {
  1649. if (info->tx_enabled)
  1650. tx_stop(info);
  1651. }
  1652. spin_unlock_irqrestore(&info->lock,flags);
  1653. return 0;
  1654. }
  1655. static int tx_abort(MGSLPC_INFO * info)
  1656. {
  1657. unsigned long flags;
  1658. if (debug_level >= DEBUG_LEVEL_INFO)
  1659. printk("tx_abort(%s)\n", info->device_name);
  1660. spin_lock_irqsave(&info->lock,flags);
  1661. if (info->tx_active && info->tx_count &&
  1662. info->params.mode == MGSL_MODE_HDLC) {
  1663. /* clear data count so FIFO is not filled on next IRQ.
  1664. * This results in underrun and abort transmission.
  1665. */
  1666. info->tx_count = info->tx_put = info->tx_get = 0;
  1667. info->tx_aborting = TRUE;
  1668. }
  1669. spin_unlock_irqrestore(&info->lock,flags);
  1670. return 0;
  1671. }
  1672. static int set_rxenable(MGSLPC_INFO * info, int enable)
  1673. {
  1674. unsigned long flags;
  1675. if (debug_level >= DEBUG_LEVEL_INFO)
  1676. printk("set_rxenable(%s,%d)\n", info->device_name, enable);
  1677. spin_lock_irqsave(&info->lock,flags);
  1678. if (enable) {
  1679. if (!info->rx_enabled)
  1680. rx_start(info);
  1681. } else {
  1682. if (info->rx_enabled)
  1683. rx_stop(info);
  1684. }
  1685. spin_unlock_irqrestore(&info->lock,flags);
  1686. return 0;
  1687. }
  1688. /* wait for specified event to occur
  1689. *
  1690. * Arguments: info pointer to device instance data
  1691. * mask pointer to bitmask of events to wait for
  1692. * Return Value: 0 if successful and bit mask updated with
  1693. * of events triggerred,
  1694. * otherwise error code
  1695. */
  1696. static int wait_events(MGSLPC_INFO * info, int __user *mask_ptr)
  1697. {
  1698. unsigned long flags;
  1699. int s;
  1700. int rc=0;
  1701. struct mgsl_icount cprev, cnow;
  1702. int events;
  1703. int mask;
  1704. struct _input_signal_events oldsigs, newsigs;
  1705. DECLARE_WAITQUEUE(wait, current);
  1706. COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
  1707. if (rc)
  1708. return -EFAULT;
  1709. if (debug_level >= DEBUG_LEVEL_INFO)
  1710. printk("wait_events(%s,%d)\n", info->device_name, mask);
  1711. spin_lock_irqsave(&info->lock,flags);
  1712. /* return immediately if state matches requested events */
  1713. get_signals(info);
  1714. s = info->serial_signals;
  1715. events = mask &
  1716. ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
  1717. ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
  1718. ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
  1719. ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
  1720. if (events) {
  1721. spin_unlock_irqrestore(&info->lock,flags);
  1722. goto exit;
  1723. }
  1724. /* save current irq counts */
  1725. cprev = info->icount;
  1726. oldsigs = info->input_signal_events;
  1727. if ((info->params.mode == MGSL_MODE_HDLC) &&
  1728. (mask & MgslEvent_ExitHuntMode))
  1729. irq_enable(info, CHA, IRQ_EXITHUNT);
  1730. set_current_state(TASK_INTERRUPTIBLE);
  1731. add_wait_queue(&info->event_wait_q, &wait);
  1732. spin_unlock_irqrestore(&info->lock,flags);
  1733. for(;;) {
  1734. schedule();
  1735. if (signal_pending(current)) {
  1736. rc = -ERESTARTSYS;
  1737. break;
  1738. }
  1739. /* get current irq counts */
  1740. spin_lock_irqsave(&info->lock,flags);
  1741. cnow = info->icount;
  1742. newsigs = info->input_signal_events;
  1743. set_current_state(TASK_INTERRUPTIBLE);
  1744. spin_unlock_irqrestore(&info->lock,flags);
  1745. /* if no change, wait aborted for some reason */
  1746. if (newsigs.dsr_up == oldsigs.dsr_up &&
  1747. newsigs.dsr_down == oldsigs.dsr_down &&
  1748. newsigs.dcd_up == oldsigs.dcd_up &&
  1749. newsigs.dcd_down == oldsigs.dcd_down &&
  1750. newsigs.cts_up == oldsigs.cts_up &&
  1751. newsigs.cts_down == oldsigs.cts_down &&
  1752. newsigs.ri_up == oldsigs.ri_up &&
  1753. newsigs.ri_down == oldsigs.ri_down &&
  1754. cnow.exithunt == cprev.exithunt &&
  1755. cnow.rxidle == cprev.rxidle) {
  1756. rc = -EIO;
  1757. break;
  1758. }
  1759. events = mask &
  1760. ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
  1761. (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
  1762. (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
  1763. (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
  1764. (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
  1765. (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
  1766. (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
  1767. (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
  1768. (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
  1769. (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
  1770. if (events)
  1771. break;
  1772. cprev = cnow;
  1773. oldsigs = newsigs;
  1774. }
  1775. remove_wait_queue(&info->event_wait_q, &wait);
  1776. set_current_state(TASK_RUNNING);
  1777. if (mask & MgslEvent_ExitHuntMode) {
  1778. spin_lock_irqsave(&info->lock,flags);
  1779. if (!waitqueue_active(&info->event_wait_q))
  1780. irq_disable(info, CHA, IRQ_EXITHUNT);
  1781. spin_unlock_irqrestore(&info->lock,flags);
  1782. }
  1783. exit:
  1784. if (rc == 0)
  1785. PUT_USER(rc, events, mask_ptr);
  1786. return rc;
  1787. }
  1788. static int modem_input_wait(MGSLPC_INFO *info,int arg)
  1789. {
  1790. unsigned long flags;
  1791. int rc;
  1792. struct mgsl_icount cprev, cnow;
  1793. DECLARE_WAITQUEUE(wait, current);
  1794. /* save current irq counts */
  1795. spin_lock_irqsave(&info->lock,flags);
  1796. cprev = info->icount;
  1797. add_wait_queue(&info->status_event_wait_q, &wait);
  1798. set_current_state(TASK_INTERRUPTIBLE);
  1799. spin_unlock_irqrestore(&info->lock,flags);
  1800. for(;;) {
  1801. schedule();
  1802. if (signal_pending(current)) {
  1803. rc = -ERESTARTSYS;
  1804. break;
  1805. }
  1806. /* get new irq counts */
  1807. spin_lock_irqsave(&info->lock,flags);
  1808. cnow = info->icount;
  1809. set_current_state(TASK_INTERRUPTIBLE);
  1810. spin_unlock_irqrestore(&info->lock,flags);
  1811. /* if no change, wait aborted for some reason */
  1812. if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
  1813. cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
  1814. rc = -EIO;
  1815. break;
  1816. }
  1817. /* check for change in caller specified modem input */
  1818. if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
  1819. (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
  1820. (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
  1821. (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
  1822. rc = 0;
  1823. break;
  1824. }
  1825. cprev = cnow;
  1826. }
  1827. remove_wait_queue(&info->status_event_wait_q, &wait);
  1828. set_current_state(TASK_RUNNING);
  1829. return rc;
  1830. }
  1831. /* return the state of the serial control and status signals
  1832. */
  1833. static int tiocmget(struct tty_struct *tty, struct file *file)
  1834. {
  1835. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1836. unsigned int result;
  1837. unsigned long flags;
  1838. spin_lock_irqsave(&info->lock,flags);
  1839. get_signals(info);
  1840. spin_unlock_irqrestore(&info->lock,flags);
  1841. result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
  1842. ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
  1843. ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
  1844. ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
  1845. ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
  1846. ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
  1847. if (debug_level >= DEBUG_LEVEL_INFO)
  1848. printk("%s(%d):%s tiocmget() value=%08X\n",
  1849. __FILE__,__LINE__, info->device_name, result );
  1850. return result;
  1851. }
  1852. /* set modem control signals (DTR/RTS)
  1853. */
  1854. static int tiocmset(struct tty_struct *tty, struct file *file,
  1855. unsigned int set, unsigned int clear)
  1856. {
  1857. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1858. unsigned long flags;
  1859. if (debug_level >= DEBUG_LEVEL_INFO)
  1860. printk("%s(%d):%s tiocmset(%x,%x)\n",
  1861. __FILE__,__LINE__,info->device_name, set, clear);
  1862. if (set & TIOCM_RTS)
  1863. info->serial_signals |= SerialSignal_RTS;
  1864. if (set & TIOCM_DTR)
  1865. info->serial_signals |= SerialSignal_DTR;
  1866. if (clear & TIOCM_RTS)
  1867. info->serial_signals &= ~SerialSignal_RTS;
  1868. if (clear & TIOCM_DTR)
  1869. info->serial_signals &= ~SerialSignal_DTR;
  1870. spin_lock_irqsave(&info->lock,flags);
  1871. set_signals(info);
  1872. spin_unlock_irqrestore(&info->lock,flags);
  1873. return 0;
  1874. }
  1875. /* Set or clear transmit break condition
  1876. *
  1877. * Arguments: tty pointer to tty instance data
  1878. * break_state -1=set break condition, 0=clear
  1879. */
  1880. static void mgslpc_break(struct tty_struct *tty, int break_state)
  1881. {
  1882. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1883. unsigned long flags;
  1884. if (debug_level >= DEBUG_LEVEL_INFO)
  1885. printk("%s(%d):mgslpc_break(%s,%d)\n",
  1886. __FILE__,__LINE__, info->device_name, break_state);
  1887. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_break"))
  1888. return;
  1889. spin_lock_irqsave(&info->lock,flags);
  1890. if (break_state == -1)
  1891. set_reg_bits(info, CHA+DAFO, BIT6);
  1892. else
  1893. clear_reg_bits(info, CHA+DAFO, BIT6);
  1894. spin_unlock_irqrestore(&info->lock,flags);
  1895. }
  1896. /* Service an IOCTL request
  1897. *
  1898. * Arguments:
  1899. *
  1900. * tty pointer to tty instance data
  1901. * file pointer to associated file object for device
  1902. * cmd IOCTL command code
  1903. * arg command argument/context
  1904. *
  1905. * Return Value: 0 if success, otherwise error code
  1906. */
  1907. static int mgslpc_ioctl(struct tty_struct *tty, struct file * file,
  1908. unsigned int cmd, unsigned long arg)
  1909. {
  1910. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  1911. if (debug_level >= DEBUG_LEVEL_INFO)
  1912. printk("%s(%d):mgslpc_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
  1913. info->device_name, cmd );
  1914. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_ioctl"))
  1915. return -ENODEV;
  1916. if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
  1917. (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
  1918. if (tty->flags & (1 << TTY_IO_ERROR))
  1919. return -EIO;
  1920. }
  1921. return ioctl_common(info, cmd, arg);
  1922. }
  1923. static int ioctl_common(MGSLPC_INFO *info, unsigned int cmd, unsigned long arg)
  1924. {
  1925. int error;
  1926. struct mgsl_icount cnow; /* kernel counter temps */
  1927. struct serial_icounter_struct __user *p_cuser; /* user space */
  1928. void __user *argp = (void __user *)arg;
  1929. unsigned long flags;
  1930. switch (cmd) {
  1931. case MGSL_IOCGPARAMS:
  1932. return get_params(info, argp);
  1933. case MGSL_IOCSPARAMS:
  1934. return set_params(info, argp);
  1935. case MGSL_IOCGTXIDLE:
  1936. return get_txidle(info, argp);
  1937. case MGSL_IOCSTXIDLE:
  1938. return set_txidle(info, (int)arg);
  1939. case MGSL_IOCGIF:
  1940. return get_interface(info, argp);
  1941. case MGSL_IOCSIF:
  1942. return set_interface(info,(int)arg);
  1943. case MGSL_IOCTXENABLE:
  1944. return set_txenable(info,(int)arg);
  1945. case MGSL_IOCRXENABLE:
  1946. return set_rxenable(info,(int)arg);
  1947. case MGSL_IOCTXABORT:
  1948. return tx_abort(info);
  1949. case MGSL_IOCGSTATS:
  1950. return get_stats(info, argp);
  1951. case MGSL_IOCWAITEVENT:
  1952. return wait_events(info, argp);
  1953. case TIOCMIWAIT:
  1954. return modem_input_wait(info,(int)arg);
  1955. case TIOCGICOUNT:
  1956. spin_lock_irqsave(&info->lock,flags);
  1957. cnow = info->icount;
  1958. spin_unlock_irqrestore(&info->lock,flags);
  1959. p_cuser = argp;
  1960. PUT_USER(error,cnow.cts, &p_cuser->cts);
  1961. if (error) return error;
  1962. PUT_USER(error,cnow.dsr, &p_cuser->dsr);
  1963. if (error) return error;
  1964. PUT_USER(error,cnow.rng, &p_cuser->rng);
  1965. if (error) return error;
  1966. PUT_USER(error,cnow.dcd, &p_cuser->dcd);
  1967. if (error) return error;
  1968. PUT_USER(error,cnow.rx, &p_cuser->rx);
  1969. if (error) return error;
  1970. PUT_USER(error,cnow.tx, &p_cuser->tx);
  1971. if (error) return error;
  1972. PUT_USER(error,cnow.frame, &p_cuser->frame);
  1973. if (error) return error;
  1974. PUT_USER(error,cnow.overrun, &p_cuser->overrun);
  1975. if (error) return error;
  1976. PUT_USER(error,cnow.parity, &p_cuser->parity);
  1977. if (error) return error;
  1978. PUT_USER(error,cnow.brk, &p_cuser->brk);
  1979. if (error) return error;
  1980. PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
  1981. if (error) return error;
  1982. return 0;
  1983. default:
  1984. return -ENOIOCTLCMD;
  1985. }
  1986. return 0;
  1987. }
  1988. /* Set new termios settings
  1989. *
  1990. * Arguments:
  1991. *
  1992. * tty pointer to tty structure
  1993. * termios pointer to buffer to hold returned old termios
  1994. */
  1995. static void mgslpc_set_termios(struct tty_struct *tty, struct termios *old_termios)
  1996. {
  1997. MGSLPC_INFO *info = (MGSLPC_INFO *)tty->driver_data;
  1998. unsigned long flags;
  1999. if (debug_level >= DEBUG_LEVEL_INFO)
  2000. printk("%s(%d):mgslpc_set_termios %s\n", __FILE__,__LINE__,
  2001. tty->driver->name );
  2002. /* just return if nothing has changed */
  2003. if ((tty->termios->c_cflag == old_termios->c_cflag)
  2004. && (RELEVANT_IFLAG(tty->termios->c_iflag)
  2005. == RELEVANT_IFLAG(old_termios->c_iflag)))
  2006. return;
  2007. mgslpc_change_params(info);
  2008. /* Handle transition to B0 status */
  2009. if (old_termios->c_cflag & CBAUD &&
  2010. !(tty->termios->c_cflag & CBAUD)) {
  2011. info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
  2012. spin_lock_irqsave(&info->lock,flags);
  2013. set_signals(info);
  2014. spin_unlock_irqrestore(&info->lock,flags);
  2015. }
  2016. /* Handle transition away from B0 status */
  2017. if (!(old_termios->c_cflag & CBAUD) &&
  2018. tty->termios->c_cflag & CBAUD) {
  2019. info->serial_signals |= SerialSignal_DTR;
  2020. if (!(tty->termios->c_cflag & CRTSCTS) ||
  2021. !test_bit(TTY_THROTTLED, &tty->flags)) {
  2022. info->serial_signals |= SerialSignal_RTS;
  2023. }
  2024. spin_lock_irqsave(&info->lock,flags);
  2025. set_signals(info);
  2026. spin_unlock_irqrestore(&info->lock,flags);
  2027. }
  2028. /* Handle turning off CRTSCTS */
  2029. if (old_termios->c_cflag & CRTSCTS &&
  2030. !(tty->termios->c_cflag & CRTSCTS)) {
  2031. tty->hw_stopped = 0;
  2032. tx_release(tty);
  2033. }
  2034. }
  2035. static void mgslpc_close(struct tty_struct *tty, struct file * filp)
  2036. {
  2037. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2038. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_close"))
  2039. return;
  2040. if (debug_level >= DEBUG_LEVEL_INFO)
  2041. printk("%s(%d):mgslpc_close(%s) entry, count=%d\n",
  2042. __FILE__,__LINE__, info->device_name, info->count);
  2043. if (!info->count)
  2044. return;
  2045. if (tty_hung_up_p(filp))
  2046. goto cleanup;
  2047. if ((tty->count == 1) && (info->count != 1)) {
  2048. /*
  2049. * tty->count is 1 and the tty structure will be freed.
  2050. * info->count should be one in this case.
  2051. * if it's not, correct it so that the port is shutdown.
  2052. */
  2053. printk("mgslpc_close: bad refcount; tty->count is 1, "
  2054. "info->count is %d\n", info->count);
  2055. info->count = 1;
  2056. }
  2057. info->count--;
  2058. /* if at least one open remaining, leave hardware active */
  2059. if (info->count)
  2060. goto cleanup;
  2061. info->flags |= ASYNC_CLOSING;
  2062. /* set tty->closing to notify line discipline to
  2063. * only process XON/XOFF characters. Only the N_TTY
  2064. * discipline appears to use this (ppp does not).
  2065. */
  2066. tty->closing = 1;
  2067. /* wait for transmit data to clear all layers */
  2068. if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
  2069. if (debug_level >= DEBUG_LEVEL_INFO)
  2070. printk("%s(%d):mgslpc_close(%s) calling tty_wait_until_sent\n",
  2071. __FILE__,__LINE__, info->device_name );
  2072. tty_wait_until_sent(tty, info->closing_wait);
  2073. }
  2074. if (info->flags & ASYNC_INITIALIZED)
  2075. mgslpc_wait_until_sent(tty, info->timeout);
  2076. if (tty->driver->flush_buffer)
  2077. tty->driver->flush_buffer(tty);
  2078. ldisc_flush_buffer(tty);
  2079. shutdown(info);
  2080. tty->closing = 0;
  2081. info->tty = NULL;
  2082. if (info->blocked_open) {
  2083. if (info->close_delay) {
  2084. msleep_interruptible(jiffies_to_msecs(info->close_delay));
  2085. }
  2086. wake_up_interruptible(&info->open_wait);
  2087. }
  2088. info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
  2089. wake_up_interruptible(&info->close_wait);
  2090. cleanup:
  2091. if (debug_level >= DEBUG_LEVEL_INFO)
  2092. printk("%s(%d):mgslpc_close(%s) exit, count=%d\n", __FILE__,__LINE__,
  2093. tty->driver->name, info->count);
  2094. }
  2095. /* Wait until the transmitter is empty.
  2096. */
  2097. static void mgslpc_wait_until_sent(struct tty_struct *tty, int timeout)
  2098. {
  2099. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2100. unsigned long orig_jiffies, char_time;
  2101. if (!info )
  2102. return;
  2103. if (debug_level >= DEBUG_LEVEL_INFO)
  2104. printk("%s(%d):mgslpc_wait_until_sent(%s) entry\n",
  2105. __FILE__,__LINE__, info->device_name );
  2106. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_wait_until_sent"))
  2107. return;
  2108. if (!(info->flags & ASYNC_INITIALIZED))
  2109. goto exit;
  2110. orig_jiffies = jiffies;
  2111. /* Set check interval to 1/5 of estimated time to
  2112. * send a character, and make it at least 1. The check
  2113. * interval should also be less than the timeout.
  2114. * Note: use tight timings here to satisfy the NIST-PCTS.
  2115. */
  2116. if ( info->params.data_rate ) {
  2117. char_time = info->timeout/(32 * 5);
  2118. if (!char_time)
  2119. char_time++;
  2120. } else
  2121. char_time = 1;
  2122. if (timeout)
  2123. char_time = min_t(unsigned long, char_time, timeout);
  2124. if (info->params.mode == MGSL_MODE_HDLC) {
  2125. while (info->tx_active) {
  2126. msleep_interruptible(jiffies_to_msecs(char_time));
  2127. if (signal_pending(current))
  2128. break;
  2129. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2130. break;
  2131. }
  2132. } else {
  2133. while ((info->tx_count || info->tx_active) &&
  2134. info->tx_enabled) {
  2135. msleep_interruptible(jiffies_to_msecs(char_time));
  2136. if (signal_pending(current))
  2137. break;
  2138. if (timeout && time_after(jiffies, orig_jiffies + timeout))
  2139. break;
  2140. }
  2141. }
  2142. exit:
  2143. if (debug_level >= DEBUG_LEVEL_INFO)
  2144. printk("%s(%d):mgslpc_wait_until_sent(%s) exit\n",
  2145. __FILE__,__LINE__, info->device_name );
  2146. }
  2147. /* Called by tty_hangup() when a hangup is signaled.
  2148. * This is the same as closing all open files for the port.
  2149. */
  2150. static void mgslpc_hangup(struct tty_struct *tty)
  2151. {
  2152. MGSLPC_INFO * info = (MGSLPC_INFO *)tty->driver_data;
  2153. if (debug_level >= DEBUG_LEVEL_INFO)
  2154. printk("%s(%d):mgslpc_hangup(%s)\n",
  2155. __FILE__,__LINE__, info->device_name );
  2156. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_hangup"))
  2157. return;
  2158. mgslpc_flush_buffer(tty);
  2159. shutdown(info);
  2160. info->count = 0;
  2161. info->flags &= ~ASYNC_NORMAL_ACTIVE;
  2162. info->tty = NULL;
  2163. wake_up_interruptible(&info->open_wait);
  2164. }
  2165. /* Block the current process until the specified port
  2166. * is ready to be opened.
  2167. */
  2168. static int block_til_ready(struct tty_struct *tty, struct file *filp,
  2169. MGSLPC_INFO *info)
  2170. {
  2171. DECLARE_WAITQUEUE(wait, current);
  2172. int retval;
  2173. int do_clocal = 0, extra_count = 0;
  2174. unsigned long flags;
  2175. if (debug_level >= DEBUG_LEVEL_INFO)
  2176. printk("%s(%d):block_til_ready on %s\n",
  2177. __FILE__,__LINE__, tty->driver->name );
  2178. if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
  2179. /* nonblock mode is set or port is not enabled */
  2180. /* just verify that callout device is not active */
  2181. info->flags |= ASYNC_NORMAL_ACTIVE;
  2182. return 0;
  2183. }
  2184. if (tty->termios->c_cflag & CLOCAL)
  2185. do_clocal = 1;
  2186. /* Wait for carrier detect and the line to become
  2187. * free (i.e., not in use by the callout). While we are in
  2188. * this loop, info->count is dropped by one, so that
  2189. * mgslpc_close() knows when to free things. We restore it upon
  2190. * exit, either normal or abnormal.
  2191. */
  2192. retval = 0;
  2193. add_wait_queue(&info->open_wait, &wait);
  2194. if (debug_level >= DEBUG_LEVEL_INFO)
  2195. printk("%s(%d):block_til_ready before block on %s count=%d\n",
  2196. __FILE__,__LINE__, tty->driver->name, info->count );
  2197. spin_lock_irqsave(&info->lock, flags);
  2198. if (!tty_hung_up_p(filp)) {
  2199. extra_count = 1;
  2200. info->count--;
  2201. }
  2202. spin_unlock_irqrestore(&info->lock, flags);
  2203. info->blocked_open++;
  2204. while (1) {
  2205. if ((tty->termios->c_cflag & CBAUD)) {
  2206. spin_lock_irqsave(&info->lock,flags);
  2207. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  2208. set_signals(info);
  2209. spin_unlock_irqrestore(&info->lock,flags);
  2210. }
  2211. set_current_state(TASK_INTERRUPTIBLE);
  2212. if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
  2213. retval = (info->flags & ASYNC_HUP_NOTIFY) ?
  2214. -EAGAIN : -ERESTARTSYS;
  2215. break;
  2216. }
  2217. spin_lock_irqsave(&info->lock,flags);
  2218. get_signals(info);
  2219. spin_unlock_irqrestore(&info->lock,flags);
  2220. if (!(info->flags & ASYNC_CLOSING) &&
  2221. (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
  2222. break;
  2223. }
  2224. if (signal_pending(current)) {
  2225. retval = -ERESTARTSYS;
  2226. break;
  2227. }
  2228. if (debug_level >= DEBUG_LEVEL_INFO)
  2229. printk("%s(%d):block_til_ready blocking on %s count=%d\n",
  2230. __FILE__,__LINE__, tty->driver->name, info->count );
  2231. schedule();
  2232. }
  2233. set_current_state(TASK_RUNNING);
  2234. remove_wait_queue(&info->open_wait, &wait);
  2235. if (extra_count)
  2236. info->count++;
  2237. info->blocked_open--;
  2238. if (debug_level >= DEBUG_LEVEL_INFO)
  2239. printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
  2240. __FILE__,__LINE__, tty->driver->name, info->count );
  2241. if (!retval)
  2242. info->flags |= ASYNC_NORMAL_ACTIVE;
  2243. return retval;
  2244. }
  2245. static int mgslpc_open(struct tty_struct *tty, struct file * filp)
  2246. {
  2247. MGSLPC_INFO *info;
  2248. int retval, line;
  2249. unsigned long flags;
  2250. /* verify range of specified line number */
  2251. line = tty->index;
  2252. if ((line < 0) || (line >= mgslpc_device_count)) {
  2253. printk("%s(%d):mgslpc_open with invalid line #%d.\n",
  2254. __FILE__,__LINE__,line);
  2255. return -ENODEV;
  2256. }
  2257. /* find the info structure for the specified line */
  2258. info = mgslpc_device_list;
  2259. while(info && info->line != line)
  2260. info = info->next_device;
  2261. if (mgslpc_paranoia_check(info, tty->name, "mgslpc_open"))
  2262. return -ENODEV;
  2263. tty->driver_data = info;
  2264. info->tty = tty;
  2265. if (debug_level >= DEBUG_LEVEL_INFO)
  2266. printk("%s(%d):mgslpc_open(%s), old ref count = %d\n",
  2267. __FILE__,__LINE__,tty->driver->name, info->count);
  2268. /* If port is closing, signal caller to try again */
  2269. if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
  2270. if (info->flags & ASYNC_CLOSING)
  2271. interruptible_sleep_on(&info->close_wait);
  2272. retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
  2273. -EAGAIN : -ERESTARTSYS);
  2274. goto cleanup;
  2275. }
  2276. info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
  2277. spin_lock_irqsave(&info->netlock, flags);
  2278. if (info->netcount) {
  2279. retval = -EBUSY;
  2280. spin_unlock_irqrestore(&info->netlock, flags);
  2281. goto cleanup;
  2282. }
  2283. info->count++;
  2284. spin_unlock_irqrestore(&info->netlock, flags);
  2285. if (info->count == 1) {
  2286. /* 1st open on this device, init hardware */
  2287. retval = startup(info);
  2288. if (retval < 0)
  2289. goto cleanup;
  2290. }
  2291. retval = block_til_ready(tty, filp, info);
  2292. if (retval) {
  2293. if (debug_level >= DEBUG_LEVEL_INFO)
  2294. printk("%s(%d):block_til_ready(%s) returned %d\n",
  2295. __FILE__,__LINE__, info->device_name, retval);
  2296. goto cleanup;
  2297. }
  2298. if (debug_level >= DEBUG_LEVEL_INFO)
  2299. printk("%s(%d):mgslpc_open(%s) success\n",
  2300. __FILE__,__LINE__, info->device_name);
  2301. retval = 0;
  2302. cleanup:
  2303. if (retval) {
  2304. if (tty->count == 1)
  2305. info->tty = NULL; /* tty layer will release tty struct */
  2306. if(info->count)
  2307. info->count--;
  2308. }
  2309. return retval;
  2310. }
  2311. /*
  2312. * /proc fs routines....
  2313. */
  2314. static inline int line_info(char *buf, MGSLPC_INFO *info)
  2315. {
  2316. char stat_buf[30];
  2317. int ret;
  2318. unsigned long flags;
  2319. ret = sprintf(buf, "%s:io:%04X irq:%d",
  2320. info->device_name, info->io_base, info->irq_level);
  2321. /* output current serial signal states */
  2322. spin_lock_irqsave(&info->lock,flags);
  2323. get_signals(info);
  2324. spin_unlock_irqrestore(&info->lock,flags);
  2325. stat_buf[0] = 0;
  2326. stat_buf[1] = 0;
  2327. if (info->serial_signals & SerialSignal_RTS)
  2328. strcat(stat_buf, "|RTS");
  2329. if (info->serial_signals & SerialSignal_CTS)
  2330. strcat(stat_buf, "|CTS");
  2331. if (info->serial_signals & SerialSignal_DTR)
  2332. strcat(stat_buf, "|DTR");
  2333. if (info->serial_signals & SerialSignal_DSR)
  2334. strcat(stat_buf, "|DSR");
  2335. if (info->serial_signals & SerialSignal_DCD)
  2336. strcat(stat_buf, "|CD");
  2337. if (info->serial_signals & SerialSignal_RI)
  2338. strcat(stat_buf, "|RI");
  2339. if (info->params.mode == MGSL_MODE_HDLC) {
  2340. ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
  2341. info->icount.txok, info->icount.rxok);
  2342. if (info->icount.txunder)
  2343. ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
  2344. if (info->icount.txabort)
  2345. ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
  2346. if (info->icount.rxshort)
  2347. ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
  2348. if (info->icount.rxlong)
  2349. ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
  2350. if (info->icount.rxover)
  2351. ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
  2352. if (info->icount.rxcrc)
  2353. ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
  2354. } else {
  2355. ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
  2356. info->icount.tx, info->icount.rx);
  2357. if (info->icount.frame)
  2358. ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
  2359. if (info->icount.parity)
  2360. ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
  2361. if (info->icount.brk)
  2362. ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
  2363. if (info->icount.overrun)
  2364. ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
  2365. }
  2366. /* Append serial signal status to end */
  2367. ret += sprintf(buf+ret, " %s\n", stat_buf+1);
  2368. ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
  2369. info->tx_active,info->bh_requested,info->bh_running,
  2370. info->pending_bh);
  2371. return ret;
  2372. }
  2373. /* Called to print information about devices
  2374. */
  2375. static int mgslpc_read_proc(char *page, char **start, off_t off, int count,
  2376. int *eof, void *data)
  2377. {
  2378. int len = 0, l;
  2379. off_t begin = 0;
  2380. MGSLPC_INFO *info;
  2381. len += sprintf(page, "synclink driver:%s\n", driver_version);
  2382. info = mgslpc_device_list;
  2383. while( info ) {
  2384. l = line_info(page + len, info);
  2385. len += l;
  2386. if (len+begin > off+count)
  2387. goto done;
  2388. if (len+begin < off) {
  2389. begin += len;
  2390. len = 0;
  2391. }
  2392. info = info->next_device;
  2393. }
  2394. *eof = 1;
  2395. done:
  2396. if (off >= len+begin)
  2397. return 0;
  2398. *start = page + (off-begin);
  2399. return ((count < begin+len-off) ? count : begin+len-off);
  2400. }
  2401. static int rx_alloc_buffers(MGSLPC_INFO *info)
  2402. {
  2403. /* each buffer has header and data */
  2404. info->rx_buf_size = sizeof(RXBUF) + info->max_frame_size;
  2405. /* calculate total allocation size for 8 buffers */
  2406. info->rx_buf_total_size = info->rx_buf_size * 8;
  2407. /* limit total allocated memory */
  2408. if (info->rx_buf_total_size > 0x10000)
  2409. info->rx_buf_total_size = 0x10000;
  2410. /* calculate number of buffers */
  2411. info->rx_buf_count = info->rx_buf_total_size / info->rx_buf_size;
  2412. info->rx_buf = kmalloc(info->rx_buf_total_size, GFP_KERNEL);
  2413. if (info->rx_buf == NULL)
  2414. return -ENOMEM;
  2415. rx_reset_buffers(info);
  2416. return 0;
  2417. }
  2418. static void rx_free_buffers(MGSLPC_INFO *info)
  2419. {
  2420. kfree(info->rx_buf);
  2421. info->rx_buf = NULL;
  2422. }
  2423. static int claim_resources(MGSLPC_INFO *info)
  2424. {
  2425. if (rx_alloc_buffers(info) < 0 ) {
  2426. printk( "Cant allocate rx buffer %s\n", info->device_name);
  2427. release_resources(info);
  2428. return -ENODEV;
  2429. }
  2430. return 0;
  2431. }
  2432. static void release_resources(MGSLPC_INFO *info)
  2433. {
  2434. if (debug_level >= DEBUG_LEVEL_INFO)
  2435. printk("release_resources(%s)\n", info->device_name);
  2436. rx_free_buffers(info);
  2437. }
  2438. /* Add the specified device instance data structure to the
  2439. * global linked list of devices and increment the device count.
  2440. *
  2441. * Arguments: info pointer to device instance data
  2442. */
  2443. static void mgslpc_add_device(MGSLPC_INFO *info)
  2444. {
  2445. info->next_device = NULL;
  2446. info->line = mgslpc_device_count;
  2447. sprintf(info->device_name,"ttySLP%d",info->line);
  2448. if (info->line < MAX_DEVICE_COUNT) {
  2449. if (maxframe[info->line])
  2450. info->max_frame_size = maxframe[info->line];
  2451. info->dosyncppp = dosyncppp[info->line];
  2452. }
  2453. mgslpc_device_count++;
  2454. if (!mgslpc_device_list)
  2455. mgslpc_device_list = info;
  2456. else {
  2457. MGSLPC_INFO *current_dev = mgslpc_device_list;
  2458. while( current_dev->next_device )
  2459. current_dev = current_dev->next_device;
  2460. current_dev->next_device = info;
  2461. }
  2462. if (info->max_frame_size < 4096)
  2463. info->max_frame_size = 4096;
  2464. else if (info->max_frame_size > 65535)
  2465. info->max_frame_size = 65535;
  2466. printk( "SyncLink PC Card %s:IO=%04X IRQ=%d\n",
  2467. info->device_name, info->io_base, info->irq_level);
  2468. #ifdef CONFIG_HDLC
  2469. hdlcdev_init(info);
  2470. #endif
  2471. }
  2472. static void mgslpc_remove_device(MGSLPC_INFO *remove_info)
  2473. {
  2474. MGSLPC_INFO *info = mgslpc_device_list;
  2475. MGSLPC_INFO *last = NULL;
  2476. while(info) {
  2477. if (info == remove_info) {
  2478. if (last)
  2479. last->next_device = info->next_device;
  2480. else
  2481. mgslpc_device_list = info->next_device;
  2482. #ifdef CONFIG_HDLC
  2483. hdlcdev_exit(info);
  2484. #endif
  2485. release_resources(info);
  2486. kfree(info);
  2487. mgslpc_device_count--;
  2488. return;
  2489. }
  2490. last = info;
  2491. info = info->next_device;
  2492. }
  2493. }
  2494. static struct pcmcia_device_id mgslpc_ids[] = {
  2495. PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
  2496. PCMCIA_DEVICE_NULL
  2497. };
  2498. MODULE_DEVICE_TABLE(pcmcia, mgslpc_ids);
  2499. static struct pcmcia_driver mgslpc_driver = {
  2500. .owner = THIS_MODULE,
  2501. .drv = {
  2502. .name = "synclink_cs",
  2503. },
  2504. .probe = mgslpc_probe,
  2505. .remove = mgslpc_detach,
  2506. .id_table = mgslpc_ids,
  2507. .suspend = mgslpc_suspend,
  2508. .resume = mgslpc_resume,
  2509. };
  2510. static struct tty_operations mgslpc_ops = {
  2511. .open = mgslpc_open,
  2512. .close = mgslpc_close,
  2513. .write = mgslpc_write,
  2514. .put_char = mgslpc_put_char,
  2515. .flush_chars = mgslpc_flush_chars,
  2516. .write_room = mgslpc_write_room,
  2517. .chars_in_buffer = mgslpc_chars_in_buffer,
  2518. .flush_buffer = mgslpc_flush_buffer,
  2519. .ioctl = mgslpc_ioctl,
  2520. .throttle = mgslpc_throttle,
  2521. .unthrottle = mgslpc_unthrottle,
  2522. .send_xchar = mgslpc_send_xchar,
  2523. .break_ctl = mgslpc_break,
  2524. .wait_until_sent = mgslpc_wait_until_sent,
  2525. .read_proc = mgslpc_read_proc,
  2526. .set_termios = mgslpc_set_termios,
  2527. .stop = tx_pause,
  2528. .start = tx_release,
  2529. .hangup = mgslpc_hangup,
  2530. .tiocmget = tiocmget,
  2531. .tiocmset = tiocmset,
  2532. };
  2533. static void synclink_cs_cleanup(void)
  2534. {
  2535. int rc;
  2536. printk("Unloading %s: version %s\n", driver_name, driver_version);
  2537. while(mgslpc_device_list)
  2538. mgslpc_remove_device(mgslpc_device_list);
  2539. if (serial_driver) {
  2540. if ((rc = tty_unregister_driver(serial_driver)))
  2541. printk("%s(%d) failed to unregister tty driver err=%d\n",
  2542. __FILE__,__LINE__,rc);
  2543. put_tty_driver(serial_driver);
  2544. }
  2545. pcmcia_unregister_driver(&mgslpc_driver);
  2546. }
  2547. static int __init synclink_cs_init(void)
  2548. {
  2549. int rc;
  2550. if (break_on_load) {
  2551. mgslpc_get_text_ptr();
  2552. BREAKPOINT();
  2553. }
  2554. printk("%s %s\n", driver_name, driver_version);
  2555. if ((rc = pcmcia_register_driver(&mgslpc_driver)) < 0)
  2556. return rc;
  2557. serial_driver = alloc_tty_driver(MAX_DEVICE_COUNT);
  2558. if (!serial_driver) {
  2559. rc = -ENOMEM;
  2560. goto error;
  2561. }
  2562. /* Initialize the tty_driver structure */
  2563. serial_driver->owner = THIS_MODULE;
  2564. serial_driver->driver_name = "synclink_cs";
  2565. serial_driver->name = "ttySLP";
  2566. serial_driver->major = ttymajor;
  2567. serial_driver->minor_start = 64;
  2568. serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
  2569. serial_driver->subtype = SERIAL_TYPE_NORMAL;
  2570. serial_driver->init_termios = tty_std_termios;
  2571. serial_driver->init_termios.c_cflag =
  2572. B9600 | CS8 | CREAD | HUPCL | CLOCAL;
  2573. serial_driver->flags = TTY_DRIVER_REAL_RAW;
  2574. tty_set_operations(serial_driver, &mgslpc_ops);
  2575. if ((rc = tty_register_driver(serial_driver)) < 0) {
  2576. printk("%s(%d):Couldn't register serial driver\n",
  2577. __FILE__,__LINE__);
  2578. put_tty_driver(serial_driver);
  2579. serial_driver = NULL;
  2580. goto error;
  2581. }
  2582. printk("%s %s, tty major#%d\n",
  2583. driver_name, driver_version,
  2584. serial_driver->major);
  2585. return 0;
  2586. error:
  2587. synclink_cs_cleanup();
  2588. return rc;
  2589. }
  2590. static void __exit synclink_cs_exit(void)
  2591. {
  2592. synclink_cs_cleanup();
  2593. }
  2594. module_init(synclink_cs_init);
  2595. module_exit(synclink_cs_exit);
  2596. static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
  2597. {
  2598. unsigned int M, N;
  2599. unsigned char val;
  2600. /* note:standard BRG mode is broken in V3.2 chip
  2601. * so enhanced mode is always used
  2602. */
  2603. if (rate) {
  2604. N = 3686400 / rate;
  2605. if (!N)
  2606. N = 1;
  2607. N >>= 1;
  2608. for (M = 1; N > 64 && M < 16; M++)
  2609. N >>= 1;
  2610. N--;
  2611. /* BGR[5..0] = N
  2612. * BGR[9..6] = M
  2613. * BGR[7..0] contained in BGR register
  2614. * BGR[9..8] contained in CCR2[7..6]
  2615. * divisor = (N+1)*2^M
  2616. *
  2617. * Note: M *must* not be zero (causes asymetric duty cycle)
  2618. */
  2619. write_reg(info, (unsigned char) (channel + BGR),
  2620. (unsigned char) ((M << 6) + N));
  2621. val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
  2622. val |= ((M << 4) & 0xc0);
  2623. write_reg(info, (unsigned char) (channel + CCR2), val);
  2624. }
  2625. }
  2626. /* Enabled the AUX clock output at the specified frequency.
  2627. */
  2628. static void enable_auxclk(MGSLPC_INFO *info)
  2629. {
  2630. unsigned char val;
  2631. /* MODE
  2632. *
  2633. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2634. * 05 ADM Address Mode, 0 = no addr recognition
  2635. * 04 TMD Timer Mode, 0 = external
  2636. * 03 RAC Receiver Active, 0 = inactive
  2637. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2638. * 01 TRS Timer Resolution, 1=512
  2639. * 00 TLP Test Loop, 0 = no loop
  2640. *
  2641. * 1000 0010
  2642. */
  2643. val = 0x82;
  2644. /* channel B RTS is used to enable AUXCLK driver on SP505 */
  2645. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2646. val |= BIT2;
  2647. write_reg(info, CHB + MODE, val);
  2648. /* CCR0
  2649. *
  2650. * 07 PU Power Up, 1=active, 0=power down
  2651. * 06 MCE Master Clock Enable, 1=enabled
  2652. * 05 Reserved, 0
  2653. * 04..02 SC[2..0] Encoding
  2654. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2655. *
  2656. * 11000000
  2657. */
  2658. write_reg(info, CHB + CCR0, 0xc0);
  2659. /* CCR1
  2660. *
  2661. * 07 SFLG Shared Flag, 0 = disable shared flags
  2662. * 06 GALP Go Active On Loop, 0 = not used
  2663. * 05 GLP Go On Loop, 0 = not used
  2664. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2665. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2666. * 02..00 CM[2..0] Clock Mode
  2667. *
  2668. * 0001 0111
  2669. */
  2670. write_reg(info, CHB + CCR1, 0x17);
  2671. /* CCR2 (Channel B)
  2672. *
  2673. * 07..06 BGR[9..8] Baud rate bits 9..8
  2674. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2675. * 04 SSEL Clock source select, 1=submode b
  2676. * 03 TOE 0=TxCLK is input, 1=TxCLK is output
  2677. * 02 RWX Read/Write Exchange 0=disabled
  2678. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2679. * 00 DIV, data inversion 0=disabled, 1=enabled
  2680. *
  2681. * 0011 1000
  2682. */
  2683. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2684. write_reg(info, CHB + CCR2, 0x38);
  2685. else
  2686. write_reg(info, CHB + CCR2, 0x30);
  2687. /* CCR4
  2688. *
  2689. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2690. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2691. * 05 TST1 Test Pin, 0=normal operation
  2692. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2693. * 03..02 Reserved, must be 0
  2694. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2695. *
  2696. * 0101 0000
  2697. */
  2698. write_reg(info, CHB + CCR4, 0x50);
  2699. /* if auxclk not enabled, set internal BRG so
  2700. * CTS transitions can be detected (requires TxC)
  2701. */
  2702. if (info->params.mode == MGSL_MODE_HDLC && info->params.clock_speed)
  2703. mgslpc_set_rate(info, CHB, info->params.clock_speed);
  2704. else
  2705. mgslpc_set_rate(info, CHB, 921600);
  2706. }
  2707. static void loopback_enable(MGSLPC_INFO *info)
  2708. {
  2709. unsigned char val;
  2710. /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
  2711. val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
  2712. write_reg(info, CHA + CCR1, val);
  2713. /* CCR2:04 SSEL Clock source select, 1=submode b */
  2714. val = read_reg(info, CHA + CCR2) | (BIT4 + BIT5);
  2715. write_reg(info, CHA + CCR2, val);
  2716. /* set LinkSpeed if available, otherwise default to 2Mbps */
  2717. if (info->params.clock_speed)
  2718. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2719. else
  2720. mgslpc_set_rate(info, CHA, 1843200);
  2721. /* MODE:00 TLP Test Loop, 1=loopback enabled */
  2722. val = read_reg(info, CHA + MODE) | BIT0;
  2723. write_reg(info, CHA + MODE, val);
  2724. }
  2725. static void hdlc_mode(MGSLPC_INFO *info)
  2726. {
  2727. unsigned char val;
  2728. unsigned char clkmode, clksubmode;
  2729. /* disable all interrupts */
  2730. irq_disable(info, CHA, 0xffff);
  2731. irq_disable(info, CHB, 0xffff);
  2732. port_irq_disable(info, 0xff);
  2733. /* assume clock mode 0a, rcv=RxC xmt=TxC */
  2734. clkmode = clksubmode = 0;
  2735. if (info->params.flags & HDLC_FLAG_RXC_DPLL
  2736. && info->params.flags & HDLC_FLAG_TXC_DPLL) {
  2737. /* clock mode 7a, rcv = DPLL, xmt = DPLL */
  2738. clkmode = 7;
  2739. } else if (info->params.flags & HDLC_FLAG_RXC_BRG
  2740. && info->params.flags & HDLC_FLAG_TXC_BRG) {
  2741. /* clock mode 7b, rcv = BRG, xmt = BRG */
  2742. clkmode = 7;
  2743. clksubmode = 1;
  2744. } else if (info->params.flags & HDLC_FLAG_RXC_DPLL) {
  2745. if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2746. /* clock mode 6b, rcv = DPLL, xmt = BRG/16 */
  2747. clkmode = 6;
  2748. clksubmode = 1;
  2749. } else {
  2750. /* clock mode 6a, rcv = DPLL, xmt = TxC */
  2751. clkmode = 6;
  2752. }
  2753. } else if (info->params.flags & HDLC_FLAG_TXC_BRG) {
  2754. /* clock mode 0b, rcv = RxC, xmt = BRG */
  2755. clksubmode = 1;
  2756. }
  2757. /* MODE
  2758. *
  2759. * 07..06 MDS[1..0] 10 = transparent HDLC mode
  2760. * 05 ADM Address Mode, 0 = no addr recognition
  2761. * 04 TMD Timer Mode, 0 = external
  2762. * 03 RAC Receiver Active, 0 = inactive
  2763. * 02 RTS 0=RTS active during xmit, 1=RTS always active
  2764. * 01 TRS Timer Resolution, 1=512
  2765. * 00 TLP Test Loop, 0 = no loop
  2766. *
  2767. * 1000 0010
  2768. */
  2769. val = 0x82;
  2770. if (info->params.loopback)
  2771. val |= BIT0;
  2772. /* preserve RTS state */
  2773. if (info->serial_signals & SerialSignal_RTS)
  2774. val |= BIT2;
  2775. write_reg(info, CHA + MODE, val);
  2776. /* CCR0
  2777. *
  2778. * 07 PU Power Up, 1=active, 0=power down
  2779. * 06 MCE Master Clock Enable, 1=enabled
  2780. * 05 Reserved, 0
  2781. * 04..02 SC[2..0] Encoding
  2782. * 01..00 SM[1..0] Serial Mode, 00=HDLC
  2783. *
  2784. * 11000000
  2785. */
  2786. val = 0xc0;
  2787. switch (info->params.encoding)
  2788. {
  2789. case HDLC_ENCODING_NRZI:
  2790. val |= BIT3;
  2791. break;
  2792. case HDLC_ENCODING_BIPHASE_SPACE:
  2793. val |= BIT4;
  2794. break; // FM0
  2795. case HDLC_ENCODING_BIPHASE_MARK:
  2796. val |= BIT4 + BIT2;
  2797. break; // FM1
  2798. case HDLC_ENCODING_BIPHASE_LEVEL:
  2799. val |= BIT4 + BIT3;
  2800. break; // Manchester
  2801. }
  2802. write_reg(info, CHA + CCR0, val);
  2803. /* CCR1
  2804. *
  2805. * 07 SFLG Shared Flag, 0 = disable shared flags
  2806. * 06 GALP Go Active On Loop, 0 = not used
  2807. * 05 GLP Go On Loop, 0 = not used
  2808. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  2809. * 03 ITF Interframe Time Fill, 0=mark, 1=flag
  2810. * 02..00 CM[2..0] Clock Mode
  2811. *
  2812. * 0001 0000
  2813. */
  2814. val = 0x10 + clkmode;
  2815. write_reg(info, CHA + CCR1, val);
  2816. /* CCR2
  2817. *
  2818. * 07..06 BGR[9..8] Baud rate bits 9..8
  2819. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  2820. * 04 SSEL Clock source select, 1=submode b
  2821. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  2822. * 02 RWX Read/Write Exchange 0=disabled
  2823. * 01 C32, CRC select, 0=CRC-16, 1=CRC-32
  2824. * 00 DIV, data inversion 0=disabled, 1=enabled
  2825. *
  2826. * 0000 0000
  2827. */
  2828. val = 0x00;
  2829. if (clkmode == 2 || clkmode == 3 || clkmode == 6
  2830. || clkmode == 7 || (clkmode == 0 && clksubmode == 1))
  2831. val |= BIT5;
  2832. if (clksubmode)
  2833. val |= BIT4;
  2834. if (info->params.crc_type == HDLC_CRC_32_CCITT)
  2835. val |= BIT1;
  2836. if (info->params.encoding == HDLC_ENCODING_NRZB)
  2837. val |= BIT0;
  2838. write_reg(info, CHA + CCR2, val);
  2839. /* CCR3
  2840. *
  2841. * 07..06 PRE[1..0] Preamble count 00=1, 01=2, 10=4, 11=8
  2842. * 05 EPT Enable preamble transmission, 1=enabled
  2843. * 04 RADD Receive address pushed to FIFO, 0=disabled
  2844. * 03 CRL CRC Reset Level, 0=FFFF
  2845. * 02 RCRC Rx CRC 0=On 1=Off
  2846. * 01 TCRC Tx CRC 0=On 1=Off
  2847. * 00 PSD DPLL Phase Shift Disable
  2848. *
  2849. * 0000 0000
  2850. */
  2851. val = 0x00;
  2852. if (info->params.crc_type == HDLC_CRC_NONE)
  2853. val |= BIT2 + BIT1;
  2854. if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
  2855. val |= BIT5;
  2856. switch (info->params.preamble_length)
  2857. {
  2858. case HDLC_PREAMBLE_LENGTH_16BITS:
  2859. val |= BIT6;
  2860. break;
  2861. case HDLC_PREAMBLE_LENGTH_32BITS:
  2862. val |= BIT6;
  2863. break;
  2864. case HDLC_PREAMBLE_LENGTH_64BITS:
  2865. val |= BIT7 + BIT6;
  2866. break;
  2867. }
  2868. write_reg(info, CHA + CCR3, val);
  2869. /* PRE - Preamble pattern */
  2870. val = 0;
  2871. switch (info->params.preamble)
  2872. {
  2873. case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
  2874. case HDLC_PREAMBLE_PATTERN_10: val = 0xaa; break;
  2875. case HDLC_PREAMBLE_PATTERN_01: val = 0x55; break;
  2876. case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
  2877. }
  2878. write_reg(info, CHA + PRE, val);
  2879. /* CCR4
  2880. *
  2881. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  2882. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  2883. * 05 TST1 Test Pin, 0=normal operation
  2884. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  2885. * 03..02 Reserved, must be 0
  2886. * 01..00 RFT[1..0] RxFIFO Threshold 00=32 bytes
  2887. *
  2888. * 0101 0000
  2889. */
  2890. val = 0x50;
  2891. write_reg(info, CHA + CCR4, val);
  2892. if (info->params.flags & HDLC_FLAG_RXC_DPLL)
  2893. mgslpc_set_rate(info, CHA, info->params.clock_speed * 16);
  2894. else
  2895. mgslpc_set_rate(info, CHA, info->params.clock_speed);
  2896. /* RLCR Receive length check register
  2897. *
  2898. * 7 1=enable receive length check
  2899. * 6..0 Max frame length = (RL + 1) * 32
  2900. */
  2901. write_reg(info, CHA + RLCR, 0);
  2902. /* XBCH Transmit Byte Count High
  2903. *
  2904. * 07 DMA mode, 0 = interrupt driven
  2905. * 06 NRM, 0=ABM (ignored)
  2906. * 05 CAS Carrier Auto Start
  2907. * 04 XC Transmit Continuously (ignored)
  2908. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  2909. *
  2910. * 0000 0000
  2911. */
  2912. val = 0x00;
  2913. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  2914. val |= BIT5;
  2915. write_reg(info, CHA + XBCH, val);
  2916. enable_auxclk(info);
  2917. if (info->params.loopback || info->testing_irq)
  2918. loopback_enable(info);
  2919. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  2920. {
  2921. irq_enable(info, CHB, IRQ_CTS);
  2922. /* PVR[3] 1=AUTO CTS active */
  2923. set_reg_bits(info, CHA + PVR, BIT3);
  2924. } else
  2925. clear_reg_bits(info, CHA + PVR, BIT3);
  2926. irq_enable(info, CHA,
  2927. IRQ_RXEOM + IRQ_RXFIFO + IRQ_ALLSENT +
  2928. IRQ_UNDERRUN + IRQ_TXFIFO);
  2929. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  2930. wait_command_complete(info, CHA);
  2931. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  2932. /* Master clock mode enabled above to allow reset commands
  2933. * to complete even if no data clocks are present.
  2934. *
  2935. * Disable master clock mode for normal communications because
  2936. * V3.2 of the ESCC2 has a bug that prevents the transmit all sent
  2937. * IRQ when in master clock mode.
  2938. *
  2939. * Leave master clock mode enabled for IRQ test because the
  2940. * timer IRQ used by the test can only happen in master clock mode.
  2941. */
  2942. if (!info->testing_irq)
  2943. clear_reg_bits(info, CHA + CCR0, BIT6);
  2944. tx_set_idle(info);
  2945. tx_stop(info);
  2946. rx_stop(info);
  2947. }
  2948. static void rx_stop(MGSLPC_INFO *info)
  2949. {
  2950. if (debug_level >= DEBUG_LEVEL_ISR)
  2951. printk("%s(%d):rx_stop(%s)\n",
  2952. __FILE__,__LINE__, info->device_name );
  2953. /* MODE:03 RAC Receiver Active, 0=inactive */
  2954. clear_reg_bits(info, CHA + MODE, BIT3);
  2955. info->rx_enabled = 0;
  2956. info->rx_overflow = 0;
  2957. }
  2958. static void rx_start(MGSLPC_INFO *info)
  2959. {
  2960. if (debug_level >= DEBUG_LEVEL_ISR)
  2961. printk("%s(%d):rx_start(%s)\n",
  2962. __FILE__,__LINE__, info->device_name );
  2963. rx_reset_buffers(info);
  2964. info->rx_enabled = 0;
  2965. info->rx_overflow = 0;
  2966. /* MODE:03 RAC Receiver Active, 1=active */
  2967. set_reg_bits(info, CHA + MODE, BIT3);
  2968. info->rx_enabled = 1;
  2969. }
  2970. static void tx_start(MGSLPC_INFO *info)
  2971. {
  2972. if (debug_level >= DEBUG_LEVEL_ISR)
  2973. printk("%s(%d):tx_start(%s)\n",
  2974. __FILE__,__LINE__, info->device_name );
  2975. if (info->tx_count) {
  2976. /* If auto RTS enabled and RTS is inactive, then assert */
  2977. /* RTS and set a flag indicating that the driver should */
  2978. /* negate RTS when the transmission completes. */
  2979. info->drop_rts_on_tx_done = 0;
  2980. if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
  2981. get_signals(info);
  2982. if (!(info->serial_signals & SerialSignal_RTS)) {
  2983. info->serial_signals |= SerialSignal_RTS;
  2984. set_signals(info);
  2985. info->drop_rts_on_tx_done = 1;
  2986. }
  2987. }
  2988. if (info->params.mode == MGSL_MODE_ASYNC) {
  2989. if (!info->tx_active) {
  2990. info->tx_active = 1;
  2991. tx_ready(info);
  2992. }
  2993. } else {
  2994. info->tx_active = 1;
  2995. tx_ready(info);
  2996. info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
  2997. add_timer(&info->tx_timer);
  2998. }
  2999. }
  3000. if (!info->tx_enabled)
  3001. info->tx_enabled = 1;
  3002. }
  3003. static void tx_stop(MGSLPC_INFO *info)
  3004. {
  3005. if (debug_level >= DEBUG_LEVEL_ISR)
  3006. printk("%s(%d):tx_stop(%s)\n",
  3007. __FILE__,__LINE__, info->device_name );
  3008. del_timer(&info->tx_timer);
  3009. info->tx_enabled = 0;
  3010. info->tx_active = 0;
  3011. }
  3012. /* Reset the adapter to a known state and prepare it for further use.
  3013. */
  3014. static void reset_device(MGSLPC_INFO *info)
  3015. {
  3016. /* power up both channels (set BIT7) */
  3017. write_reg(info, CHA + CCR0, 0x80);
  3018. write_reg(info, CHB + CCR0, 0x80);
  3019. write_reg(info, CHA + MODE, 0);
  3020. write_reg(info, CHB + MODE, 0);
  3021. /* disable all interrupts */
  3022. irq_disable(info, CHA, 0xffff);
  3023. irq_disable(info, CHB, 0xffff);
  3024. port_irq_disable(info, 0xff);
  3025. /* PCR Port Configuration Register
  3026. *
  3027. * 07..04 DEC[3..0] Serial I/F select outputs
  3028. * 03 output, 1=AUTO CTS control enabled
  3029. * 02 RI Ring Indicator input 0=active
  3030. * 01 DSR input 0=active
  3031. * 00 DTR output 0=active
  3032. *
  3033. * 0000 0110
  3034. */
  3035. write_reg(info, PCR, 0x06);
  3036. /* PVR Port Value Register
  3037. *
  3038. * 07..04 DEC[3..0] Serial I/F select (0000=disabled)
  3039. * 03 AUTO CTS output 1=enabled
  3040. * 02 RI Ring Indicator input
  3041. * 01 DSR input
  3042. * 00 DTR output (1=inactive)
  3043. *
  3044. * 0000 0001
  3045. */
  3046. // write_reg(info, PVR, PVR_DTR);
  3047. /* IPC Interrupt Port Configuration
  3048. *
  3049. * 07 VIS 1=Masked interrupts visible
  3050. * 06..05 Reserved, 0
  3051. * 04..03 SLA Slave address, 00 ignored
  3052. * 02 CASM Cascading Mode, 1=daisy chain
  3053. * 01..00 IC[1..0] Interrupt Config, 01=push-pull output, active low
  3054. *
  3055. * 0000 0101
  3056. */
  3057. write_reg(info, IPC, 0x05);
  3058. }
  3059. static void async_mode(MGSLPC_INFO *info)
  3060. {
  3061. unsigned char val;
  3062. /* disable all interrupts */
  3063. irq_disable(info, CHA, 0xffff);
  3064. irq_disable(info, CHB, 0xffff);
  3065. port_irq_disable(info, 0xff);
  3066. /* MODE
  3067. *
  3068. * 07 Reserved, 0
  3069. * 06 FRTS RTS State, 0=active
  3070. * 05 FCTS Flow Control on CTS
  3071. * 04 FLON Flow Control Enable
  3072. * 03 RAC Receiver Active, 0 = inactive
  3073. * 02 RTS 0=Auto RTS, 1=manual RTS
  3074. * 01 TRS Timer Resolution, 1=512
  3075. * 00 TLP Test Loop, 0 = no loop
  3076. *
  3077. * 0000 0110
  3078. */
  3079. val = 0x06;
  3080. if (info->params.loopback)
  3081. val |= BIT0;
  3082. /* preserve RTS state */
  3083. if (!(info->serial_signals & SerialSignal_RTS))
  3084. val |= BIT6;
  3085. write_reg(info, CHA + MODE, val);
  3086. /* CCR0
  3087. *
  3088. * 07 PU Power Up, 1=active, 0=power down
  3089. * 06 MCE Master Clock Enable, 1=enabled
  3090. * 05 Reserved, 0
  3091. * 04..02 SC[2..0] Encoding, 000=NRZ
  3092. * 01..00 SM[1..0] Serial Mode, 11=Async
  3093. *
  3094. * 1000 0011
  3095. */
  3096. write_reg(info, CHA + CCR0, 0x83);
  3097. /* CCR1
  3098. *
  3099. * 07..05 Reserved, 0
  3100. * 04 ODS Output Driver Select, 1=TxD is push-pull output
  3101. * 03 BCR Bit Clock Rate, 1=16x
  3102. * 02..00 CM[2..0] Clock Mode, 111=BRG
  3103. *
  3104. * 0001 1111
  3105. */
  3106. write_reg(info, CHA + CCR1, 0x1f);
  3107. /* CCR2 (channel A)
  3108. *
  3109. * 07..06 BGR[9..8] Baud rate bits 9..8
  3110. * 05 BDF Baud rate divisor factor, 0=1, 1=BGR value
  3111. * 04 SSEL Clock source select, 1=submode b
  3112. * 03 TOE 0=TxCLK is input, 0=TxCLK is input
  3113. * 02 RWX Read/Write Exchange 0=disabled
  3114. * 01 Reserved, 0
  3115. * 00 DIV, data inversion 0=disabled, 1=enabled
  3116. *
  3117. * 0001 0000
  3118. */
  3119. write_reg(info, CHA + CCR2, 0x10);
  3120. /* CCR3
  3121. *
  3122. * 07..01 Reserved, 0
  3123. * 00 PSD DPLL Phase Shift Disable
  3124. *
  3125. * 0000 0000
  3126. */
  3127. write_reg(info, CHA + CCR3, 0);
  3128. /* CCR4
  3129. *
  3130. * 07 MCK4 Master Clock Divide by 4, 1=enabled
  3131. * 06 EBRG Enhanced Baud Rate Generator Mode, 1=enabled
  3132. * 05 TST1 Test Pin, 0=normal operation
  3133. * 04 ICD Ivert Carrier Detect, 1=enabled (active low)
  3134. * 03..00 Reserved, must be 0
  3135. *
  3136. * 0101 0000
  3137. */
  3138. write_reg(info, CHA + CCR4, 0x50);
  3139. mgslpc_set_rate(info, CHA, info->params.data_rate * 16);
  3140. /* DAFO Data Format
  3141. *
  3142. * 07 Reserved, 0
  3143. * 06 XBRK transmit break, 0=normal operation
  3144. * 05 Stop bits (0=1, 1=2)
  3145. * 04..03 PAR[1..0] Parity (01=odd, 10=even)
  3146. * 02 PAREN Parity Enable
  3147. * 01..00 CHL[1..0] Character Length (00=8, 01=7)
  3148. *
  3149. */
  3150. val = 0x00;
  3151. if (info->params.data_bits != 8)
  3152. val |= BIT0; /* 7 bits */
  3153. if (info->params.stop_bits != 1)
  3154. val |= BIT5;
  3155. if (info->params.parity != ASYNC_PARITY_NONE)
  3156. {
  3157. val |= BIT2; /* Parity enable */
  3158. if (info->params.parity == ASYNC_PARITY_ODD)
  3159. val |= BIT3;
  3160. else
  3161. val |= BIT4;
  3162. }
  3163. write_reg(info, CHA + DAFO, val);
  3164. /* RFC Rx FIFO Control
  3165. *
  3166. * 07 Reserved, 0
  3167. * 06 DPS, 1=parity bit not stored in data byte
  3168. * 05 DXS, 0=all data stored in FIFO (including XON/XOFF)
  3169. * 04 RFDF Rx FIFO Data Format, 1=status byte stored in FIFO
  3170. * 03..02 RFTH[1..0], rx threshold, 11=16 status + 16 data byte
  3171. * 01 Reserved, 0
  3172. * 00 TCDE Terminate Char Detect Enable, 0=disabled
  3173. *
  3174. * 0101 1100
  3175. */
  3176. write_reg(info, CHA + RFC, 0x5c);
  3177. /* RLCR Receive length check register
  3178. *
  3179. * Max frame length = (RL + 1) * 32
  3180. */
  3181. write_reg(info, CHA + RLCR, 0);
  3182. /* XBCH Transmit Byte Count High
  3183. *
  3184. * 07 DMA mode, 0 = interrupt driven
  3185. * 06 NRM, 0=ABM (ignored)
  3186. * 05 CAS Carrier Auto Start
  3187. * 04 XC Transmit Continuously (ignored)
  3188. * 03..00 XBC[10..8] Transmit byte count bits 10..8
  3189. *
  3190. * 0000 0000
  3191. */
  3192. val = 0x00;
  3193. if (info->params.flags & HDLC_FLAG_AUTO_DCD)
  3194. val |= BIT5;
  3195. write_reg(info, CHA + XBCH, val);
  3196. if (info->params.flags & HDLC_FLAG_AUTO_CTS)
  3197. irq_enable(info, CHA, IRQ_CTS);
  3198. /* MODE:03 RAC Receiver Active, 1=active */
  3199. set_reg_bits(info, CHA + MODE, BIT3);
  3200. enable_auxclk(info);
  3201. if (info->params.flags & HDLC_FLAG_AUTO_CTS) {
  3202. irq_enable(info, CHB, IRQ_CTS);
  3203. /* PVR[3] 1=AUTO CTS active */
  3204. set_reg_bits(info, CHA + PVR, BIT3);
  3205. } else
  3206. clear_reg_bits(info, CHA + PVR, BIT3);
  3207. irq_enable(info, CHA,
  3208. IRQ_RXEOM + IRQ_RXFIFO + IRQ_BREAK_ON + IRQ_RXTIME +
  3209. IRQ_ALLSENT + IRQ_TXFIFO);
  3210. issue_command(info, CHA, CMD_TXRESET + CMD_RXRESET);
  3211. wait_command_complete(info, CHA);
  3212. read_reg16(info, CHA + ISR); /* clear pending IRQs */
  3213. }
  3214. /* Set the HDLC idle mode for the transmitter.
  3215. */
  3216. static void tx_set_idle(MGSLPC_INFO *info)
  3217. {
  3218. /* Note: ESCC2 only supports flags and one idle modes */
  3219. if (info->idle_mode == HDLC_TXIDLE_FLAGS)
  3220. set_reg_bits(info, CHA + CCR1, BIT3);
  3221. else
  3222. clear_reg_bits(info, CHA + CCR1, BIT3);
  3223. }
  3224. /* get state of the V24 status (input) signals.
  3225. */
  3226. static void get_signals(MGSLPC_INFO *info)
  3227. {
  3228. unsigned char status = 0;
  3229. /* preserve DTR and RTS */
  3230. info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
  3231. if (read_reg(info, CHB + VSTR) & BIT7)
  3232. info->serial_signals |= SerialSignal_DCD;
  3233. if (read_reg(info, CHB + STAR) & BIT1)
  3234. info->serial_signals |= SerialSignal_CTS;
  3235. status = read_reg(info, CHA + PVR);
  3236. if (!(status & PVR_RI))
  3237. info->serial_signals |= SerialSignal_RI;
  3238. if (!(status & PVR_DSR))
  3239. info->serial_signals |= SerialSignal_DSR;
  3240. }
  3241. /* Set the state of DTR and RTS based on contents of
  3242. * serial_signals member of device extension.
  3243. */
  3244. static void set_signals(MGSLPC_INFO *info)
  3245. {
  3246. unsigned char val;
  3247. val = read_reg(info, CHA + MODE);
  3248. if (info->params.mode == MGSL_MODE_ASYNC) {
  3249. if (info->serial_signals & SerialSignal_RTS)
  3250. val &= ~BIT6;
  3251. else
  3252. val |= BIT6;
  3253. } else {
  3254. if (info->serial_signals & SerialSignal_RTS)
  3255. val |= BIT2;
  3256. else
  3257. val &= ~BIT2;
  3258. }
  3259. write_reg(info, CHA + MODE, val);
  3260. if (info->serial_signals & SerialSignal_DTR)
  3261. clear_reg_bits(info, CHA + PVR, PVR_DTR);
  3262. else
  3263. set_reg_bits(info, CHA + PVR, PVR_DTR);
  3264. }
  3265. static void rx_reset_buffers(MGSLPC_INFO *info)
  3266. {
  3267. RXBUF *buf;
  3268. int i;
  3269. info->rx_put = 0;
  3270. info->rx_get = 0;
  3271. info->rx_frame_count = 0;
  3272. for (i=0 ; i < info->rx_buf_count ; i++) {
  3273. buf = (RXBUF*)(info->rx_buf + (i * info->rx_buf_size));
  3274. buf->status = buf->count = 0;
  3275. }
  3276. }
  3277. /* Attempt to return a received HDLC frame
  3278. * Only frames received without errors are returned.
  3279. *
  3280. * Returns 1 if frame returned, otherwise 0
  3281. */
  3282. static int rx_get_frame(MGSLPC_INFO *info)
  3283. {
  3284. unsigned short status;
  3285. RXBUF *buf;
  3286. unsigned int framesize = 0;
  3287. unsigned long flags;
  3288. struct tty_struct *tty = info->tty;
  3289. int return_frame = 0;
  3290. if (info->rx_frame_count == 0)
  3291. return 0;
  3292. buf = (RXBUF*)(info->rx_buf + (info->rx_get * info->rx_buf_size));
  3293. status = buf->status;
  3294. /* 07 VFR 1=valid frame
  3295. * 06 RDO 1=data overrun
  3296. * 05 CRC 1=OK, 0=error
  3297. * 04 RAB 1=frame aborted
  3298. */
  3299. if ((status & 0xf0) != 0xA0) {
  3300. if (!(status & BIT7) || (status & BIT4))
  3301. info->icount.rxabort++;
  3302. else if (status & BIT6)
  3303. info->icount.rxover++;
  3304. else if (!(status & BIT5)) {
  3305. info->icount.rxcrc++;
  3306. if (info->params.crc_type & HDLC_CRC_RETURN_EX)
  3307. return_frame = 1;
  3308. }
  3309. framesize = 0;
  3310. #ifdef CONFIG_HDLC
  3311. {
  3312. struct net_device_stats *stats = hdlc_stats(info->netdev);
  3313. stats->rx_errors++;
  3314. stats->rx_frame_errors++;
  3315. }
  3316. #endif
  3317. } else
  3318. return_frame = 1;
  3319. if (return_frame)
  3320. framesize = buf->count;
  3321. if (debug_level >= DEBUG_LEVEL_BH)
  3322. printk("%s(%d):rx_get_frame(%s) status=%04X size=%d\n",
  3323. __FILE__,__LINE__,info->device_name,status,framesize);
  3324. if (debug_level >= DEBUG_LEVEL_DATA)
  3325. trace_block(info, buf->data, framesize, 0);
  3326. if (framesize) {
  3327. if ((info->params.crc_type & HDLC_CRC_RETURN_EX &&
  3328. framesize+1 > info->max_frame_size) ||
  3329. framesize > info->max_frame_size)
  3330. info->icount.rxlong++;
  3331. else {
  3332. if (status & BIT5)
  3333. info->icount.rxok++;
  3334. if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
  3335. *(buf->data + framesize) = status & BIT5 ? RX_OK:RX_CRC_ERROR;
  3336. ++framesize;
  3337. }
  3338. #ifdef CONFIG_HDLC
  3339. if (info->netcount)
  3340. hdlcdev_rx(info, buf->data, framesize);
  3341. else
  3342. #endif
  3343. ldisc_receive_buf(tty, buf->data, info->flag_buf, framesize);
  3344. }
  3345. }
  3346. spin_lock_irqsave(&info->lock,flags);
  3347. buf->status = buf->count = 0;
  3348. info->rx_frame_count--;
  3349. info->rx_get++;
  3350. if (info->rx_get >= info->rx_buf_count)
  3351. info->rx_get = 0;
  3352. spin_unlock_irqrestore(&info->lock,flags);
  3353. return 1;
  3354. }
  3355. static BOOLEAN register_test(MGSLPC_INFO *info)
  3356. {
  3357. static unsigned char patterns[] =
  3358. { 0x00, 0xff, 0xaa, 0x55, 0x69, 0x96, 0x0f };
  3359. static unsigned int count = ARRAY_SIZE(patterns);
  3360. unsigned int i;
  3361. BOOLEAN rc = TRUE;
  3362. unsigned long flags;
  3363. spin_lock_irqsave(&info->lock,flags);
  3364. reset_device(info);
  3365. for (i = 0; i < count; i++) {
  3366. write_reg(info, XAD1, patterns[i]);
  3367. write_reg(info, XAD2, patterns[(i + 1) % count]);
  3368. if ((read_reg(info, XAD1) != patterns[i]) ||
  3369. (read_reg(info, XAD2) != patterns[(i + 1) % count])) {
  3370. rc = FALSE;
  3371. break;
  3372. }
  3373. }
  3374. spin_unlock_irqrestore(&info->lock,flags);
  3375. return rc;
  3376. }
  3377. static BOOLEAN irq_test(MGSLPC_INFO *info)
  3378. {
  3379. unsigned long end_time;
  3380. unsigned long flags;
  3381. spin_lock_irqsave(&info->lock,flags);
  3382. reset_device(info);
  3383. info->testing_irq = TRUE;
  3384. hdlc_mode(info);
  3385. info->irq_occurred = FALSE;
  3386. /* init hdlc mode */
  3387. irq_enable(info, CHA, IRQ_TIMER);
  3388. write_reg(info, CHA + TIMR, 0); /* 512 cycles */
  3389. issue_command(info, CHA, CMD_START_TIMER);
  3390. spin_unlock_irqrestore(&info->lock,flags);
  3391. end_time=100;
  3392. while(end_time-- && !info->irq_occurred) {
  3393. msleep_interruptible(10);
  3394. }
  3395. info->testing_irq = FALSE;
  3396. spin_lock_irqsave(&info->lock,flags);
  3397. reset_device(info);
  3398. spin_unlock_irqrestore(&info->lock,flags);
  3399. return info->irq_occurred ? TRUE : FALSE;
  3400. }
  3401. static int adapter_test(MGSLPC_INFO *info)
  3402. {
  3403. if (!register_test(info)) {
  3404. info->init_error = DiagStatus_AddressFailure;
  3405. printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
  3406. __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
  3407. return -ENODEV;
  3408. }
  3409. if (!irq_test(info)) {
  3410. info->init_error = DiagStatus_IrqFailure;
  3411. printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
  3412. __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
  3413. return -ENODEV;
  3414. }
  3415. if (debug_level >= DEBUG_LEVEL_INFO)
  3416. printk("%s(%d):device %s passed diagnostics\n",
  3417. __FILE__,__LINE__,info->device_name);
  3418. return 0;
  3419. }
  3420. static void trace_block(MGSLPC_INFO *info,const char* data, int count, int xmit)
  3421. {
  3422. int i;
  3423. int linecount;
  3424. if (xmit)
  3425. printk("%s tx data:\n",info->device_name);
  3426. else
  3427. printk("%s rx data:\n",info->device_name);
  3428. while(count) {
  3429. if (count > 16)
  3430. linecount = 16;
  3431. else
  3432. linecount = count;
  3433. for(i=0;i<linecount;i++)
  3434. printk("%02X ",(unsigned char)data[i]);
  3435. for(;i<17;i++)
  3436. printk(" ");
  3437. for(i=0;i<linecount;i++) {
  3438. if (data[i]>=040 && data[i]<=0176)
  3439. printk("%c",data[i]);
  3440. else
  3441. printk(".");
  3442. }
  3443. printk("\n");
  3444. data += linecount;
  3445. count -= linecount;
  3446. }
  3447. }
  3448. /* HDLC frame time out
  3449. * update stats and do tx completion processing
  3450. */
  3451. static void tx_timeout(unsigned long context)
  3452. {
  3453. MGSLPC_INFO *info = (MGSLPC_INFO*)context;
  3454. unsigned long flags;
  3455. if ( debug_level >= DEBUG_LEVEL_INFO )
  3456. printk( "%s(%d):tx_timeout(%s)\n",
  3457. __FILE__,__LINE__,info->device_name);
  3458. if(info->tx_active &&
  3459. info->params.mode == MGSL_MODE_HDLC) {
  3460. info->icount.txtimeout++;
  3461. }
  3462. spin_lock_irqsave(&info->lock,flags);
  3463. info->tx_active = 0;
  3464. info->tx_count = info->tx_put = info->tx_get = 0;
  3465. spin_unlock_irqrestore(&info->lock,flags);
  3466. #ifdef CONFIG_HDLC
  3467. if (info->netcount)
  3468. hdlcdev_tx_done(info);
  3469. else
  3470. #endif
  3471. bh_transmit(info);
  3472. }
  3473. #ifdef CONFIG_HDLC
  3474. /**
  3475. * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
  3476. * set encoding and frame check sequence (FCS) options
  3477. *
  3478. * dev pointer to network device structure
  3479. * encoding serial encoding setting
  3480. * parity FCS setting
  3481. *
  3482. * returns 0 if success, otherwise error code
  3483. */
  3484. static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
  3485. unsigned short parity)
  3486. {
  3487. MGSLPC_INFO *info = dev_to_port(dev);
  3488. unsigned char new_encoding;
  3489. unsigned short new_crctype;
  3490. /* return error if TTY interface open */
  3491. if (info->count)
  3492. return -EBUSY;
  3493. switch (encoding)
  3494. {
  3495. case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
  3496. case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
  3497. case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
  3498. case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
  3499. case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
  3500. default: return -EINVAL;
  3501. }
  3502. switch (parity)
  3503. {
  3504. case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
  3505. case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
  3506. case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
  3507. default: return -EINVAL;
  3508. }
  3509. info->params.encoding = new_encoding;
  3510. info->params.crc_type = new_crctype;
  3511. /* if network interface up, reprogram hardware */
  3512. if (info->netcount)
  3513. mgslpc_program_hw(info);
  3514. return 0;
  3515. }
  3516. /**
  3517. * called by generic HDLC layer to send frame
  3518. *
  3519. * skb socket buffer containing HDLC frame
  3520. * dev pointer to network device structure
  3521. *
  3522. * returns 0 if success, otherwise error code
  3523. */
  3524. static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
  3525. {
  3526. MGSLPC_INFO *info = dev_to_port(dev);
  3527. struct net_device_stats *stats = hdlc_stats(dev);
  3528. unsigned long flags;
  3529. if (debug_level >= DEBUG_LEVEL_INFO)
  3530. printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
  3531. /* stop sending until this frame completes */
  3532. netif_stop_queue(dev);
  3533. /* copy data to device buffers */
  3534. memcpy(info->tx_buf, skb->data, skb->len);
  3535. info->tx_get = 0;
  3536. info->tx_put = info->tx_count = skb->len;
  3537. /* update network statistics */
  3538. stats->tx_packets++;
  3539. stats->tx_bytes += skb->len;
  3540. /* done with socket buffer, so free it */
  3541. dev_kfree_skb(skb);
  3542. /* save start time for transmit timeout detection */
  3543. dev->trans_start = jiffies;
  3544. /* start hardware transmitter if necessary */
  3545. spin_lock_irqsave(&info->lock,flags);
  3546. if (!info->tx_active)
  3547. tx_start(info);
  3548. spin_unlock_irqrestore(&info->lock,flags);
  3549. return 0;
  3550. }
  3551. /**
  3552. * called by network layer when interface enabled
  3553. * claim resources and initialize hardware
  3554. *
  3555. * dev pointer to network device structure
  3556. *
  3557. * returns 0 if success, otherwise error code
  3558. */
  3559. static int hdlcdev_open(struct net_device *dev)
  3560. {
  3561. MGSLPC_INFO *info = dev_to_port(dev);
  3562. int rc;
  3563. unsigned long flags;
  3564. if (debug_level >= DEBUG_LEVEL_INFO)
  3565. printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
  3566. /* generic HDLC layer open processing */
  3567. if ((rc = hdlc_open(dev)))
  3568. return rc;
  3569. /* arbitrate between network and tty opens */
  3570. spin_lock_irqsave(&info->netlock, flags);
  3571. if (info->count != 0 || info->netcount != 0) {
  3572. printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
  3573. spin_unlock_irqrestore(&info->netlock, flags);
  3574. return -EBUSY;
  3575. }
  3576. info->netcount=1;
  3577. spin_unlock_irqrestore(&info->netlock, flags);
  3578. /* claim resources and init adapter */
  3579. if ((rc = startup(info)) != 0) {
  3580. spin_lock_irqsave(&info->netlock, flags);
  3581. info->netcount=0;
  3582. spin_unlock_irqrestore(&info->netlock, flags);
  3583. return rc;
  3584. }
  3585. /* assert DTR and RTS, apply hardware settings */
  3586. info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
  3587. mgslpc_program_hw(info);
  3588. /* enable network layer transmit */
  3589. dev->trans_start = jiffies;
  3590. netif_start_queue(dev);
  3591. /* inform generic HDLC layer of current DCD status */
  3592. spin_lock_irqsave(&info->lock, flags);
  3593. get_signals(info);
  3594. spin_unlock_irqrestore(&info->lock, flags);
  3595. if (info->serial_signals & SerialSignal_DCD)
  3596. netif_carrier_on(dev);
  3597. else
  3598. netif_carrier_off(dev);
  3599. return 0;
  3600. }
  3601. /**
  3602. * called by network layer when interface is disabled
  3603. * shutdown hardware and release resources
  3604. *
  3605. * dev pointer to network device structure
  3606. *
  3607. * returns 0 if success, otherwise error code
  3608. */
  3609. static int hdlcdev_close(struct net_device *dev)
  3610. {
  3611. MGSLPC_INFO *info = dev_to_port(dev);
  3612. unsigned long flags;
  3613. if (debug_level >= DEBUG_LEVEL_INFO)
  3614. printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
  3615. netif_stop_queue(dev);
  3616. /* shutdown adapter and release resources */
  3617. shutdown(info);
  3618. hdlc_close(dev);
  3619. spin_lock_irqsave(&info->netlock, flags);
  3620. info->netcount=0;
  3621. spin_unlock_irqrestore(&info->netlock, flags);
  3622. return 0;
  3623. }
  3624. /**
  3625. * called by network layer to process IOCTL call to network device
  3626. *
  3627. * dev pointer to network device structure
  3628. * ifr pointer to network interface request structure
  3629. * cmd IOCTL command code
  3630. *
  3631. * returns 0 if success, otherwise error code
  3632. */
  3633. static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  3634. {
  3635. const size_t size = sizeof(sync_serial_settings);
  3636. sync_serial_settings new_line;
  3637. sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
  3638. MGSLPC_INFO *info = dev_to_port(dev);
  3639. unsigned int flags;
  3640. if (debug_level >= DEBUG_LEVEL_INFO)
  3641. printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
  3642. /* return error if TTY interface open */
  3643. if (info->count)
  3644. return -EBUSY;
  3645. if (cmd != SIOCWANDEV)
  3646. return hdlc_ioctl(dev, ifr, cmd);
  3647. switch(ifr->ifr_settings.type) {
  3648. case IF_GET_IFACE: /* return current sync_serial_settings */
  3649. ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
  3650. if (ifr->ifr_settings.size < size) {
  3651. ifr->ifr_settings.size = size; /* data size wanted */
  3652. return -ENOBUFS;
  3653. }
  3654. flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3655. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3656. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3657. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3658. switch (flags){
  3659. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
  3660. case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
  3661. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
  3662. case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
  3663. default: new_line.clock_type = CLOCK_DEFAULT;
  3664. }
  3665. new_line.clock_rate = info->params.clock_speed;
  3666. new_line.loopback = info->params.loopback ? 1:0;
  3667. if (copy_to_user(line, &new_line, size))
  3668. return -EFAULT;
  3669. return 0;
  3670. case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
  3671. if(!capable(CAP_NET_ADMIN))
  3672. return -EPERM;
  3673. if (copy_from_user(&new_line, line, size))
  3674. return -EFAULT;
  3675. switch (new_line.clock_type)
  3676. {
  3677. case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
  3678. case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
  3679. case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
  3680. case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
  3681. case CLOCK_DEFAULT: flags = info->params.flags &
  3682. (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3683. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3684. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3685. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
  3686. default: return -EINVAL;
  3687. }
  3688. if (new_line.loopback != 0 && new_line.loopback != 1)
  3689. return -EINVAL;
  3690. info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
  3691. HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
  3692. HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
  3693. HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
  3694. info->params.flags |= flags;
  3695. info->params.loopback = new_line.loopback;
  3696. if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
  3697. info->params.clock_speed = new_line.clock_rate;
  3698. else
  3699. info->params.clock_speed = 0;
  3700. /* if network interface up, reprogram hardware */
  3701. if (info->netcount)
  3702. mgslpc_program_hw(info);
  3703. return 0;
  3704. default:
  3705. return hdlc_ioctl(dev, ifr, cmd);
  3706. }
  3707. }
  3708. /**
  3709. * called by network layer when transmit timeout is detected
  3710. *
  3711. * dev pointer to network device structure
  3712. */
  3713. static void hdlcdev_tx_timeout(struct net_device *dev)
  3714. {
  3715. MGSLPC_INFO *info = dev_to_port(dev);
  3716. struct net_device_stats *stats = hdlc_stats(dev);
  3717. unsigned long flags;
  3718. if (debug_level >= DEBUG_LEVEL_INFO)
  3719. printk("hdlcdev_tx_timeout(%s)\n",dev->name);
  3720. stats->tx_errors++;
  3721. stats->tx_aborted_errors++;
  3722. spin_lock_irqsave(&info->lock,flags);
  3723. tx_stop(info);
  3724. spin_unlock_irqrestore(&info->lock,flags);
  3725. netif_wake_queue(dev);
  3726. }
  3727. /**
  3728. * called by device driver when transmit completes
  3729. * reenable network layer transmit if stopped
  3730. *
  3731. * info pointer to device instance information
  3732. */
  3733. static void hdlcdev_tx_done(MGSLPC_INFO *info)
  3734. {
  3735. if (netif_queue_stopped(info->netdev))
  3736. netif_wake_queue(info->netdev);
  3737. }
  3738. /**
  3739. * called by device driver when frame received
  3740. * pass frame to network layer
  3741. *
  3742. * info pointer to device instance information
  3743. * buf pointer to buffer contianing frame data
  3744. * size count of data bytes in buf
  3745. */
  3746. static void hdlcdev_rx(MGSLPC_INFO *info, char *buf, int size)
  3747. {
  3748. struct sk_buff *skb = dev_alloc_skb(size);
  3749. struct net_device *dev = info->netdev;
  3750. struct net_device_stats *stats = hdlc_stats(dev);
  3751. if (debug_level >= DEBUG_LEVEL_INFO)
  3752. printk("hdlcdev_rx(%s)\n",dev->name);
  3753. if (skb == NULL) {
  3754. printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
  3755. stats->rx_dropped++;
  3756. return;
  3757. }
  3758. memcpy(skb_put(skb, size),buf,size);
  3759. skb->protocol = hdlc_type_trans(skb, info->netdev);
  3760. stats->rx_packets++;
  3761. stats->rx_bytes += size;
  3762. netif_rx(skb);
  3763. info->netdev->last_rx = jiffies;
  3764. }
  3765. /**
  3766. * called by device driver when adding device instance
  3767. * do generic HDLC initialization
  3768. *
  3769. * info pointer to device instance information
  3770. *
  3771. * returns 0 if success, otherwise error code
  3772. */
  3773. static int hdlcdev_init(MGSLPC_INFO *info)
  3774. {
  3775. int rc;
  3776. struct net_device *dev;
  3777. hdlc_device *hdlc;
  3778. /* allocate and initialize network and HDLC layer objects */
  3779. if (!(dev = alloc_hdlcdev(info))) {
  3780. printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
  3781. return -ENOMEM;
  3782. }
  3783. /* for network layer reporting purposes only */
  3784. dev->base_addr = info->io_base;
  3785. dev->irq = info->irq_level;
  3786. /* network layer callbacks and settings */
  3787. dev->do_ioctl = hdlcdev_ioctl;
  3788. dev->open = hdlcdev_open;
  3789. dev->stop = hdlcdev_close;
  3790. dev->tx_timeout = hdlcdev_tx_timeout;
  3791. dev->watchdog_timeo = 10*HZ;
  3792. dev->tx_queue_len = 50;
  3793. /* generic HDLC layer callbacks and settings */
  3794. hdlc = dev_to_hdlc(dev);
  3795. hdlc->attach = hdlcdev_attach;
  3796. hdlc->xmit = hdlcdev_xmit;
  3797. /* register objects with HDLC layer */
  3798. if ((rc = register_hdlc_device(dev))) {
  3799. printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
  3800. free_netdev(dev);
  3801. return rc;
  3802. }
  3803. info->netdev = dev;
  3804. return 0;
  3805. }
  3806. /**
  3807. * called by device driver when removing device instance
  3808. * do generic HDLC cleanup
  3809. *
  3810. * info pointer to device instance information
  3811. */
  3812. static void hdlcdev_exit(MGSLPC_INFO *info)
  3813. {
  3814. unregister_hdlc_device(info->netdev);
  3815. free_netdev(info->netdev);
  3816. info->netdev = NULL;
  3817. }
  3818. #endif /* CONFIG_HDLC */