io_apic.c 46 KB

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  1. /*
  2. * Intel IO-APIC support for multi-Pentium hosts.
  3. *
  4. * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
  5. *
  6. * Many thanks to Stig Venaas for trying out countless experimental
  7. * patches and reporting/debugging problems patiently!
  8. *
  9. * (c) 1999, Multiple IO-APIC support, developed by
  10. * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11. * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12. * further tested and cleaned up by Zach Brown <zab@redhat.com>
  13. * and Ingo Molnar <mingo@redhat.com>
  14. *
  15. * Fixes
  16. * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
  17. * thanks to Eric Gilmore
  18. * and Rolf G. Tews
  19. * for testing these extensively
  20. * Paul Diefenbaugh : Added full ACPI support
  21. */
  22. #include <linux/mm.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/sched.h>
  27. #include <linux/smp_lock.h>
  28. #include <linux/mc146818rtc.h>
  29. #include <linux/acpi.h>
  30. #include <linux/sysdev.h>
  31. #ifdef CONFIG_ACPI
  32. #include <acpi/acpi_bus.h>
  33. #endif
  34. #include <asm/io.h>
  35. #include <asm/smp.h>
  36. #include <asm/desc.h>
  37. #include <asm/proto.h>
  38. #include <asm/mach_apic.h>
  39. #include <asm/acpi.h>
  40. #include <asm/dma.h>
  41. #include <asm/nmi.h>
  42. #define __apicdebuginit __init
  43. int sis_apic_bug; /* not actually supported, dummy for compile */
  44. static int no_timer_check;
  45. static int disable_timer_pin_1 __initdata;
  46. int timer_over_8254 __initdata = 0;
  47. /* Where if anywhere is the i8259 connect in external int mode */
  48. static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  49. static DEFINE_SPINLOCK(ioapic_lock);
  50. static DEFINE_SPINLOCK(vector_lock);
  51. /*
  52. * # of IRQ routing registers
  53. */
  54. int nr_ioapic_registers[MAX_IO_APICS];
  55. /*
  56. * Rough estimation of how many shared IRQs there are, can
  57. * be changed anytime.
  58. */
  59. #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  60. #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  61. /*
  62. * This is performance-critical, we want to do it O(1)
  63. *
  64. * the indexing order of this array favors 1:1 mappings
  65. * between pins and IRQs.
  66. */
  67. static struct irq_pin_list {
  68. short apic, pin, next;
  69. } irq_2_pin[PIN_MAP_SIZE];
  70. int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  71. #ifdef CONFIG_PCI_MSI
  72. #define vector_to_irq(vector) \
  73. (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  74. #else
  75. #define vector_to_irq(vector) (vector)
  76. #endif
  77. #define __DO_ACTION(R, ACTION, FINAL) \
  78. \
  79. { \
  80. int pin; \
  81. struct irq_pin_list *entry = irq_2_pin + irq; \
  82. \
  83. BUG_ON(irq >= NR_IRQS); \
  84. for (;;) { \
  85. unsigned int reg; \
  86. pin = entry->pin; \
  87. if (pin == -1) \
  88. break; \
  89. reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
  90. reg ACTION; \
  91. io_apic_modify(entry->apic, reg); \
  92. if (!entry->next) \
  93. break; \
  94. entry = irq_2_pin + entry->next; \
  95. } \
  96. FINAL; \
  97. }
  98. union entry_union {
  99. struct { u32 w1, w2; };
  100. struct IO_APIC_route_entry entry;
  101. };
  102. static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
  103. {
  104. union entry_union eu;
  105. unsigned long flags;
  106. spin_lock_irqsave(&ioapic_lock, flags);
  107. eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
  108. eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
  109. spin_unlock_irqrestore(&ioapic_lock, flags);
  110. return eu.entry;
  111. }
  112. static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
  113. {
  114. unsigned long flags;
  115. union entry_union eu;
  116. eu.entry = e;
  117. spin_lock_irqsave(&ioapic_lock, flags);
  118. io_apic_write(apic, 0x10 + 2*pin, eu.w1);
  119. io_apic_write(apic, 0x11 + 2*pin, eu.w2);
  120. spin_unlock_irqrestore(&ioapic_lock, flags);
  121. }
  122. #ifdef CONFIG_SMP
  123. static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
  124. {
  125. unsigned long flags;
  126. unsigned int dest;
  127. cpumask_t tmp;
  128. cpus_and(tmp, mask, cpu_online_map);
  129. if (cpus_empty(tmp))
  130. tmp = TARGET_CPUS;
  131. cpus_and(mask, tmp, CPU_MASK_ALL);
  132. dest = cpu_mask_to_apicid(mask);
  133. /*
  134. * Only the high 8 bits are valid.
  135. */
  136. dest = SET_APIC_LOGICAL_ID(dest);
  137. spin_lock_irqsave(&ioapic_lock, flags);
  138. __DO_ACTION(1, = dest, )
  139. set_irq_info(irq, mask);
  140. spin_unlock_irqrestore(&ioapic_lock, flags);
  141. }
  142. #endif
  143. static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
  144. /*
  145. * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  146. * shared ISA-space IRQs, so we have to support them. We are super
  147. * fast in the common case, and fast for shared ISA-space IRQs.
  148. */
  149. static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  150. {
  151. static int first_free_entry = NR_IRQS;
  152. struct irq_pin_list *entry = irq_2_pin + irq;
  153. BUG_ON(irq >= NR_IRQS);
  154. while (entry->next)
  155. entry = irq_2_pin + entry->next;
  156. if (entry->pin != -1) {
  157. entry->next = first_free_entry;
  158. entry = irq_2_pin + entry->next;
  159. if (++first_free_entry >= PIN_MAP_SIZE)
  160. panic("io_apic.c: ran out of irq_2_pin entries!");
  161. }
  162. entry->apic = apic;
  163. entry->pin = pin;
  164. }
  165. #define DO_ACTION(name,R,ACTION, FINAL) \
  166. \
  167. static void name##_IO_APIC_irq (unsigned int irq) \
  168. __DO_ACTION(R, ACTION, FINAL)
  169. DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
  170. /* mask = 1 */
  171. DO_ACTION( __unmask, 0, &= 0xfffeffff, )
  172. /* mask = 0 */
  173. static void mask_IO_APIC_irq (unsigned int irq)
  174. {
  175. unsigned long flags;
  176. spin_lock_irqsave(&ioapic_lock, flags);
  177. __mask_IO_APIC_irq(irq);
  178. spin_unlock_irqrestore(&ioapic_lock, flags);
  179. }
  180. static void unmask_IO_APIC_irq (unsigned int irq)
  181. {
  182. unsigned long flags;
  183. spin_lock_irqsave(&ioapic_lock, flags);
  184. __unmask_IO_APIC_irq(irq);
  185. spin_unlock_irqrestore(&ioapic_lock, flags);
  186. }
  187. static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
  188. {
  189. struct IO_APIC_route_entry entry;
  190. /* Check delivery_mode to be sure we're not clearing an SMI pin */
  191. entry = ioapic_read_entry(apic, pin);
  192. if (entry.delivery_mode == dest_SMI)
  193. return;
  194. /*
  195. * Disable it in the IO-APIC irq-routing table:
  196. */
  197. memset(&entry, 0, sizeof(entry));
  198. entry.mask = 1;
  199. ioapic_write_entry(apic, pin, entry);
  200. }
  201. static void clear_IO_APIC (void)
  202. {
  203. int apic, pin;
  204. for (apic = 0; apic < nr_ioapics; apic++)
  205. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
  206. clear_IO_APIC_pin(apic, pin);
  207. }
  208. int skip_ioapic_setup;
  209. int ioapic_force;
  210. /* dummy parsing: see setup.c */
  211. static int __init disable_ioapic_setup(char *str)
  212. {
  213. skip_ioapic_setup = 1;
  214. return 0;
  215. }
  216. early_param("noapic", disable_ioapic_setup);
  217. /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
  218. static int __init disable_timer_pin_setup(char *arg)
  219. {
  220. disable_timer_pin_1 = 1;
  221. return 1;
  222. }
  223. __setup("disable_timer_pin_1", disable_timer_pin_setup);
  224. static int __init setup_disable_8254_timer(char *s)
  225. {
  226. timer_over_8254 = -1;
  227. return 1;
  228. }
  229. static int __init setup_enable_8254_timer(char *s)
  230. {
  231. timer_over_8254 = 2;
  232. return 1;
  233. }
  234. __setup("disable_8254_timer", setup_disable_8254_timer);
  235. __setup("enable_8254_timer", setup_enable_8254_timer);
  236. /*
  237. * Find the IRQ entry number of a certain pin.
  238. */
  239. static int find_irq_entry(int apic, int pin, int type)
  240. {
  241. int i;
  242. for (i = 0; i < mp_irq_entries; i++)
  243. if (mp_irqs[i].mpc_irqtype == type &&
  244. (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
  245. mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
  246. mp_irqs[i].mpc_dstirq == pin)
  247. return i;
  248. return -1;
  249. }
  250. /*
  251. * Find the pin to which IRQ[irq] (ISA) is connected
  252. */
  253. static int __init find_isa_irq_pin(int irq, int type)
  254. {
  255. int i;
  256. for (i = 0; i < mp_irq_entries; i++) {
  257. int lbus = mp_irqs[i].mpc_srcbus;
  258. if (test_bit(lbus, mp_bus_not_pci) &&
  259. (mp_irqs[i].mpc_irqtype == type) &&
  260. (mp_irqs[i].mpc_srcbusirq == irq))
  261. return mp_irqs[i].mpc_dstirq;
  262. }
  263. return -1;
  264. }
  265. static int __init find_isa_irq_apic(int irq, int type)
  266. {
  267. int i;
  268. for (i = 0; i < mp_irq_entries; i++) {
  269. int lbus = mp_irqs[i].mpc_srcbus;
  270. if (test_bit(lbus, mp_bus_not_pci) &&
  271. (mp_irqs[i].mpc_irqtype == type) &&
  272. (mp_irqs[i].mpc_srcbusirq == irq))
  273. break;
  274. }
  275. if (i < mp_irq_entries) {
  276. int apic;
  277. for(apic = 0; apic < nr_ioapics; apic++) {
  278. if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
  279. return apic;
  280. }
  281. }
  282. return -1;
  283. }
  284. /*
  285. * Find a specific PCI IRQ entry.
  286. * Not an __init, possibly needed by modules
  287. */
  288. static int pin_2_irq(int idx, int apic, int pin);
  289. int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
  290. {
  291. int apic, i, best_guess = -1;
  292. apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
  293. bus, slot, pin);
  294. if (mp_bus_id_to_pci_bus[bus] == -1) {
  295. apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
  296. return -1;
  297. }
  298. for (i = 0; i < mp_irq_entries; i++) {
  299. int lbus = mp_irqs[i].mpc_srcbus;
  300. for (apic = 0; apic < nr_ioapics; apic++)
  301. if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
  302. mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
  303. break;
  304. if (!test_bit(lbus, mp_bus_not_pci) &&
  305. !mp_irqs[i].mpc_irqtype &&
  306. (bus == lbus) &&
  307. (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
  308. int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
  309. if (!(apic || IO_APIC_IRQ(irq)))
  310. continue;
  311. if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
  312. return irq;
  313. /*
  314. * Use the first all-but-pin matching entry as a
  315. * best-guess fuzzy result for broken mptables.
  316. */
  317. if (best_guess < 0)
  318. best_guess = irq;
  319. }
  320. }
  321. BUG_ON(best_guess >= NR_IRQS);
  322. return best_guess;
  323. }
  324. /* ISA interrupts are always polarity zero edge triggered,
  325. * when listed as conforming in the MP table. */
  326. #define default_ISA_trigger(idx) (0)
  327. #define default_ISA_polarity(idx) (0)
  328. /* PCI interrupts are always polarity one level triggered,
  329. * when listed as conforming in the MP table. */
  330. #define default_PCI_trigger(idx) (1)
  331. #define default_PCI_polarity(idx) (1)
  332. static int __init MPBIOS_polarity(int idx)
  333. {
  334. int bus = mp_irqs[idx].mpc_srcbus;
  335. int polarity;
  336. /*
  337. * Determine IRQ line polarity (high active or low active):
  338. */
  339. switch (mp_irqs[idx].mpc_irqflag & 3)
  340. {
  341. case 0: /* conforms, ie. bus-type dependent polarity */
  342. if (test_bit(bus, mp_bus_not_pci))
  343. polarity = default_ISA_polarity(idx);
  344. else
  345. polarity = default_PCI_polarity(idx);
  346. break;
  347. case 1: /* high active */
  348. {
  349. polarity = 0;
  350. break;
  351. }
  352. case 2: /* reserved */
  353. {
  354. printk(KERN_WARNING "broken BIOS!!\n");
  355. polarity = 1;
  356. break;
  357. }
  358. case 3: /* low active */
  359. {
  360. polarity = 1;
  361. break;
  362. }
  363. default: /* invalid */
  364. {
  365. printk(KERN_WARNING "broken BIOS!!\n");
  366. polarity = 1;
  367. break;
  368. }
  369. }
  370. return polarity;
  371. }
  372. static int MPBIOS_trigger(int idx)
  373. {
  374. int bus = mp_irqs[idx].mpc_srcbus;
  375. int trigger;
  376. /*
  377. * Determine IRQ trigger mode (edge or level sensitive):
  378. */
  379. switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
  380. {
  381. case 0: /* conforms, ie. bus-type dependent */
  382. if (test_bit(bus, mp_bus_not_pci))
  383. trigger = default_ISA_trigger(idx);
  384. else
  385. trigger = default_PCI_trigger(idx);
  386. break;
  387. case 1: /* edge */
  388. {
  389. trigger = 0;
  390. break;
  391. }
  392. case 2: /* reserved */
  393. {
  394. printk(KERN_WARNING "broken BIOS!!\n");
  395. trigger = 1;
  396. break;
  397. }
  398. case 3: /* level */
  399. {
  400. trigger = 1;
  401. break;
  402. }
  403. default: /* invalid */
  404. {
  405. printk(KERN_WARNING "broken BIOS!!\n");
  406. trigger = 0;
  407. break;
  408. }
  409. }
  410. return trigger;
  411. }
  412. static inline int irq_polarity(int idx)
  413. {
  414. return MPBIOS_polarity(idx);
  415. }
  416. static inline int irq_trigger(int idx)
  417. {
  418. return MPBIOS_trigger(idx);
  419. }
  420. static int next_irq = 16;
  421. /*
  422. * gsi_irq_sharing -- Name overload! "irq" can be either a legacy IRQ
  423. * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
  424. * from ACPI, which can reach 800 in large boxen.
  425. *
  426. * Compact the sparse GSI space into a sequential IRQ series and reuse
  427. * vectors if possible.
  428. */
  429. int gsi_irq_sharing(int gsi)
  430. {
  431. int i, tries, vector;
  432. BUG_ON(gsi >= NR_IRQ_VECTORS);
  433. if (platform_legacy_irq(gsi))
  434. return gsi;
  435. if (gsi_2_irq[gsi] != 0xFF)
  436. return (int)gsi_2_irq[gsi];
  437. tries = NR_IRQS;
  438. try_again:
  439. vector = assign_irq_vector(gsi);
  440. /*
  441. * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
  442. * use of vector and if found, return that IRQ. However, we never want
  443. * to share legacy IRQs, which usually have a different trigger mode
  444. * than PCI.
  445. */
  446. for (i = 0; i < NR_IRQS; i++)
  447. if (IO_APIC_VECTOR(i) == vector)
  448. break;
  449. if (platform_legacy_irq(i)) {
  450. if (--tries >= 0) {
  451. IO_APIC_VECTOR(i) = 0;
  452. goto try_again;
  453. }
  454. panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
  455. }
  456. if (i < NR_IRQS) {
  457. gsi_2_irq[gsi] = i;
  458. printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
  459. gsi, vector, i);
  460. return i;
  461. }
  462. i = next_irq++;
  463. BUG_ON(i >= NR_IRQS);
  464. gsi_2_irq[gsi] = i;
  465. IO_APIC_VECTOR(i) = vector;
  466. printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
  467. gsi, vector, i);
  468. return i;
  469. }
  470. static int pin_2_irq(int idx, int apic, int pin)
  471. {
  472. int irq, i;
  473. int bus = mp_irqs[idx].mpc_srcbus;
  474. /*
  475. * Debugging check, we are in big trouble if this message pops up!
  476. */
  477. if (mp_irqs[idx].mpc_dstirq != pin)
  478. printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
  479. if (test_bit(bus, mp_bus_not_pci)) {
  480. irq = mp_irqs[idx].mpc_srcbusirq;
  481. } else {
  482. /*
  483. * PCI IRQs are mapped in order
  484. */
  485. i = irq = 0;
  486. while (i < apic)
  487. irq += nr_ioapic_registers[i++];
  488. irq += pin;
  489. irq = gsi_irq_sharing(irq);
  490. }
  491. BUG_ON(irq >= NR_IRQS);
  492. return irq;
  493. }
  494. static inline int IO_APIC_irq_trigger(int irq)
  495. {
  496. int apic, idx, pin;
  497. for (apic = 0; apic < nr_ioapics; apic++) {
  498. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  499. idx = find_irq_entry(apic,pin,mp_INT);
  500. if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
  501. return irq_trigger(idx);
  502. }
  503. }
  504. /*
  505. * nonexistent IRQs are edge default
  506. */
  507. return 0;
  508. }
  509. /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
  510. u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
  511. int assign_irq_vector(int irq)
  512. {
  513. static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
  514. unsigned long flags;
  515. int vector;
  516. BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
  517. spin_lock_irqsave(&vector_lock, flags);
  518. if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
  519. spin_unlock_irqrestore(&vector_lock, flags);
  520. return IO_APIC_VECTOR(irq);
  521. }
  522. next:
  523. current_vector += 8;
  524. if (current_vector == IA32_SYSCALL_VECTOR)
  525. goto next;
  526. if (current_vector >= FIRST_SYSTEM_VECTOR) {
  527. /* If we run out of vectors on large boxen, must share them. */
  528. offset = (offset + 1) % 8;
  529. current_vector = FIRST_DEVICE_VECTOR + offset;
  530. }
  531. vector = current_vector;
  532. vector_irq[vector] = irq;
  533. if (irq != AUTO_ASSIGN)
  534. IO_APIC_VECTOR(irq) = vector;
  535. spin_unlock_irqrestore(&vector_lock, flags);
  536. return vector;
  537. }
  538. extern void (*interrupt[NR_IRQS])(void);
  539. static struct hw_interrupt_type ioapic_level_type;
  540. static struct hw_interrupt_type ioapic_edge_type;
  541. #define IOAPIC_AUTO -1
  542. #define IOAPIC_EDGE 0
  543. #define IOAPIC_LEVEL 1
  544. static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
  545. {
  546. unsigned idx;
  547. idx = use_pci_vector() && !platform_legacy_irq(irq) ? vector : irq;
  548. if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
  549. trigger == IOAPIC_LEVEL)
  550. irq_desc[idx].chip = &ioapic_level_type;
  551. else
  552. irq_desc[idx].chip = &ioapic_edge_type;
  553. set_intr_gate(vector, interrupt[idx]);
  554. }
  555. static void __init setup_IO_APIC_irqs(void)
  556. {
  557. struct IO_APIC_route_entry entry;
  558. int apic, pin, idx, irq, first_notcon = 1, vector;
  559. unsigned long flags;
  560. apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
  561. for (apic = 0; apic < nr_ioapics; apic++) {
  562. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  563. /*
  564. * add it to the IO-APIC irq-routing table:
  565. */
  566. memset(&entry,0,sizeof(entry));
  567. entry.delivery_mode = INT_DELIVERY_MODE;
  568. entry.dest_mode = INT_DEST_MODE;
  569. entry.mask = 0; /* enable IRQ */
  570. entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  571. idx = find_irq_entry(apic,pin,mp_INT);
  572. if (idx == -1) {
  573. if (first_notcon) {
  574. apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
  575. first_notcon = 0;
  576. } else
  577. apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
  578. continue;
  579. }
  580. entry.trigger = irq_trigger(idx);
  581. entry.polarity = irq_polarity(idx);
  582. if (irq_trigger(idx)) {
  583. entry.trigger = 1;
  584. entry.mask = 1;
  585. entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  586. }
  587. irq = pin_2_irq(idx, apic, pin);
  588. add_pin_to_irq(irq, apic, pin);
  589. if (!apic && !IO_APIC_IRQ(irq))
  590. continue;
  591. if (IO_APIC_IRQ(irq)) {
  592. vector = assign_irq_vector(irq);
  593. entry.vector = vector;
  594. ioapic_register_intr(irq, vector, IOAPIC_AUTO);
  595. if (!apic && (irq < 16))
  596. disable_8259A_irq(irq);
  597. }
  598. ioapic_write_entry(apic, pin, entry);
  599. spin_lock_irqsave(&ioapic_lock, flags);
  600. set_native_irq_info(irq, TARGET_CPUS);
  601. spin_unlock_irqrestore(&ioapic_lock, flags);
  602. }
  603. }
  604. if (!first_notcon)
  605. apic_printk(APIC_VERBOSE," not connected.\n");
  606. }
  607. /*
  608. * Set up the 8259A-master output pin as broadcast to all
  609. * CPUs.
  610. */
  611. static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
  612. {
  613. struct IO_APIC_route_entry entry;
  614. unsigned long flags;
  615. memset(&entry,0,sizeof(entry));
  616. disable_8259A_irq(0);
  617. /* mask LVT0 */
  618. apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  619. /*
  620. * We use logical delivery to get the timer IRQ
  621. * to the first CPU.
  622. */
  623. entry.dest_mode = INT_DEST_MODE;
  624. entry.mask = 0; /* unmask IRQ now */
  625. entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  626. entry.delivery_mode = INT_DELIVERY_MODE;
  627. entry.polarity = 0;
  628. entry.trigger = 0;
  629. entry.vector = vector;
  630. /*
  631. * The timer IRQ doesn't have to know that behind the
  632. * scene we have a 8259A-master in AEOI mode ...
  633. */
  634. irq_desc[0].chip = &ioapic_edge_type;
  635. /*
  636. * Add it to the IO-APIC irq-routing table:
  637. */
  638. spin_lock_irqsave(&ioapic_lock, flags);
  639. io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
  640. io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
  641. spin_unlock_irqrestore(&ioapic_lock, flags);
  642. enable_8259A_irq(0);
  643. }
  644. void __init UNEXPECTED_IO_APIC(void)
  645. {
  646. }
  647. void __apicdebuginit print_IO_APIC(void)
  648. {
  649. int apic, i;
  650. union IO_APIC_reg_00 reg_00;
  651. union IO_APIC_reg_01 reg_01;
  652. union IO_APIC_reg_02 reg_02;
  653. unsigned long flags;
  654. if (apic_verbosity == APIC_QUIET)
  655. return;
  656. printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  657. for (i = 0; i < nr_ioapics; i++)
  658. printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  659. mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
  660. /*
  661. * We are a bit conservative about what we expect. We have to
  662. * know about every hardware change ASAP.
  663. */
  664. printk(KERN_INFO "testing the IO APIC.......................\n");
  665. for (apic = 0; apic < nr_ioapics; apic++) {
  666. spin_lock_irqsave(&ioapic_lock, flags);
  667. reg_00.raw = io_apic_read(apic, 0);
  668. reg_01.raw = io_apic_read(apic, 1);
  669. if (reg_01.bits.version >= 0x10)
  670. reg_02.raw = io_apic_read(apic, 2);
  671. spin_unlock_irqrestore(&ioapic_lock, flags);
  672. printk("\n");
  673. printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
  674. printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
  675. printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
  676. if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
  677. UNEXPECTED_IO_APIC();
  678. printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
  679. printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
  680. if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
  681. (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
  682. (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
  683. (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
  684. (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
  685. (reg_01.bits.entries != 0x2E) &&
  686. (reg_01.bits.entries != 0x3F) &&
  687. (reg_01.bits.entries != 0x03)
  688. )
  689. UNEXPECTED_IO_APIC();
  690. printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
  691. printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
  692. if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
  693. (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
  694. (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
  695. (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
  696. (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
  697. (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
  698. )
  699. UNEXPECTED_IO_APIC();
  700. if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
  701. UNEXPECTED_IO_APIC();
  702. if (reg_01.bits.version >= 0x10) {
  703. printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  704. printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
  705. if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
  706. UNEXPECTED_IO_APIC();
  707. }
  708. printk(KERN_DEBUG ".... IRQ redirection table:\n");
  709. printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
  710. " Stat Dest Deli Vect: \n");
  711. for (i = 0; i <= reg_01.bits.entries; i++) {
  712. struct IO_APIC_route_entry entry;
  713. entry = ioapic_read_entry(apic, i);
  714. printk(KERN_DEBUG " %02x %03X %02X ",
  715. i,
  716. entry.dest.logical.logical_dest,
  717. entry.dest.physical.physical_dest
  718. );
  719. printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
  720. entry.mask,
  721. entry.trigger,
  722. entry.irr,
  723. entry.polarity,
  724. entry.delivery_status,
  725. entry.dest_mode,
  726. entry.delivery_mode,
  727. entry.vector
  728. );
  729. }
  730. }
  731. if (use_pci_vector())
  732. printk(KERN_INFO "Using vector-based indexing\n");
  733. printk(KERN_DEBUG "IRQ to pin mappings:\n");
  734. for (i = 0; i < NR_IRQS; i++) {
  735. struct irq_pin_list *entry = irq_2_pin + i;
  736. if (entry->pin < 0)
  737. continue;
  738. if (use_pci_vector() && !platform_legacy_irq(i))
  739. printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
  740. else
  741. printk(KERN_DEBUG "IRQ%d ", i);
  742. for (;;) {
  743. printk("-> %d:%d", entry->apic, entry->pin);
  744. if (!entry->next)
  745. break;
  746. entry = irq_2_pin + entry->next;
  747. }
  748. printk("\n");
  749. }
  750. printk(KERN_INFO ".................................... done.\n");
  751. return;
  752. }
  753. #if 0
  754. static __apicdebuginit void print_APIC_bitfield (int base)
  755. {
  756. unsigned int v;
  757. int i, j;
  758. if (apic_verbosity == APIC_QUIET)
  759. return;
  760. printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
  761. for (i = 0; i < 8; i++) {
  762. v = apic_read(base + i*0x10);
  763. for (j = 0; j < 32; j++) {
  764. if (v & (1<<j))
  765. printk("1");
  766. else
  767. printk("0");
  768. }
  769. printk("\n");
  770. }
  771. }
  772. void __apicdebuginit print_local_APIC(void * dummy)
  773. {
  774. unsigned int v, ver, maxlvt;
  775. if (apic_verbosity == APIC_QUIET)
  776. return;
  777. printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
  778. smp_processor_id(), hard_smp_processor_id());
  779. v = apic_read(APIC_ID);
  780. printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
  781. v = apic_read(APIC_LVR);
  782. printk(KERN_INFO "... APIC VERSION: %08x\n", v);
  783. ver = GET_APIC_VERSION(v);
  784. maxlvt = get_maxlvt();
  785. v = apic_read(APIC_TASKPRI);
  786. printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
  787. v = apic_read(APIC_ARBPRI);
  788. printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
  789. v & APIC_ARBPRI_MASK);
  790. v = apic_read(APIC_PROCPRI);
  791. printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
  792. v = apic_read(APIC_EOI);
  793. printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
  794. v = apic_read(APIC_RRR);
  795. printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
  796. v = apic_read(APIC_LDR);
  797. printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
  798. v = apic_read(APIC_DFR);
  799. printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
  800. v = apic_read(APIC_SPIV);
  801. printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
  802. printk(KERN_DEBUG "... APIC ISR field:\n");
  803. print_APIC_bitfield(APIC_ISR);
  804. printk(KERN_DEBUG "... APIC TMR field:\n");
  805. print_APIC_bitfield(APIC_TMR);
  806. printk(KERN_DEBUG "... APIC IRR field:\n");
  807. print_APIC_bitfield(APIC_IRR);
  808. v = apic_read(APIC_ESR);
  809. printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
  810. v = apic_read(APIC_ICR);
  811. printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
  812. v = apic_read(APIC_ICR2);
  813. printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
  814. v = apic_read(APIC_LVTT);
  815. printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
  816. if (maxlvt > 3) { /* PC is LVT#4. */
  817. v = apic_read(APIC_LVTPC);
  818. printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
  819. }
  820. v = apic_read(APIC_LVT0);
  821. printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
  822. v = apic_read(APIC_LVT1);
  823. printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
  824. if (maxlvt > 2) { /* ERR is LVT#3. */
  825. v = apic_read(APIC_LVTERR);
  826. printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
  827. }
  828. v = apic_read(APIC_TMICT);
  829. printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
  830. v = apic_read(APIC_TMCCT);
  831. printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
  832. v = apic_read(APIC_TDCR);
  833. printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
  834. printk("\n");
  835. }
  836. void print_all_local_APICs (void)
  837. {
  838. on_each_cpu(print_local_APIC, NULL, 1, 1);
  839. }
  840. void __apicdebuginit print_PIC(void)
  841. {
  842. unsigned int v;
  843. unsigned long flags;
  844. if (apic_verbosity == APIC_QUIET)
  845. return;
  846. printk(KERN_DEBUG "\nprinting PIC contents\n");
  847. spin_lock_irqsave(&i8259A_lock, flags);
  848. v = inb(0xa1) << 8 | inb(0x21);
  849. printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
  850. v = inb(0xa0) << 8 | inb(0x20);
  851. printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
  852. outb(0x0b,0xa0);
  853. outb(0x0b,0x20);
  854. v = inb(0xa0) << 8 | inb(0x20);
  855. outb(0x0a,0xa0);
  856. outb(0x0a,0x20);
  857. spin_unlock_irqrestore(&i8259A_lock, flags);
  858. printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
  859. v = inb(0x4d1) << 8 | inb(0x4d0);
  860. printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
  861. }
  862. #endif /* 0 */
  863. static void __init enable_IO_APIC(void)
  864. {
  865. union IO_APIC_reg_01 reg_01;
  866. int i8259_apic, i8259_pin;
  867. int i, apic;
  868. unsigned long flags;
  869. for (i = 0; i < PIN_MAP_SIZE; i++) {
  870. irq_2_pin[i].pin = -1;
  871. irq_2_pin[i].next = 0;
  872. }
  873. /*
  874. * The number of IO-APIC IRQ registers (== #pins):
  875. */
  876. for (apic = 0; apic < nr_ioapics; apic++) {
  877. spin_lock_irqsave(&ioapic_lock, flags);
  878. reg_01.raw = io_apic_read(apic, 1);
  879. spin_unlock_irqrestore(&ioapic_lock, flags);
  880. nr_ioapic_registers[apic] = reg_01.bits.entries+1;
  881. }
  882. for(apic = 0; apic < nr_ioapics; apic++) {
  883. int pin;
  884. /* See if any of the pins is in ExtINT mode */
  885. for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
  886. struct IO_APIC_route_entry entry;
  887. entry = ioapic_read_entry(apic, pin);
  888. /* If the interrupt line is enabled and in ExtInt mode
  889. * I have found the pin where the i8259 is connected.
  890. */
  891. if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
  892. ioapic_i8259.apic = apic;
  893. ioapic_i8259.pin = pin;
  894. goto found_i8259;
  895. }
  896. }
  897. }
  898. found_i8259:
  899. /* Look to see what if the MP table has reported the ExtINT */
  900. i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
  901. i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
  902. /* Trust the MP table if nothing is setup in the hardware */
  903. if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
  904. printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
  905. ioapic_i8259.pin = i8259_pin;
  906. ioapic_i8259.apic = i8259_apic;
  907. }
  908. /* Complain if the MP table and the hardware disagree */
  909. if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
  910. (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
  911. {
  912. printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
  913. }
  914. /*
  915. * Do not trust the IO-APIC being empty at bootup
  916. */
  917. clear_IO_APIC();
  918. }
  919. /*
  920. * Not an __init, needed by the reboot code
  921. */
  922. void disable_IO_APIC(void)
  923. {
  924. /*
  925. * Clear the IO-APIC before rebooting:
  926. */
  927. clear_IO_APIC();
  928. /*
  929. * If the i8259 is routed through an IOAPIC
  930. * Put that IOAPIC in virtual wire mode
  931. * so legacy interrupts can be delivered.
  932. */
  933. if (ioapic_i8259.pin != -1) {
  934. struct IO_APIC_route_entry entry;
  935. memset(&entry, 0, sizeof(entry));
  936. entry.mask = 0; /* Enabled */
  937. entry.trigger = 0; /* Edge */
  938. entry.irr = 0;
  939. entry.polarity = 0; /* High */
  940. entry.delivery_status = 0;
  941. entry.dest_mode = 0; /* Physical */
  942. entry.delivery_mode = dest_ExtINT; /* ExtInt */
  943. entry.vector = 0;
  944. entry.dest.physical.physical_dest =
  945. GET_APIC_ID(apic_read(APIC_ID));
  946. /*
  947. * Add it to the IO-APIC irq-routing table:
  948. */
  949. ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
  950. }
  951. disconnect_bsp_APIC(ioapic_i8259.pin != -1);
  952. }
  953. /*
  954. * There is a nasty bug in some older SMP boards, their mptable lies
  955. * about the timer IRQ. We do the following to work around the situation:
  956. *
  957. * - timer IRQ defaults to IO-APIC IRQ
  958. * - if this function detects that timer IRQs are defunct, then we fall
  959. * back to ISA timer IRQs
  960. */
  961. static int __init timer_irq_works(void)
  962. {
  963. unsigned long t1 = jiffies;
  964. local_irq_enable();
  965. /* Let ten ticks pass... */
  966. mdelay((10 * 1000) / HZ);
  967. /*
  968. * Expect a few ticks at least, to be sure some possible
  969. * glue logic does not lock up after one or two first
  970. * ticks in a non-ExtINT mode. Also the local APIC
  971. * might have cached one ExtINT interrupt. Finally, at
  972. * least one tick may be lost due to delays.
  973. */
  974. /* jiffies wrap? */
  975. if (jiffies - t1 > 4)
  976. return 1;
  977. return 0;
  978. }
  979. /*
  980. * In the SMP+IOAPIC case it might happen that there are an unspecified
  981. * number of pending IRQ events unhandled. These cases are very rare,
  982. * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
  983. * better to do it this way as thus we do not have to be aware of
  984. * 'pending' interrupts in the IRQ path, except at this point.
  985. */
  986. /*
  987. * Edge triggered needs to resend any interrupt
  988. * that was delayed but this is now handled in the device
  989. * independent code.
  990. */
  991. /*
  992. * Starting up a edge-triggered IO-APIC interrupt is
  993. * nasty - we need to make sure that we get the edge.
  994. * If it is already asserted for some reason, we need
  995. * return 1 to indicate that is was pending.
  996. *
  997. * This is not complete - we should be able to fake
  998. * an edge even if it isn't on the 8259A...
  999. */
  1000. static unsigned int startup_edge_ioapic_irq(unsigned int irq)
  1001. {
  1002. int was_pending = 0;
  1003. unsigned long flags;
  1004. spin_lock_irqsave(&ioapic_lock, flags);
  1005. if (irq < 16) {
  1006. disable_8259A_irq(irq);
  1007. if (i8259A_irq_pending(irq))
  1008. was_pending = 1;
  1009. }
  1010. __unmask_IO_APIC_irq(irq);
  1011. spin_unlock_irqrestore(&ioapic_lock, flags);
  1012. return was_pending;
  1013. }
  1014. /*
  1015. * Once we have recorded IRQ_PENDING already, we can mask the
  1016. * interrupt for real. This prevents IRQ storms from unhandled
  1017. * devices.
  1018. */
  1019. static void ack_edge_ioapic_irq(unsigned int irq)
  1020. {
  1021. move_irq(irq);
  1022. if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
  1023. == (IRQ_PENDING | IRQ_DISABLED))
  1024. mask_IO_APIC_irq(irq);
  1025. ack_APIC_irq();
  1026. }
  1027. /*
  1028. * Level triggered interrupts can just be masked,
  1029. * and shutting down and starting up the interrupt
  1030. * is the same as enabling and disabling them -- except
  1031. * with a startup need to return a "was pending" value.
  1032. *
  1033. * Level triggered interrupts are special because we
  1034. * do not touch any IO-APIC register while handling
  1035. * them. We ack the APIC in the end-IRQ handler, not
  1036. * in the start-IRQ-handler. Protection against reentrance
  1037. * from the same interrupt is still provided, both by the
  1038. * generic IRQ layer and by the fact that an unacked local
  1039. * APIC does not accept IRQs.
  1040. */
  1041. static unsigned int startup_level_ioapic_irq (unsigned int irq)
  1042. {
  1043. unmask_IO_APIC_irq(irq);
  1044. return 0; /* don't check for pending */
  1045. }
  1046. static void end_level_ioapic_irq (unsigned int irq)
  1047. {
  1048. move_irq(irq);
  1049. ack_APIC_irq();
  1050. }
  1051. #ifdef CONFIG_PCI_MSI
  1052. static unsigned int startup_edge_ioapic_vector(unsigned int vector)
  1053. {
  1054. int irq = vector_to_irq(vector);
  1055. return startup_edge_ioapic_irq(irq);
  1056. }
  1057. static void ack_edge_ioapic_vector(unsigned int vector)
  1058. {
  1059. int irq = vector_to_irq(vector);
  1060. move_native_irq(vector);
  1061. ack_edge_ioapic_irq(irq);
  1062. }
  1063. static unsigned int startup_level_ioapic_vector (unsigned int vector)
  1064. {
  1065. int irq = vector_to_irq(vector);
  1066. return startup_level_ioapic_irq (irq);
  1067. }
  1068. static void end_level_ioapic_vector (unsigned int vector)
  1069. {
  1070. int irq = vector_to_irq(vector);
  1071. move_native_irq(vector);
  1072. end_level_ioapic_irq(irq);
  1073. }
  1074. static void mask_IO_APIC_vector (unsigned int vector)
  1075. {
  1076. int irq = vector_to_irq(vector);
  1077. mask_IO_APIC_irq(irq);
  1078. }
  1079. static void unmask_IO_APIC_vector (unsigned int vector)
  1080. {
  1081. int irq = vector_to_irq(vector);
  1082. unmask_IO_APIC_irq(irq);
  1083. }
  1084. #ifdef CONFIG_SMP
  1085. static void set_ioapic_affinity_vector (unsigned int vector,
  1086. cpumask_t cpu_mask)
  1087. {
  1088. int irq = vector_to_irq(vector);
  1089. set_native_irq_info(vector, cpu_mask);
  1090. set_ioapic_affinity_irq(irq, cpu_mask);
  1091. }
  1092. #endif // CONFIG_SMP
  1093. #endif // CONFIG_PCI_MSI
  1094. static int ioapic_retrigger(unsigned int irq)
  1095. {
  1096. send_IPI_self(IO_APIC_VECTOR(irq));
  1097. return 1;
  1098. }
  1099. /*
  1100. * Level and edge triggered IO-APIC interrupts need different handling,
  1101. * so we use two separate IRQ descriptors. Edge triggered IRQs can be
  1102. * handled with the level-triggered descriptor, but that one has slightly
  1103. * more overhead. Level-triggered interrupts cannot be handled with the
  1104. * edge-triggered handler, without risking IRQ storms and other ugly
  1105. * races.
  1106. */
  1107. static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
  1108. .typename = "IO-APIC-edge",
  1109. .startup = startup_edge_ioapic,
  1110. .shutdown = shutdown_edge_ioapic,
  1111. .enable = enable_edge_ioapic,
  1112. .disable = disable_edge_ioapic,
  1113. .ack = ack_edge_ioapic,
  1114. .end = end_edge_ioapic,
  1115. #ifdef CONFIG_SMP
  1116. .set_affinity = set_ioapic_affinity,
  1117. #endif
  1118. .retrigger = ioapic_retrigger,
  1119. };
  1120. static struct hw_interrupt_type ioapic_level_type __read_mostly = {
  1121. .typename = "IO-APIC-level",
  1122. .startup = startup_level_ioapic,
  1123. .shutdown = shutdown_level_ioapic,
  1124. .enable = enable_level_ioapic,
  1125. .disable = disable_level_ioapic,
  1126. .ack = mask_and_ack_level_ioapic,
  1127. .end = end_level_ioapic,
  1128. #ifdef CONFIG_SMP
  1129. .set_affinity = set_ioapic_affinity,
  1130. #endif
  1131. .retrigger = ioapic_retrigger,
  1132. };
  1133. static inline void init_IO_APIC_traps(void)
  1134. {
  1135. int irq;
  1136. /*
  1137. * NOTE! The local APIC isn't very good at handling
  1138. * multiple interrupts at the same interrupt level.
  1139. * As the interrupt level is determined by taking the
  1140. * vector number and shifting that right by 4, we
  1141. * want to spread these out a bit so that they don't
  1142. * all fall in the same interrupt level.
  1143. *
  1144. * Also, we've got to be careful not to trash gate
  1145. * 0x80, because int 0x80 is hm, kind of importantish. ;)
  1146. */
  1147. for (irq = 0; irq < NR_IRQS ; irq++) {
  1148. int tmp = irq;
  1149. if (use_pci_vector()) {
  1150. if (!platform_legacy_irq(tmp))
  1151. if ((tmp = vector_to_irq(tmp)) == -1)
  1152. continue;
  1153. }
  1154. if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
  1155. /*
  1156. * Hmm.. We don't have an entry for this,
  1157. * so default to an old-fashioned 8259
  1158. * interrupt if we can..
  1159. */
  1160. if (irq < 16)
  1161. make_8259A_irq(irq);
  1162. else
  1163. /* Strange. Oh, well.. */
  1164. irq_desc[irq].chip = &no_irq_type;
  1165. }
  1166. }
  1167. }
  1168. static void enable_lapic_irq (unsigned int irq)
  1169. {
  1170. unsigned long v;
  1171. v = apic_read(APIC_LVT0);
  1172. apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
  1173. }
  1174. static void disable_lapic_irq (unsigned int irq)
  1175. {
  1176. unsigned long v;
  1177. v = apic_read(APIC_LVT0);
  1178. apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
  1179. }
  1180. static void ack_lapic_irq (unsigned int irq)
  1181. {
  1182. ack_APIC_irq();
  1183. }
  1184. static void end_lapic_irq (unsigned int i) { /* nothing */ }
  1185. static struct hw_interrupt_type lapic_irq_type __read_mostly = {
  1186. .typename = "local-APIC-edge",
  1187. .startup = NULL, /* startup_irq() not used for IRQ0 */
  1188. .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
  1189. .enable = enable_lapic_irq,
  1190. .disable = disable_lapic_irq,
  1191. .ack = ack_lapic_irq,
  1192. .end = end_lapic_irq,
  1193. };
  1194. static void setup_nmi (void)
  1195. {
  1196. /*
  1197. * Dirty trick to enable the NMI watchdog ...
  1198. * We put the 8259A master into AEOI mode and
  1199. * unmask on all local APICs LVT0 as NMI.
  1200. *
  1201. * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
  1202. * is from Maciej W. Rozycki - so we do not have to EOI from
  1203. * the NMI handler or the timer interrupt.
  1204. */
  1205. printk(KERN_INFO "activating NMI Watchdog ...");
  1206. enable_NMI_through_LVT0(NULL);
  1207. printk(" done.\n");
  1208. }
  1209. /*
  1210. * This looks a bit hackish but it's about the only one way of sending
  1211. * a few INTA cycles to 8259As and any associated glue logic. ICR does
  1212. * not support the ExtINT mode, unfortunately. We need to send these
  1213. * cycles as some i82489DX-based boards have glue logic that keeps the
  1214. * 8259A interrupt line asserted until INTA. --macro
  1215. */
  1216. static inline void unlock_ExtINT_logic(void)
  1217. {
  1218. int apic, pin, i;
  1219. struct IO_APIC_route_entry entry0, entry1;
  1220. unsigned char save_control, save_freq_select;
  1221. unsigned long flags;
  1222. pin = find_isa_irq_pin(8, mp_INT);
  1223. apic = find_isa_irq_apic(8, mp_INT);
  1224. if (pin == -1)
  1225. return;
  1226. spin_lock_irqsave(&ioapic_lock, flags);
  1227. *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
  1228. *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
  1229. spin_unlock_irqrestore(&ioapic_lock, flags);
  1230. clear_IO_APIC_pin(apic, pin);
  1231. memset(&entry1, 0, sizeof(entry1));
  1232. entry1.dest_mode = 0; /* physical delivery */
  1233. entry1.mask = 0; /* unmask IRQ now */
  1234. entry1.dest.physical.physical_dest = hard_smp_processor_id();
  1235. entry1.delivery_mode = dest_ExtINT;
  1236. entry1.polarity = entry0.polarity;
  1237. entry1.trigger = 0;
  1238. entry1.vector = 0;
  1239. spin_lock_irqsave(&ioapic_lock, flags);
  1240. io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
  1241. io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
  1242. spin_unlock_irqrestore(&ioapic_lock, flags);
  1243. save_control = CMOS_READ(RTC_CONTROL);
  1244. save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
  1245. CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
  1246. RTC_FREQ_SELECT);
  1247. CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
  1248. i = 100;
  1249. while (i-- > 0) {
  1250. mdelay(10);
  1251. if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
  1252. i -= 10;
  1253. }
  1254. CMOS_WRITE(save_control, RTC_CONTROL);
  1255. CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
  1256. clear_IO_APIC_pin(apic, pin);
  1257. spin_lock_irqsave(&ioapic_lock, flags);
  1258. io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
  1259. io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
  1260. spin_unlock_irqrestore(&ioapic_lock, flags);
  1261. }
  1262. int timer_uses_ioapic_pin_0;
  1263. /*
  1264. * This code may look a bit paranoid, but it's supposed to cooperate with
  1265. * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
  1266. * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
  1267. * fanatically on his truly buggy board.
  1268. *
  1269. * FIXME: really need to revamp this for modern platforms only.
  1270. */
  1271. static inline void check_timer(void)
  1272. {
  1273. int apic1, pin1, apic2, pin2;
  1274. int vector;
  1275. /*
  1276. * get/set the timer IRQ vector:
  1277. */
  1278. disable_8259A_irq(0);
  1279. vector = assign_irq_vector(0);
  1280. set_intr_gate(vector, interrupt[0]);
  1281. /*
  1282. * Subtle, code in do_timer_interrupt() expects an AEOI
  1283. * mode for the 8259A whenever interrupts are routed
  1284. * through I/O APICs. Also IRQ0 has to be enabled in
  1285. * the 8259A which implies the virtual wire has to be
  1286. * disabled in the local APIC.
  1287. */
  1288. apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
  1289. init_8259A(1);
  1290. if (timer_over_8254 > 0)
  1291. enable_8259A_irq(0);
  1292. pin1 = find_isa_irq_pin(0, mp_INT);
  1293. apic1 = find_isa_irq_apic(0, mp_INT);
  1294. pin2 = ioapic_i8259.pin;
  1295. apic2 = ioapic_i8259.apic;
  1296. if (pin1 == 0)
  1297. timer_uses_ioapic_pin_0 = 1;
  1298. apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
  1299. vector, apic1, pin1, apic2, pin2);
  1300. if (pin1 != -1) {
  1301. /*
  1302. * Ok, does IRQ0 through the IOAPIC work?
  1303. */
  1304. unmask_IO_APIC_irq(0);
  1305. if (!no_timer_check && timer_irq_works()) {
  1306. nmi_watchdog_default();
  1307. if (nmi_watchdog == NMI_IO_APIC) {
  1308. disable_8259A_irq(0);
  1309. setup_nmi();
  1310. enable_8259A_irq(0);
  1311. }
  1312. if (disable_timer_pin_1 > 0)
  1313. clear_IO_APIC_pin(0, pin1);
  1314. return;
  1315. }
  1316. clear_IO_APIC_pin(apic1, pin1);
  1317. apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
  1318. "connected to IO-APIC\n");
  1319. }
  1320. apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
  1321. "through the 8259A ... ");
  1322. if (pin2 != -1) {
  1323. apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
  1324. apic2, pin2);
  1325. /*
  1326. * legacy devices should be connected to IO APIC #0
  1327. */
  1328. setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
  1329. if (timer_irq_works()) {
  1330. apic_printk(APIC_VERBOSE," works.\n");
  1331. nmi_watchdog_default();
  1332. if (nmi_watchdog == NMI_IO_APIC) {
  1333. setup_nmi();
  1334. }
  1335. return;
  1336. }
  1337. /*
  1338. * Cleanup, just in case ...
  1339. */
  1340. clear_IO_APIC_pin(apic2, pin2);
  1341. }
  1342. apic_printk(APIC_VERBOSE," failed.\n");
  1343. if (nmi_watchdog == NMI_IO_APIC) {
  1344. printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
  1345. nmi_watchdog = 0;
  1346. }
  1347. apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
  1348. disable_8259A_irq(0);
  1349. irq_desc[0].chip = &lapic_irq_type;
  1350. apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
  1351. enable_8259A_irq(0);
  1352. if (timer_irq_works()) {
  1353. apic_printk(APIC_VERBOSE," works.\n");
  1354. return;
  1355. }
  1356. apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
  1357. apic_printk(APIC_VERBOSE," failed.\n");
  1358. apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
  1359. init_8259A(0);
  1360. make_8259A_irq(0);
  1361. apic_write(APIC_LVT0, APIC_DM_EXTINT);
  1362. unlock_ExtINT_logic();
  1363. if (timer_irq_works()) {
  1364. apic_printk(APIC_VERBOSE," works.\n");
  1365. return;
  1366. }
  1367. apic_printk(APIC_VERBOSE," failed :(.\n");
  1368. panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
  1369. }
  1370. static int __init notimercheck(char *s)
  1371. {
  1372. no_timer_check = 1;
  1373. return 1;
  1374. }
  1375. __setup("no_timer_check", notimercheck);
  1376. /*
  1377. *
  1378. * IRQ's that are handled by the PIC in the MPS IOAPIC case.
  1379. * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
  1380. * Linux doesn't really care, as it's not actually used
  1381. * for any interrupt handling anyway.
  1382. */
  1383. #define PIC_IRQS (1<<2)
  1384. void __init setup_IO_APIC(void)
  1385. {
  1386. enable_IO_APIC();
  1387. if (acpi_ioapic)
  1388. io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
  1389. else
  1390. io_apic_irqs = ~PIC_IRQS;
  1391. apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
  1392. sync_Arb_IDs();
  1393. setup_IO_APIC_irqs();
  1394. init_IO_APIC_traps();
  1395. check_timer();
  1396. if (!acpi_ioapic)
  1397. print_IO_APIC();
  1398. }
  1399. struct sysfs_ioapic_data {
  1400. struct sys_device dev;
  1401. struct IO_APIC_route_entry entry[0];
  1402. };
  1403. static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
  1404. static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
  1405. {
  1406. struct IO_APIC_route_entry *entry;
  1407. struct sysfs_ioapic_data *data;
  1408. int i;
  1409. data = container_of(dev, struct sysfs_ioapic_data, dev);
  1410. entry = data->entry;
  1411. for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
  1412. *entry = ioapic_read_entry(dev->id, i);
  1413. return 0;
  1414. }
  1415. static int ioapic_resume(struct sys_device *dev)
  1416. {
  1417. struct IO_APIC_route_entry *entry;
  1418. struct sysfs_ioapic_data *data;
  1419. unsigned long flags;
  1420. union IO_APIC_reg_00 reg_00;
  1421. int i;
  1422. data = container_of(dev, struct sysfs_ioapic_data, dev);
  1423. entry = data->entry;
  1424. spin_lock_irqsave(&ioapic_lock, flags);
  1425. reg_00.raw = io_apic_read(dev->id, 0);
  1426. if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
  1427. reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
  1428. io_apic_write(dev->id, 0, reg_00.raw);
  1429. }
  1430. spin_unlock_irqrestore(&ioapic_lock, flags);
  1431. for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
  1432. ioapic_write_entry(dev->id, i, entry[i]);
  1433. return 0;
  1434. }
  1435. static struct sysdev_class ioapic_sysdev_class = {
  1436. set_kset_name("ioapic"),
  1437. .suspend = ioapic_suspend,
  1438. .resume = ioapic_resume,
  1439. };
  1440. static int __init ioapic_init_sysfs(void)
  1441. {
  1442. struct sys_device * dev;
  1443. int i, size, error = 0;
  1444. error = sysdev_class_register(&ioapic_sysdev_class);
  1445. if (error)
  1446. return error;
  1447. for (i = 0; i < nr_ioapics; i++ ) {
  1448. size = sizeof(struct sys_device) + nr_ioapic_registers[i]
  1449. * sizeof(struct IO_APIC_route_entry);
  1450. mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
  1451. if (!mp_ioapic_data[i]) {
  1452. printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  1453. continue;
  1454. }
  1455. memset(mp_ioapic_data[i], 0, size);
  1456. dev = &mp_ioapic_data[i]->dev;
  1457. dev->id = i;
  1458. dev->cls = &ioapic_sysdev_class;
  1459. error = sysdev_register(dev);
  1460. if (error) {
  1461. kfree(mp_ioapic_data[i]);
  1462. mp_ioapic_data[i] = NULL;
  1463. printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
  1464. continue;
  1465. }
  1466. }
  1467. return 0;
  1468. }
  1469. device_initcall(ioapic_init_sysfs);
  1470. /* --------------------------------------------------------------------------
  1471. ACPI-based IOAPIC Configuration
  1472. -------------------------------------------------------------------------- */
  1473. #ifdef CONFIG_ACPI
  1474. #define IO_APIC_MAX_ID 0xFE
  1475. int __init io_apic_get_redir_entries (int ioapic)
  1476. {
  1477. union IO_APIC_reg_01 reg_01;
  1478. unsigned long flags;
  1479. spin_lock_irqsave(&ioapic_lock, flags);
  1480. reg_01.raw = io_apic_read(ioapic, 1);
  1481. spin_unlock_irqrestore(&ioapic_lock, flags);
  1482. return reg_01.bits.entries;
  1483. }
  1484. int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
  1485. {
  1486. struct IO_APIC_route_entry entry;
  1487. unsigned long flags;
  1488. if (!IO_APIC_IRQ(irq)) {
  1489. apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
  1490. ioapic);
  1491. return -EINVAL;
  1492. }
  1493. /*
  1494. * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
  1495. * Note that we mask (disable) IRQs now -- these get enabled when the
  1496. * corresponding device driver registers for this IRQ.
  1497. */
  1498. memset(&entry,0,sizeof(entry));
  1499. entry.delivery_mode = INT_DELIVERY_MODE;
  1500. entry.dest_mode = INT_DEST_MODE;
  1501. entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  1502. entry.trigger = triggering;
  1503. entry.polarity = polarity;
  1504. entry.mask = 1; /* Disabled (masked) */
  1505. irq = gsi_irq_sharing(irq);
  1506. /*
  1507. * IRQs < 16 are already in the irq_2_pin[] map
  1508. */
  1509. if (irq >= 16)
  1510. add_pin_to_irq(irq, ioapic, pin);
  1511. entry.vector = assign_irq_vector(irq);
  1512. apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
  1513. "IRQ %d Mode:%i Active:%i)\n", ioapic,
  1514. mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
  1515. triggering, polarity);
  1516. ioapic_register_intr(irq, entry.vector, triggering);
  1517. if (!ioapic && (irq < 16))
  1518. disable_8259A_irq(irq);
  1519. ioapic_write_entry(ioapic, pin, entry);
  1520. spin_lock_irqsave(&ioapic_lock, flags);
  1521. set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
  1522. spin_unlock_irqrestore(&ioapic_lock, flags);
  1523. return 0;
  1524. }
  1525. #endif /* CONFIG_ACPI */
  1526. /*
  1527. * This function currently is only a helper for the i386 smp boot process where
  1528. * we need to reprogram the ioredtbls to cater for the cpus which have come online
  1529. * so mask in all cases should simply be TARGET_CPUS
  1530. */
  1531. #ifdef CONFIG_SMP
  1532. void __init setup_ioapic_dest(void)
  1533. {
  1534. int pin, ioapic, irq, irq_entry;
  1535. if (skip_ioapic_setup == 1)
  1536. return;
  1537. for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
  1538. for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
  1539. irq_entry = find_irq_entry(ioapic, pin, mp_INT);
  1540. if (irq_entry == -1)
  1541. continue;
  1542. irq = pin_2_irq(irq_entry, ioapic, pin);
  1543. set_ioapic_affinity_irq(irq, TARGET_CPUS);
  1544. }
  1545. }
  1546. }
  1547. #endif