malta_setup.c 6.1 KB

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  1. /*
  2. * Carsten Langgaard, carstenl@mips.com
  3. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  4. *
  5. * This program is free software; you can distribute it and/or modify it
  6. * under the terms of the GNU General Public License (Version 2) as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along
  15. * with this program; if not, write to the Free Software Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/sched.h>
  20. #include <linux/ioport.h>
  21. #include <linux/pci.h>
  22. #include <linux/screen_info.h>
  23. #ifdef CONFIG_MTD
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/map.h>
  28. #endif
  29. #include <asm/cpu.h>
  30. #include <asm/bootinfo.h>
  31. #include <asm/irq.h>
  32. #include <asm/mips-boards/generic.h>
  33. #include <asm/mips-boards/prom.h>
  34. #include <asm/mips-boards/malta.h>
  35. #include <asm/mips-boards/maltaint.h>
  36. #include <asm/dma.h>
  37. #include <asm/time.h>
  38. #include <asm/traps.h>
  39. #ifdef CONFIG_VT
  40. #include <linux/console.h>
  41. #endif
  42. extern void mips_reboot_setup(void);
  43. extern void mips_time_init(void);
  44. extern unsigned long mips_rtc_get_time(void);
  45. #ifdef CONFIG_KGDB
  46. extern void kgdb_config(void);
  47. #endif
  48. struct resource standard_io_resources[] = {
  49. { .name = "dma1", .start = 0x00, .end = 0x1f, .flags = IORESOURCE_BUSY },
  50. { .name = "timer", .start = 0x40, .end = 0x5f, .flags = IORESOURCE_BUSY },
  51. { .name = "keyboard", .start = 0x60, .end = 0x6f, .flags = IORESOURCE_BUSY },
  52. { .name = "dma page reg", .start = 0x80, .end = 0x8f, .flags = IORESOURCE_BUSY },
  53. { .name = "dma2", .start = 0xc0, .end = 0xdf, .flags = IORESOURCE_BUSY },
  54. };
  55. #ifdef CONFIG_MTD
  56. static struct mtd_partition malta_mtd_partitions[] = {
  57. {
  58. .name = "YAMON",
  59. .offset = 0x0,
  60. .size = 0x100000,
  61. .mask_flags = MTD_WRITEABLE
  62. },
  63. {
  64. .name = "User FS",
  65. .offset = 0x100000,
  66. .size = 0x2e0000
  67. },
  68. {
  69. .name = "Board Config",
  70. .offset = 0x3e0000,
  71. .size = 0x020000,
  72. .mask_flags = MTD_WRITEABLE
  73. }
  74. };
  75. #define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
  76. #endif
  77. const char *get_system_type(void)
  78. {
  79. return "MIPS Malta";
  80. }
  81. #ifdef CONFIG_BLK_DEV_FD
  82. void __init fd_activate(void)
  83. {
  84. /*
  85. * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
  86. * Controller.
  87. * Done by YAMON 2.00 onwards
  88. */
  89. /* Entering config state. */
  90. SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
  91. /* Activate floppy controller. */
  92. SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
  93. SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
  94. SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
  95. SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
  96. /* Exit config state. */
  97. SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
  98. }
  99. #endif
  100. void __init plat_mem_setup(void)
  101. {
  102. unsigned int i;
  103. mips_pcibios_init();
  104. /* Request I/O space for devices used on the Malta board. */
  105. for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
  106. request_resource(&ioport_resource, standard_io_resources+i);
  107. /*
  108. * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
  109. */
  110. enable_dma(4);
  111. #ifdef CONFIG_KGDB
  112. kgdb_config ();
  113. #endif
  114. if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
  115. (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
  116. (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
  117. char *argptr;
  118. argptr = prom_getcmdline();
  119. if (strstr(argptr, "debug")) {
  120. BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
  121. printk ("Enabled Bonito debug mode\n");
  122. }
  123. else
  124. BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
  125. #ifdef CONFIG_DMA_COHERENT
  126. if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
  127. BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
  128. printk("Enabled Bonito CPU coherency\n");
  129. argptr = prom_getcmdline();
  130. if (strstr(argptr, "iobcuncached")) {
  131. BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
  132. BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
  133. ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
  134. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
  135. printk("Disabled Bonito IOBC coherency\n");
  136. }
  137. else {
  138. BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
  139. BONITO_PCIMEMBASECFG |=
  140. (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
  141. BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
  142. printk("Disabled Bonito IOBC coherency\n");
  143. }
  144. }
  145. else
  146. panic("Hardware DMA cache coherency not supported");
  147. #endif
  148. }
  149. #ifdef CONFIG_DMA_COHERENT
  150. else {
  151. panic("Hardware DMA cache coherency not supported");
  152. }
  153. #endif
  154. #ifdef CONFIG_BLK_DEV_IDE
  155. /* Check PCI clock */
  156. {
  157. int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
  158. static const int pciclocks[] __initdata = {
  159. 33, 20, 25, 30, 12, 16, 37, 10
  160. };
  161. int pciclock = pciclocks[jmpr];
  162. char *argptr = prom_getcmdline();
  163. if (pciclock != 33 && !strstr (argptr, "idebus=")) {
  164. printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
  165. argptr += strlen(argptr);
  166. sprintf (argptr, " idebus=%d", pciclock);
  167. if (pciclock < 20 || pciclock > 66)
  168. printk ("WARNING: IDE timing calculations will be incorrect\n");
  169. }
  170. }
  171. #endif
  172. #ifdef CONFIG_BLK_DEV_FD
  173. fd_activate ();
  174. #endif
  175. #ifdef CONFIG_VT
  176. #if defined(CONFIG_VGA_CONSOLE)
  177. screen_info = (struct screen_info) {
  178. 0, 25, /* orig-x, orig-y */
  179. 0, /* unused */
  180. 0, /* orig-video-page */
  181. 0, /* orig-video-mode */
  182. 80, /* orig-video-cols */
  183. 0,0,0, /* ega_ax, ega_bx, ega_cx */
  184. 25, /* orig-video-lines */
  185. VIDEO_TYPE_VGAC, /* orig-video-isVGA */
  186. 16 /* orig-video-points */
  187. };
  188. #endif
  189. #endif
  190. #ifdef CONFIG_MTD
  191. /*
  192. * Support for MTD on Malta. Use the generic physmap driver
  193. */
  194. physmap_configure(0x1e000000, 0x400000, 4, NULL);
  195. physmap_set_partitions(malta_mtd_partitions, number_partitions);
  196. #endif
  197. mips_reboot_setup();
  198. board_time_init = mips_time_init;
  199. rtc_mips_get_time = mips_rtc_get_time;
  200. }