twl4030.c 69 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283
  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. 0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
  116. };
  117. /* codec private data */
  118. struct twl4030_priv {
  119. unsigned int bypass_state;
  120. unsigned int codec_powered;
  121. unsigned int codec_muted;
  122. struct snd_pcm_substream *master_substream;
  123. struct snd_pcm_substream *slave_substream;
  124. unsigned int configured;
  125. unsigned int rate;
  126. unsigned int sample_bits;
  127. unsigned int channels;
  128. unsigned int sysclk;
  129. /* Headset output state handling */
  130. unsigned int hsl_enabled;
  131. unsigned int hsr_enabled;
  132. };
  133. /*
  134. * read twl4030 register cache
  135. */
  136. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  137. unsigned int reg)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return -EIO;
  142. return cache[reg];
  143. }
  144. /*
  145. * write twl4030 register cache
  146. */
  147. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  148. u8 reg, u8 value)
  149. {
  150. u8 *cache = codec->reg_cache;
  151. if (reg >= TWL4030_CACHEREGNUM)
  152. return;
  153. cache[reg] = value;
  154. }
  155. /*
  156. * write to the twl4030 register space
  157. */
  158. static int twl4030_write(struct snd_soc_codec *codec,
  159. unsigned int reg, unsigned int value)
  160. {
  161. twl4030_write_reg_cache(codec, reg, value);
  162. if (likely(reg < TWL4030_REG_SW_SHADOW))
  163. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value,
  164. reg);
  165. else
  166. return 0;
  167. }
  168. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  169. {
  170. struct twl4030_priv *twl4030 = codec->private_data;
  171. u8 mode;
  172. if (enable == twl4030->codec_powered)
  173. return;
  174. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  175. if (enable)
  176. mode |= TWL4030_CODECPDZ;
  177. else
  178. mode &= ~TWL4030_CODECPDZ;
  179. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  180. twl4030->codec_powered = enable;
  181. /* REVISIT: this delay is present in TI sample drivers */
  182. /* but there seems to be no TRM requirement for it */
  183. udelay(10);
  184. }
  185. static void twl4030_init_chip(struct snd_soc_codec *codec)
  186. {
  187. u8 *cache = codec->reg_cache;
  188. int i;
  189. /* clear CODECPDZ prior to setting register defaults */
  190. twl4030_codec_enable(codec, 0);
  191. /* set all audio section registers to reasonable defaults */
  192. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  193. twl4030_write(codec, i, cache[i]);
  194. }
  195. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  196. {
  197. struct twl4030_priv *twl4030 = codec->private_data;
  198. u8 reg_val;
  199. if (mute == twl4030->codec_muted)
  200. return;
  201. if (mute) {
  202. /* Disable PLL */
  203. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  204. reg_val &= ~TWL4030_APLL_EN;
  205. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  206. } else {
  207. /* Enable PLL */
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  209. reg_val |= TWL4030_APLL_EN;
  210. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  211. }
  212. twl4030->codec_muted = mute;
  213. }
  214. static void twl4030_power_up(struct snd_soc_codec *codec)
  215. {
  216. struct twl4030_priv *twl4030 = codec->private_data;
  217. u8 anamicl, regmisc1, byte;
  218. int i = 0;
  219. if (twl4030->codec_powered)
  220. return;
  221. /* set CODECPDZ to turn on codec */
  222. twl4030_codec_enable(codec, 1);
  223. /* initiate offset cancellation */
  224. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  225. twl4030_write(codec, TWL4030_REG_ANAMICL,
  226. anamicl | TWL4030_CNCL_OFFSET_START);
  227. /* wait for offset cancellation to complete */
  228. do {
  229. /* this takes a little while, so don't slam i2c */
  230. udelay(2000);
  231. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  232. TWL4030_REG_ANAMICL);
  233. } while ((i++ < 100) &&
  234. ((byte & TWL4030_CNCL_OFFSET_START) ==
  235. TWL4030_CNCL_OFFSET_START));
  236. /* Make sure that the reg_cache has the same value as the HW */
  237. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  238. /* anti-pop when changing analog gain */
  239. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  240. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  241. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  242. /* toggle CODECPDZ as per TRM */
  243. twl4030_codec_enable(codec, 0);
  244. twl4030_codec_enable(codec, 1);
  245. }
  246. /*
  247. * Unconditional power down
  248. */
  249. static void twl4030_power_down(struct snd_soc_codec *codec)
  250. {
  251. /* power down */
  252. twl4030_codec_enable(codec, 0);
  253. }
  254. /* Earpiece */
  255. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  256. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  257. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  258. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  259. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  260. };
  261. /* PreDrive Left */
  262. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  263. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  264. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  265. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  266. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  267. };
  268. /* PreDrive Right */
  269. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  270. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  271. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  272. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  273. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  274. };
  275. /* Headset Left */
  276. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  277. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  278. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  279. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  280. };
  281. /* Headset Right */
  282. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  283. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  284. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  285. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  286. };
  287. /* Carkit Left */
  288. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  289. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  290. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  291. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  292. };
  293. /* Carkit Right */
  294. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  295. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  296. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  297. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  298. };
  299. /* Handsfree Left */
  300. static const char *twl4030_handsfreel_texts[] =
  301. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  302. static const struct soc_enum twl4030_handsfreel_enum =
  303. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  304. ARRAY_SIZE(twl4030_handsfreel_texts),
  305. twl4030_handsfreel_texts);
  306. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  307. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  308. /* Handsfree Left virtual mute */
  309. static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
  310. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
  311. /* Handsfree Right */
  312. static const char *twl4030_handsfreer_texts[] =
  313. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  314. static const struct soc_enum twl4030_handsfreer_enum =
  315. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  316. ARRAY_SIZE(twl4030_handsfreer_texts),
  317. twl4030_handsfreer_texts);
  318. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  319. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  320. /* Handsfree Right virtual mute */
  321. static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
  322. SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
  323. /* Vibra */
  324. /* Vibra audio path selection */
  325. static const char *twl4030_vibra_texts[] =
  326. {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
  327. static const struct soc_enum twl4030_vibra_enum =
  328. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
  329. ARRAY_SIZE(twl4030_vibra_texts),
  330. twl4030_vibra_texts);
  331. static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
  332. SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
  333. /* Vibra path selection: local vibrator (PWM) or audio driven */
  334. static const char *twl4030_vibrapath_texts[] =
  335. {"Local vibrator", "Audio"};
  336. static const struct soc_enum twl4030_vibrapath_enum =
  337. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
  338. ARRAY_SIZE(twl4030_vibrapath_texts),
  339. twl4030_vibrapath_texts);
  340. static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
  341. SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
  342. /* Left analog microphone selection */
  343. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
  344. SOC_DAPM_SINGLE("Main mic", TWL4030_REG_ANAMICL, 0, 1, 0),
  345. SOC_DAPM_SINGLE("Headset mic", TWL4030_REG_ANAMICL, 1, 1, 0),
  346. SOC_DAPM_SINGLE("AUXL", TWL4030_REG_ANAMICL, 2, 1, 0),
  347. SOC_DAPM_SINGLE("Carkit mic", TWL4030_REG_ANAMICL, 3, 1, 0),
  348. };
  349. /* Right analog microphone selection */
  350. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
  351. SOC_DAPM_SINGLE("Sub mic", TWL4030_REG_ANAMICR, 0, 1, 0),
  352. SOC_DAPM_SINGLE("AUXR", TWL4030_REG_ANAMICR, 2, 1, 0),
  353. };
  354. /* TX1 L/R Analog/Digital microphone selection */
  355. static const char *twl4030_micpathtx1_texts[] =
  356. {"Analog", "Digimic0"};
  357. static const struct soc_enum twl4030_micpathtx1_enum =
  358. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  359. ARRAY_SIZE(twl4030_micpathtx1_texts),
  360. twl4030_micpathtx1_texts);
  361. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  362. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  363. /* TX2 L/R Analog/Digital microphone selection */
  364. static const char *twl4030_micpathtx2_texts[] =
  365. {"Analog", "Digimic1"};
  366. static const struct soc_enum twl4030_micpathtx2_enum =
  367. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  368. ARRAY_SIZE(twl4030_micpathtx2_texts),
  369. twl4030_micpathtx2_texts);
  370. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  371. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  372. /* Analog bypass for AudioR1 */
  373. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  374. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  375. /* Analog bypass for AudioL1 */
  376. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  377. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  378. /* Analog bypass for AudioR2 */
  379. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  380. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  381. /* Analog bypass for AudioL2 */
  382. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  383. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  384. /* Analog bypass for Voice */
  385. static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
  386. SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
  387. /* Digital bypass gain, 0 mutes the bypass */
  388. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  389. TLV_DB_RANGE_HEAD(2),
  390. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  391. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  392. };
  393. /* Digital bypass left (TX1L -> RX2L) */
  394. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  395. SOC_DAPM_SINGLE_TLV("Volume",
  396. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  397. twl4030_dapm_dbypass_tlv);
  398. /* Digital bypass right (TX1R -> RX2R) */
  399. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  400. SOC_DAPM_SINGLE_TLV("Volume",
  401. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  402. twl4030_dapm_dbypass_tlv);
  403. /*
  404. * Voice Sidetone GAIN volume control:
  405. * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
  406. */
  407. static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
  408. /* Digital bypass voice: sidetone (VUL -> VDL)*/
  409. static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
  410. SOC_DAPM_SINGLE_TLV("Volume",
  411. TWL4030_REG_VSTPGA, 0, 0x29, 0,
  412. twl4030_dapm_dbypassv_tlv);
  413. static int micpath_event(struct snd_soc_dapm_widget *w,
  414. struct snd_kcontrol *kcontrol, int event)
  415. {
  416. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  417. unsigned char adcmicsel, micbias_ctl;
  418. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  419. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  420. /* Prepare the bits for the given TX path:
  421. * shift_l == 0: TX1 microphone path
  422. * shift_l == 2: TX2 microphone path */
  423. if (e->shift_l) {
  424. /* TX2 microphone path */
  425. if (adcmicsel & TWL4030_TX2IN_SEL)
  426. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  427. else
  428. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  429. } else {
  430. /* TX1 microphone path */
  431. if (adcmicsel & TWL4030_TX1IN_SEL)
  432. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  433. else
  434. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  435. }
  436. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  437. return 0;
  438. }
  439. /*
  440. * Output PGA builder:
  441. * Handle the muting and unmuting of the given output (turning off the
  442. * amplifier associated with the output pin)
  443. * On mute bypass the reg_cache and mute the volume
  444. * On unmute: restore the register content
  445. * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
  446. */
  447. #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
  448. static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
  449. struct snd_kcontrol *kcontrol, int event) \
  450. { \
  451. u8 reg_val; \
  452. \
  453. switch (event) { \
  454. case SND_SOC_DAPM_POST_PMU: \
  455. twl4030_write(w->codec, reg, \
  456. twl4030_read_reg_cache(w->codec, reg)); \
  457. break; \
  458. case SND_SOC_DAPM_POST_PMD: \
  459. reg_val = twl4030_read_reg_cache(w->codec, reg); \
  460. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
  461. reg_val & (~mask), \
  462. reg); \
  463. break; \
  464. } \
  465. return 0; \
  466. }
  467. TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
  468. TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
  469. TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
  470. TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
  471. TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
  472. static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
  473. {
  474. unsigned char hs_ctl;
  475. hs_ctl = twl4030_read_reg_cache(codec, reg);
  476. if (ramp) {
  477. /* HF ramp-up */
  478. hs_ctl |= TWL4030_HF_CTL_REF_EN;
  479. twl4030_write(codec, reg, hs_ctl);
  480. udelay(10);
  481. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  482. twl4030_write(codec, reg, hs_ctl);
  483. udelay(40);
  484. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  485. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  486. twl4030_write(codec, reg, hs_ctl);
  487. } else {
  488. /* HF ramp-down */
  489. hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
  490. hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
  491. twl4030_write(codec, reg, hs_ctl);
  492. hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
  493. twl4030_write(codec, reg, hs_ctl);
  494. udelay(40);
  495. hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
  496. twl4030_write(codec, reg, hs_ctl);
  497. }
  498. }
  499. static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
  500. struct snd_kcontrol *kcontrol, int event)
  501. {
  502. switch (event) {
  503. case SND_SOC_DAPM_POST_PMU:
  504. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
  505. break;
  506. case SND_SOC_DAPM_POST_PMD:
  507. handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
  508. break;
  509. }
  510. return 0;
  511. }
  512. static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
  513. struct snd_kcontrol *kcontrol, int event)
  514. {
  515. switch (event) {
  516. case SND_SOC_DAPM_POST_PMU:
  517. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
  518. break;
  519. case SND_SOC_DAPM_POST_PMD:
  520. handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
  521. break;
  522. }
  523. return 0;
  524. }
  525. static void headset_ramp(struct snd_soc_codec *codec, int ramp)
  526. {
  527. struct snd_soc_device *socdev = codec->socdev;
  528. struct twl4030_setup_data *setup = socdev->codec_data;
  529. unsigned char hs_gain, hs_pop;
  530. struct twl4030_priv *twl4030 = codec->private_data;
  531. /* Base values for ramp delay calculation: 2^19 - 2^26 */
  532. unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
  533. 8388608, 16777216, 33554432, 67108864};
  534. hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
  535. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  536. /* Enable external mute control, this dramatically reduces
  537. * the pop-noise */
  538. if (setup && setup->hs_extmute) {
  539. if (setup->set_hs_extmute) {
  540. setup->set_hs_extmute(1);
  541. } else {
  542. hs_pop |= TWL4030_EXTMUTE;
  543. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  544. }
  545. }
  546. if (ramp) {
  547. /* Headset ramp-up according to the TRM */
  548. hs_pop |= TWL4030_VMID_EN;
  549. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  550. twl4030_write(codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  551. hs_pop |= TWL4030_RAMP_EN;
  552. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  553. /* Wait ramp delay time + 1, so the VMID can settle */
  554. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  555. twl4030->sysclk) + 1);
  556. } else {
  557. /* Headset ramp-down _not_ according to
  558. * the TRM, but in a way that it is working */
  559. hs_pop &= ~TWL4030_RAMP_EN;
  560. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  561. /* Wait ramp delay time + 1, so the VMID can settle */
  562. mdelay((ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
  563. twl4030->sysclk) + 1);
  564. /* Bypass the reg_cache to mute the headset */
  565. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  566. hs_gain & (~0x0f),
  567. TWL4030_REG_HS_GAIN_SET);
  568. hs_pop &= ~TWL4030_VMID_EN;
  569. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  570. }
  571. /* Disable external mute */
  572. if (setup && setup->hs_extmute) {
  573. if (setup->set_hs_extmute) {
  574. setup->set_hs_extmute(0);
  575. } else {
  576. hs_pop &= ~TWL4030_EXTMUTE;
  577. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  578. }
  579. }
  580. }
  581. static int headsetlpga_event(struct snd_soc_dapm_widget *w,
  582. struct snd_kcontrol *kcontrol, int event)
  583. {
  584. struct twl4030_priv *twl4030 = w->codec->private_data;
  585. switch (event) {
  586. case SND_SOC_DAPM_POST_PMU:
  587. /* Do the ramp-up only once */
  588. if (!twl4030->hsr_enabled)
  589. headset_ramp(w->codec, 1);
  590. twl4030->hsl_enabled = 1;
  591. break;
  592. case SND_SOC_DAPM_POST_PMD:
  593. /* Do the ramp-down only if both headsetL/R is disabled */
  594. if (!twl4030->hsr_enabled)
  595. headset_ramp(w->codec, 0);
  596. twl4030->hsl_enabled = 0;
  597. break;
  598. }
  599. return 0;
  600. }
  601. static int headsetrpga_event(struct snd_soc_dapm_widget *w,
  602. struct snd_kcontrol *kcontrol, int event)
  603. {
  604. struct twl4030_priv *twl4030 = w->codec->private_data;
  605. switch (event) {
  606. case SND_SOC_DAPM_POST_PMU:
  607. /* Do the ramp-up only once */
  608. if (!twl4030->hsl_enabled)
  609. headset_ramp(w->codec, 1);
  610. twl4030->hsr_enabled = 1;
  611. break;
  612. case SND_SOC_DAPM_POST_PMD:
  613. /* Do the ramp-down only if both headsetL/R is disabled */
  614. if (!twl4030->hsl_enabled)
  615. headset_ramp(w->codec, 0);
  616. twl4030->hsr_enabled = 0;
  617. break;
  618. }
  619. return 0;
  620. }
  621. static int bypass_event(struct snd_soc_dapm_widget *w,
  622. struct snd_kcontrol *kcontrol, int event)
  623. {
  624. struct soc_mixer_control *m =
  625. (struct soc_mixer_control *)w->kcontrols->private_value;
  626. struct twl4030_priv *twl4030 = w->codec->private_data;
  627. unsigned char reg, misc;
  628. reg = twl4030_read_reg_cache(w->codec, m->reg);
  629. /*
  630. * bypass_state[0:3] - analog HiFi bypass
  631. * bypass_state[4] - analog voice bypass
  632. * bypass_state[5] - digital voice bypass
  633. * bypass_state[6:7] - digital HiFi bypass
  634. */
  635. if (m->reg == TWL4030_REG_VSTPGA) {
  636. /* Voice digital bypass */
  637. if (reg)
  638. twl4030->bypass_state |= (1 << 5);
  639. else
  640. twl4030->bypass_state &= ~(1 << 5);
  641. } else if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  642. /* Analog bypass */
  643. if (reg & (1 << m->shift))
  644. twl4030->bypass_state |=
  645. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  646. else
  647. twl4030->bypass_state &=
  648. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  649. } else if (m->reg == TWL4030_REG_VDL_APGA_CTL) {
  650. /* Analog voice bypass */
  651. if (reg & (1 << m->shift))
  652. twl4030->bypass_state |= (1 << 4);
  653. else
  654. twl4030->bypass_state &= ~(1 << 4);
  655. } else {
  656. /* Digital bypass */
  657. if (reg & (0x7 << m->shift))
  658. twl4030->bypass_state |= (1 << (m->shift ? 7 : 6));
  659. else
  660. twl4030->bypass_state &= ~(1 << (m->shift ? 7 : 6));
  661. }
  662. /* Enable master analog loopback mode if any analog switch is enabled*/
  663. misc = twl4030_read_reg_cache(w->codec, TWL4030_REG_MISC_SET_1);
  664. if (twl4030->bypass_state & 0x1F)
  665. misc |= TWL4030_FMLOOP_EN;
  666. else
  667. misc &= ~TWL4030_FMLOOP_EN;
  668. twl4030_write(w->codec, TWL4030_REG_MISC_SET_1, misc);
  669. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  670. if (twl4030->bypass_state)
  671. twl4030_codec_mute(w->codec, 0);
  672. else
  673. twl4030_codec_mute(w->codec, 1);
  674. }
  675. return 0;
  676. }
  677. /*
  678. * Some of the gain controls in TWL (mostly those which are associated with
  679. * the outputs) are implemented in an interesting way:
  680. * 0x0 : Power down (mute)
  681. * 0x1 : 6dB
  682. * 0x2 : 0 dB
  683. * 0x3 : -6 dB
  684. * Inverting not going to help with these.
  685. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  686. */
  687. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  688. xinvert, tlv_array) \
  689. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  690. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  691. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  692. .tlv.p = (tlv_array), \
  693. .info = snd_soc_info_volsw, \
  694. .get = snd_soc_get_volsw_twl4030, \
  695. .put = snd_soc_put_volsw_twl4030, \
  696. .private_value = (unsigned long)&(struct soc_mixer_control) \
  697. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  698. .max = xmax, .invert = xinvert} }
  699. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  700. xinvert, tlv_array) \
  701. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  702. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  703. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  704. .tlv.p = (tlv_array), \
  705. .info = snd_soc_info_volsw_2r, \
  706. .get = snd_soc_get_volsw_r2_twl4030,\
  707. .put = snd_soc_put_volsw_r2_twl4030, \
  708. .private_value = (unsigned long)&(struct soc_mixer_control) \
  709. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  710. .rshift = xshift, .max = xmax, .invert = xinvert} }
  711. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  712. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  713. xinvert, tlv_array)
  714. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  715. struct snd_ctl_elem_value *ucontrol)
  716. {
  717. struct soc_mixer_control *mc =
  718. (struct soc_mixer_control *)kcontrol->private_value;
  719. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  720. unsigned int reg = mc->reg;
  721. unsigned int shift = mc->shift;
  722. unsigned int rshift = mc->rshift;
  723. int max = mc->max;
  724. int mask = (1 << fls(max)) - 1;
  725. ucontrol->value.integer.value[0] =
  726. (snd_soc_read(codec, reg) >> shift) & mask;
  727. if (ucontrol->value.integer.value[0])
  728. ucontrol->value.integer.value[0] =
  729. max + 1 - ucontrol->value.integer.value[0];
  730. if (shift != rshift) {
  731. ucontrol->value.integer.value[1] =
  732. (snd_soc_read(codec, reg) >> rshift) & mask;
  733. if (ucontrol->value.integer.value[1])
  734. ucontrol->value.integer.value[1] =
  735. max + 1 - ucontrol->value.integer.value[1];
  736. }
  737. return 0;
  738. }
  739. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  740. struct snd_ctl_elem_value *ucontrol)
  741. {
  742. struct soc_mixer_control *mc =
  743. (struct soc_mixer_control *)kcontrol->private_value;
  744. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  745. unsigned int reg = mc->reg;
  746. unsigned int shift = mc->shift;
  747. unsigned int rshift = mc->rshift;
  748. int max = mc->max;
  749. int mask = (1 << fls(max)) - 1;
  750. unsigned short val, val2, val_mask;
  751. val = (ucontrol->value.integer.value[0] & mask);
  752. val_mask = mask << shift;
  753. if (val)
  754. val = max + 1 - val;
  755. val = val << shift;
  756. if (shift != rshift) {
  757. val2 = (ucontrol->value.integer.value[1] & mask);
  758. val_mask |= mask << rshift;
  759. if (val2)
  760. val2 = max + 1 - val2;
  761. val |= val2 << rshift;
  762. }
  763. return snd_soc_update_bits(codec, reg, val_mask, val);
  764. }
  765. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  766. struct snd_ctl_elem_value *ucontrol)
  767. {
  768. struct soc_mixer_control *mc =
  769. (struct soc_mixer_control *)kcontrol->private_value;
  770. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  771. unsigned int reg = mc->reg;
  772. unsigned int reg2 = mc->rreg;
  773. unsigned int shift = mc->shift;
  774. int max = mc->max;
  775. int mask = (1<<fls(max))-1;
  776. ucontrol->value.integer.value[0] =
  777. (snd_soc_read(codec, reg) >> shift) & mask;
  778. ucontrol->value.integer.value[1] =
  779. (snd_soc_read(codec, reg2) >> shift) & mask;
  780. if (ucontrol->value.integer.value[0])
  781. ucontrol->value.integer.value[0] =
  782. max + 1 - ucontrol->value.integer.value[0];
  783. if (ucontrol->value.integer.value[1])
  784. ucontrol->value.integer.value[1] =
  785. max + 1 - ucontrol->value.integer.value[1];
  786. return 0;
  787. }
  788. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  789. struct snd_ctl_elem_value *ucontrol)
  790. {
  791. struct soc_mixer_control *mc =
  792. (struct soc_mixer_control *)kcontrol->private_value;
  793. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  794. unsigned int reg = mc->reg;
  795. unsigned int reg2 = mc->rreg;
  796. unsigned int shift = mc->shift;
  797. int max = mc->max;
  798. int mask = (1 << fls(max)) - 1;
  799. int err;
  800. unsigned short val, val2, val_mask;
  801. val_mask = mask << shift;
  802. val = (ucontrol->value.integer.value[0] & mask);
  803. val2 = (ucontrol->value.integer.value[1] & mask);
  804. if (val)
  805. val = max + 1 - val;
  806. if (val2)
  807. val2 = max + 1 - val2;
  808. val = val << shift;
  809. val2 = val2 << shift;
  810. err = snd_soc_update_bits(codec, reg, val_mask, val);
  811. if (err < 0)
  812. return err;
  813. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  814. return err;
  815. }
  816. /* Codec operation modes */
  817. static const char *twl4030_op_modes_texts[] = {
  818. "Option 2 (voice/audio)", "Option 1 (audio)"
  819. };
  820. static const struct soc_enum twl4030_op_modes_enum =
  821. SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
  822. ARRAY_SIZE(twl4030_op_modes_texts),
  823. twl4030_op_modes_texts);
  824. static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
  825. struct snd_ctl_elem_value *ucontrol)
  826. {
  827. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  828. struct twl4030_priv *twl4030 = codec->private_data;
  829. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  830. unsigned short val;
  831. unsigned short mask, bitmask;
  832. if (twl4030->configured) {
  833. printk(KERN_ERR "twl4030 operation mode cannot be "
  834. "changed on-the-fly\n");
  835. return -EBUSY;
  836. }
  837. for (bitmask = 1; bitmask < e->max; bitmask <<= 1)
  838. ;
  839. if (ucontrol->value.enumerated.item[0] > e->max - 1)
  840. return -EINVAL;
  841. val = ucontrol->value.enumerated.item[0] << e->shift_l;
  842. mask = (bitmask - 1) << e->shift_l;
  843. if (e->shift_l != e->shift_r) {
  844. if (ucontrol->value.enumerated.item[1] > e->max - 1)
  845. return -EINVAL;
  846. val |= ucontrol->value.enumerated.item[1] << e->shift_r;
  847. mask |= (bitmask - 1) << e->shift_r;
  848. }
  849. return snd_soc_update_bits(codec, e->reg, mask, val);
  850. }
  851. /*
  852. * FGAIN volume control:
  853. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  854. */
  855. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  856. /*
  857. * CGAIN volume control:
  858. * 0 dB to 12 dB in 6 dB steps
  859. * value 2 and 3 means 12 dB
  860. */
  861. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  862. /*
  863. * Voice Downlink GAIN volume control:
  864. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  865. */
  866. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  867. /*
  868. * Analog playback gain
  869. * -24 dB to 12 dB in 2 dB steps
  870. */
  871. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  872. /*
  873. * Gain controls tied to outputs
  874. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  875. */
  876. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  877. /*
  878. * Gain control for earpiece amplifier
  879. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  880. */
  881. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  882. /*
  883. * Capture gain after the ADCs
  884. * from 0 dB to 31 dB in 1 dB steps
  885. */
  886. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  887. /*
  888. * Gain control for input amplifiers
  889. * 0 dB to 30 dB in 6 dB steps
  890. */
  891. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  892. /* AVADC clock priority */
  893. static const char *twl4030_avadc_clk_priority_texts[] = {
  894. "Voice high priority", "HiFi high priority"
  895. };
  896. static const struct soc_enum twl4030_avadc_clk_priority_enum =
  897. SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
  898. ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
  899. twl4030_avadc_clk_priority_texts);
  900. static const char *twl4030_rampdelay_texts[] = {
  901. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  902. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  903. "3495/2581/1748 ms"
  904. };
  905. static const struct soc_enum twl4030_rampdelay_enum =
  906. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  907. ARRAY_SIZE(twl4030_rampdelay_texts),
  908. twl4030_rampdelay_texts);
  909. /* Vibra H-bridge direction mode */
  910. static const char *twl4030_vibradirmode_texts[] = {
  911. "Vibra H-bridge direction", "Audio data MSB",
  912. };
  913. static const struct soc_enum twl4030_vibradirmode_enum =
  914. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
  915. ARRAY_SIZE(twl4030_vibradirmode_texts),
  916. twl4030_vibradirmode_texts);
  917. /* Vibra H-bridge direction */
  918. static const char *twl4030_vibradir_texts[] = {
  919. "Positive polarity", "Negative polarity",
  920. };
  921. static const struct soc_enum twl4030_vibradir_enum =
  922. SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
  923. ARRAY_SIZE(twl4030_vibradir_texts),
  924. twl4030_vibradir_texts);
  925. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  926. /* Codec operation mode control */
  927. SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
  928. snd_soc_get_enum_double,
  929. snd_soc_put_twl4030_opmode_enum_double),
  930. /* Common playback gain controls */
  931. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  932. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  933. 0, 0x3f, 0, digital_fine_tlv),
  934. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  935. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  936. 0, 0x3f, 0, digital_fine_tlv),
  937. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  938. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  939. 6, 0x2, 0, digital_coarse_tlv),
  940. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  941. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  942. 6, 0x2, 0, digital_coarse_tlv),
  943. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  944. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  945. 3, 0x12, 1, analog_tlv),
  946. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  947. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  948. 3, 0x12, 1, analog_tlv),
  949. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  950. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  951. 1, 1, 0),
  952. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  953. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  954. 1, 1, 0),
  955. /* Common voice downlink gain controls */
  956. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  957. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  958. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  959. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  960. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  961. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  962. /* Separate output gain controls */
  963. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  964. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  965. 4, 3, 0, output_tvl),
  966. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  967. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  968. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  969. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  970. 4, 3, 0, output_tvl),
  971. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  972. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  973. /* Common capture gain controls */
  974. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  975. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  976. 0, 0x1f, 0, digital_capture_tlv),
  977. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  978. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  979. 0, 0x1f, 0, digital_capture_tlv),
  980. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  981. 0, 3, 5, 0, input_gain_tlv),
  982. SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
  983. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  984. SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
  985. SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
  986. };
  987. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  988. /* Left channel inputs */
  989. SND_SOC_DAPM_INPUT("MAINMIC"),
  990. SND_SOC_DAPM_INPUT("HSMIC"),
  991. SND_SOC_DAPM_INPUT("AUXL"),
  992. SND_SOC_DAPM_INPUT("CARKITMIC"),
  993. /* Right channel inputs */
  994. SND_SOC_DAPM_INPUT("SUBMIC"),
  995. SND_SOC_DAPM_INPUT("AUXR"),
  996. /* Digital microphones (Stereo) */
  997. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  998. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  999. /* Outputs */
  1000. SND_SOC_DAPM_OUTPUT("OUTL"),
  1001. SND_SOC_DAPM_OUTPUT("OUTR"),
  1002. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  1003. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  1004. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  1005. SND_SOC_DAPM_OUTPUT("HSOL"),
  1006. SND_SOC_DAPM_OUTPUT("HSOR"),
  1007. SND_SOC_DAPM_OUTPUT("CARKITL"),
  1008. SND_SOC_DAPM_OUTPUT("CARKITR"),
  1009. SND_SOC_DAPM_OUTPUT("HFL"),
  1010. SND_SOC_DAPM_OUTPUT("HFR"),
  1011. SND_SOC_DAPM_OUTPUT("VIBRA"),
  1012. /* DACs */
  1013. SND_SOC_DAPM_DAC("DAC Right1", "Right Front HiFi Playback",
  1014. SND_SOC_NOPM, 0, 0),
  1015. SND_SOC_DAPM_DAC("DAC Left1", "Left Front HiFi Playback",
  1016. SND_SOC_NOPM, 0, 0),
  1017. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear HiFi Playback",
  1018. SND_SOC_NOPM, 0, 0),
  1019. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear HiFi Playback",
  1020. SND_SOC_NOPM, 0, 0),
  1021. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  1022. SND_SOC_NOPM, 0, 0),
  1023. /* Analog bypasses */
  1024. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1025. &twl4030_dapm_abypassr1_control, bypass_event,
  1026. SND_SOC_DAPM_POST_REG),
  1027. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1028. &twl4030_dapm_abypassl1_control,
  1029. bypass_event, SND_SOC_DAPM_POST_REG),
  1030. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1031. &twl4030_dapm_abypassr2_control,
  1032. bypass_event, SND_SOC_DAPM_POST_REG),
  1033. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  1034. &twl4030_dapm_abypassl2_control,
  1035. bypass_event, SND_SOC_DAPM_POST_REG),
  1036. SND_SOC_DAPM_SWITCH_E("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
  1037. &twl4030_dapm_abypassv_control,
  1038. bypass_event, SND_SOC_DAPM_POST_REG),
  1039. /* Digital bypasses */
  1040. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  1041. &twl4030_dapm_dbypassl_control, bypass_event,
  1042. SND_SOC_DAPM_POST_REG),
  1043. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  1044. &twl4030_dapm_dbypassr_control, bypass_event,
  1045. SND_SOC_DAPM_POST_REG),
  1046. SND_SOC_DAPM_SWITCH_E("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
  1047. &twl4030_dapm_dbypassv_control, bypass_event,
  1048. SND_SOC_DAPM_POST_REG),
  1049. /* Digital mixers, power control for the physical DACs */
  1050. SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
  1051. TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
  1052. SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
  1053. TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
  1054. SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
  1055. TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
  1056. SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
  1057. TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
  1058. SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
  1059. TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
  1060. /* Analog mixers, power control for the physical PGAs */
  1061. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
  1062. TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
  1063. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
  1064. TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
  1065. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
  1066. TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
  1067. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
  1068. TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
  1069. SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
  1070. TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
  1071. /* Output MIXER controls */
  1072. /* Earpiece */
  1073. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  1074. &twl4030_dapm_earpiece_controls[0],
  1075. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  1076. SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
  1077. 0, 0, NULL, 0, earpiecepga_event,
  1078. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1079. /* PreDrivL/R */
  1080. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  1081. &twl4030_dapm_predrivel_controls[0],
  1082. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  1083. SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
  1084. 0, 0, NULL, 0, predrivelpga_event,
  1085. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1086. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  1087. &twl4030_dapm_predriver_controls[0],
  1088. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  1089. SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
  1090. 0, 0, NULL, 0, predriverpga_event,
  1091. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1092. /* HeadsetL/R */
  1093. SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  1094. &twl4030_dapm_hsol_controls[0],
  1095. ARRAY_SIZE(twl4030_dapm_hsol_controls)),
  1096. SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
  1097. 0, 0, NULL, 0, headsetlpga_event,
  1098. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1099. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  1100. &twl4030_dapm_hsor_controls[0],
  1101. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  1102. SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
  1103. 0, 0, NULL, 0, headsetrpga_event,
  1104. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1105. /* CarkitL/R */
  1106. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  1107. &twl4030_dapm_carkitl_controls[0],
  1108. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  1109. SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
  1110. 0, 0, NULL, 0, carkitlpga_event,
  1111. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1112. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  1113. &twl4030_dapm_carkitr_controls[0],
  1114. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  1115. SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
  1116. 0, 0, NULL, 0, carkitrpga_event,
  1117. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1118. /* Output MUX controls */
  1119. /* HandsfreeL/R */
  1120. SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
  1121. &twl4030_dapm_handsfreel_control),
  1122. SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
  1123. &twl4030_dapm_handsfreelmute_control),
  1124. SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
  1125. 0, 0, NULL, 0, handsfreelpga_event,
  1126. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1127. SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
  1128. &twl4030_dapm_handsfreer_control),
  1129. SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
  1130. &twl4030_dapm_handsfreermute_control),
  1131. SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
  1132. 0, 0, NULL, 0, handsfreerpga_event,
  1133. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  1134. /* Vibra */
  1135. SND_SOC_DAPM_MUX("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
  1136. &twl4030_dapm_vibra_control),
  1137. SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
  1138. &twl4030_dapm_vibrapath_control),
  1139. /* Introducing four virtual ADC, since TWL4030 have four channel for
  1140. capture */
  1141. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  1142. SND_SOC_NOPM, 0, 0),
  1143. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  1144. SND_SOC_NOPM, 0, 0),
  1145. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  1146. SND_SOC_NOPM, 0, 0),
  1147. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  1148. SND_SOC_NOPM, 0, 0),
  1149. /* Analog/Digital mic path selection.
  1150. TX1 Left/Right: either analog Left/Right or Digimic0
  1151. TX2 Left/Right: either analog Left/Right or Digimic1 */
  1152. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  1153. &twl4030_dapm_micpathtx1_control, micpath_event,
  1154. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1155. SND_SOC_DAPM_POST_REG),
  1156. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  1157. &twl4030_dapm_micpathtx2_control, micpath_event,
  1158. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  1159. SND_SOC_DAPM_POST_REG),
  1160. /* Analog input mixers for the capture amplifiers */
  1161. SND_SOC_DAPM_MIXER("Analog Left Capture Route",
  1162. TWL4030_REG_ANAMICL, 4, 0,
  1163. &twl4030_dapm_analoglmic_controls[0],
  1164. ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
  1165. SND_SOC_DAPM_MIXER("Analog Right Capture Route",
  1166. TWL4030_REG_ANAMICR, 4, 0,
  1167. &twl4030_dapm_analogrmic_controls[0],
  1168. ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
  1169. SND_SOC_DAPM_PGA("ADC Physical Left",
  1170. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  1171. SND_SOC_DAPM_PGA("ADC Physical Right",
  1172. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  1173. SND_SOC_DAPM_PGA("Digimic0 Enable",
  1174. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  1175. SND_SOC_DAPM_PGA("Digimic1 Enable",
  1176. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  1177. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  1178. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  1179. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  1180. };
  1181. static const struct snd_soc_dapm_route intercon[] = {
  1182. {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
  1183. {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
  1184. {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
  1185. {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
  1186. {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
  1187. {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
  1188. {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
  1189. {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
  1190. {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
  1191. {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
  1192. /* Internal playback routings */
  1193. /* Earpiece */
  1194. {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
  1195. {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1196. {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1197. {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1198. {"Earpiece PGA", NULL, "Earpiece Mixer"},
  1199. /* PreDrivL */
  1200. {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1201. {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1202. {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1203. {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1204. {"PredriveL PGA", NULL, "PredriveL Mixer"},
  1205. /* PreDrivR */
  1206. {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1207. {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1208. {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1209. {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1210. {"PredriveR PGA", NULL, "PredriveR Mixer"},
  1211. /* HeadsetL */
  1212. {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1213. {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1214. {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1215. {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
  1216. /* HeadsetR */
  1217. {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1218. {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1219. {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1220. {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
  1221. /* CarkitL */
  1222. {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
  1223. {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
  1224. {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
  1225. {"CarkitL PGA", NULL, "CarkitL Mixer"},
  1226. /* CarkitR */
  1227. {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
  1228. {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
  1229. {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
  1230. {"CarkitR PGA", NULL, "CarkitR Mixer"},
  1231. /* HandsfreeL */
  1232. {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
  1233. {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
  1234. {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1235. {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1236. {"HandsfreeL", "Switch", "HandsfreeL Mux"},
  1237. {"HandsfreeL PGA", NULL, "HandsfreeL"},
  1238. /* HandsfreeR */
  1239. {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
  1240. {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
  1241. {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
  1242. {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
  1243. {"HandsfreeR", "Switch", "HandsfreeR Mux"},
  1244. {"HandsfreeR PGA", NULL, "HandsfreeR"},
  1245. /* Vibra */
  1246. {"Vibra Mux", "AudioL1", "DAC Left1"},
  1247. {"Vibra Mux", "AudioR1", "DAC Right1"},
  1248. {"Vibra Mux", "AudioL2", "DAC Left2"},
  1249. {"Vibra Mux", "AudioR2", "DAC Right2"},
  1250. /* outputs */
  1251. {"OUTL", NULL, "Analog L2 Playback Mixer"},
  1252. {"OUTR", NULL, "Analog R2 Playback Mixer"},
  1253. {"EARPIECE", NULL, "Earpiece PGA"},
  1254. {"PREDRIVEL", NULL, "PredriveL PGA"},
  1255. {"PREDRIVER", NULL, "PredriveR PGA"},
  1256. {"HSOL", NULL, "HeadsetL PGA"},
  1257. {"HSOR", NULL, "HeadsetR PGA"},
  1258. {"CARKITL", NULL, "CarkitL PGA"},
  1259. {"CARKITR", NULL, "CarkitR PGA"},
  1260. {"HFL", NULL, "HandsfreeL PGA"},
  1261. {"HFR", NULL, "HandsfreeR PGA"},
  1262. {"Vibra Route", "Audio", "Vibra Mux"},
  1263. {"VIBRA", NULL, "Vibra Route"},
  1264. /* Capture path */
  1265. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  1266. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  1267. {"Analog Left Capture Route", "AUXL", "AUXL"},
  1268. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  1269. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  1270. {"Analog Right Capture Route", "AUXR", "AUXR"},
  1271. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  1272. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  1273. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  1274. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  1275. /* TX1 Left capture path */
  1276. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  1277. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1278. /* TX1 Right capture path */
  1279. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  1280. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  1281. /* TX2 Left capture path */
  1282. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1283. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1284. /* TX2 Right capture path */
  1285. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1286. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1287. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1288. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1289. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1290. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1291. /* Analog bypass routes */
  1292. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1293. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1294. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1295. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1296. {"Voice Analog Loopback", "Switch", "Analog Left Capture Route"},
  1297. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1298. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1299. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1300. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1301. {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
  1302. /* Digital bypass routes */
  1303. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1304. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1305. {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
  1306. {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1307. {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1308. {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
  1309. };
  1310. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1311. {
  1312. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1313. ARRAY_SIZE(twl4030_dapm_widgets));
  1314. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1315. snd_soc_dapm_new_widgets(codec);
  1316. return 0;
  1317. }
  1318. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1319. enum snd_soc_bias_level level)
  1320. {
  1321. struct twl4030_priv *twl4030 = codec->private_data;
  1322. switch (level) {
  1323. case SND_SOC_BIAS_ON:
  1324. twl4030_codec_mute(codec, 0);
  1325. break;
  1326. case SND_SOC_BIAS_PREPARE:
  1327. twl4030_power_up(codec);
  1328. if (twl4030->bypass_state)
  1329. twl4030_codec_mute(codec, 0);
  1330. else
  1331. twl4030_codec_mute(codec, 1);
  1332. break;
  1333. case SND_SOC_BIAS_STANDBY:
  1334. twl4030_power_up(codec);
  1335. if (twl4030->bypass_state)
  1336. twl4030_codec_mute(codec, 0);
  1337. else
  1338. twl4030_codec_mute(codec, 1);
  1339. break;
  1340. case SND_SOC_BIAS_OFF:
  1341. twl4030_power_down(codec);
  1342. break;
  1343. }
  1344. codec->bias_level = level;
  1345. return 0;
  1346. }
  1347. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1348. struct snd_pcm_substream *mst_substream)
  1349. {
  1350. struct snd_pcm_substream *slv_substream;
  1351. /* Pick the stream, which need to be constrained */
  1352. if (mst_substream == twl4030->master_substream)
  1353. slv_substream = twl4030->slave_substream;
  1354. else if (mst_substream == twl4030->slave_substream)
  1355. slv_substream = twl4030->master_substream;
  1356. else /* This should not happen.. */
  1357. return;
  1358. /* Set the constraints according to the already configured stream */
  1359. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1360. SNDRV_PCM_HW_PARAM_RATE,
  1361. twl4030->rate,
  1362. twl4030->rate);
  1363. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1364. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1365. twl4030->sample_bits,
  1366. twl4030->sample_bits);
  1367. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1368. SNDRV_PCM_HW_PARAM_CHANNELS,
  1369. twl4030->channels,
  1370. twl4030->channels);
  1371. }
  1372. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1373. * capture has to be enabled/disabled. */
  1374. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1375. int enable)
  1376. {
  1377. u8 reg, mask;
  1378. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1379. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1380. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1381. else
  1382. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1383. if (enable)
  1384. reg |= mask;
  1385. else
  1386. reg &= ~mask;
  1387. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1388. }
  1389. static int twl4030_startup(struct snd_pcm_substream *substream,
  1390. struct snd_soc_dai *dai)
  1391. {
  1392. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1393. struct snd_soc_device *socdev = rtd->socdev;
  1394. struct snd_soc_codec *codec = socdev->card->codec;
  1395. struct twl4030_priv *twl4030 = codec->private_data;
  1396. if (twl4030->master_substream) {
  1397. twl4030->slave_substream = substream;
  1398. /* The DAI has one configuration for playback and capture, so
  1399. * if the DAI has been already configured then constrain this
  1400. * substream to match it. */
  1401. if (twl4030->configured)
  1402. twl4030_constraints(twl4030, twl4030->master_substream);
  1403. } else {
  1404. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1405. TWL4030_OPTION_1)) {
  1406. /* In option2 4 channel is not supported, set the
  1407. * constraint for the first stream for channels, the
  1408. * second stream will 'inherit' this cosntraint */
  1409. snd_pcm_hw_constraint_minmax(substream->runtime,
  1410. SNDRV_PCM_HW_PARAM_CHANNELS,
  1411. 2, 2);
  1412. }
  1413. twl4030->master_substream = substream;
  1414. }
  1415. return 0;
  1416. }
  1417. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1418. struct snd_soc_dai *dai)
  1419. {
  1420. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1421. struct snd_soc_device *socdev = rtd->socdev;
  1422. struct snd_soc_codec *codec = socdev->card->codec;
  1423. struct twl4030_priv *twl4030 = codec->private_data;
  1424. if (twl4030->master_substream == substream)
  1425. twl4030->master_substream = twl4030->slave_substream;
  1426. twl4030->slave_substream = NULL;
  1427. /* If all streams are closed, or the remaining stream has not yet
  1428. * been configured than set the DAI as not configured. */
  1429. if (!twl4030->master_substream)
  1430. twl4030->configured = 0;
  1431. else if (!twl4030->master_substream->runtime->channels)
  1432. twl4030->configured = 0;
  1433. /* If the closing substream had 4 channel, do the necessary cleanup */
  1434. if (substream->runtime->channels == 4)
  1435. twl4030_tdm_enable(codec, substream->stream, 0);
  1436. }
  1437. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1438. struct snd_pcm_hw_params *params,
  1439. struct snd_soc_dai *dai)
  1440. {
  1441. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1442. struct snd_soc_device *socdev = rtd->socdev;
  1443. struct snd_soc_codec *codec = socdev->card->codec;
  1444. struct twl4030_priv *twl4030 = codec->private_data;
  1445. u8 mode, old_mode, format, old_format;
  1446. /* If the substream has 4 channel, do the necessary setup */
  1447. if (params_channels(params) == 4) {
  1448. format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1449. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  1450. /* Safety check: are we in the correct operating mode and
  1451. * the interface is in TDM mode? */
  1452. if ((mode & TWL4030_OPTION_1) &&
  1453. ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
  1454. twl4030_tdm_enable(codec, substream->stream, 1);
  1455. else
  1456. return -EINVAL;
  1457. }
  1458. if (twl4030->configured)
  1459. /* Ignoring hw_params for already configured DAI */
  1460. return 0;
  1461. /* bit rate */
  1462. old_mode = twl4030_read_reg_cache(codec,
  1463. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1464. mode = old_mode & ~TWL4030_APLL_RATE;
  1465. switch (params_rate(params)) {
  1466. case 8000:
  1467. mode |= TWL4030_APLL_RATE_8000;
  1468. break;
  1469. case 11025:
  1470. mode |= TWL4030_APLL_RATE_11025;
  1471. break;
  1472. case 12000:
  1473. mode |= TWL4030_APLL_RATE_12000;
  1474. break;
  1475. case 16000:
  1476. mode |= TWL4030_APLL_RATE_16000;
  1477. break;
  1478. case 22050:
  1479. mode |= TWL4030_APLL_RATE_22050;
  1480. break;
  1481. case 24000:
  1482. mode |= TWL4030_APLL_RATE_24000;
  1483. break;
  1484. case 32000:
  1485. mode |= TWL4030_APLL_RATE_32000;
  1486. break;
  1487. case 44100:
  1488. mode |= TWL4030_APLL_RATE_44100;
  1489. break;
  1490. case 48000:
  1491. mode |= TWL4030_APLL_RATE_48000;
  1492. break;
  1493. case 96000:
  1494. mode |= TWL4030_APLL_RATE_96000;
  1495. break;
  1496. default:
  1497. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1498. params_rate(params));
  1499. return -EINVAL;
  1500. }
  1501. if (mode != old_mode) {
  1502. /* change rate and set CODECPDZ */
  1503. twl4030_codec_enable(codec, 0);
  1504. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1505. twl4030_codec_enable(codec, 1);
  1506. }
  1507. /* sample size */
  1508. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1509. format = old_format;
  1510. format &= ~TWL4030_DATA_WIDTH;
  1511. switch (params_format(params)) {
  1512. case SNDRV_PCM_FORMAT_S16_LE:
  1513. format |= TWL4030_DATA_WIDTH_16S_16W;
  1514. break;
  1515. case SNDRV_PCM_FORMAT_S24_LE:
  1516. format |= TWL4030_DATA_WIDTH_32S_24W;
  1517. break;
  1518. default:
  1519. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1520. params_format(params));
  1521. return -EINVAL;
  1522. }
  1523. if (format != old_format) {
  1524. /* clear CODECPDZ before changing format (codec requirement) */
  1525. twl4030_codec_enable(codec, 0);
  1526. /* change format */
  1527. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1528. /* set CODECPDZ afterwards */
  1529. twl4030_codec_enable(codec, 1);
  1530. }
  1531. /* Store the important parameters for the DAI configuration and set
  1532. * the DAI as configured */
  1533. twl4030->configured = 1;
  1534. twl4030->rate = params_rate(params);
  1535. twl4030->sample_bits = hw_param_interval(params,
  1536. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1537. twl4030->channels = params_channels(params);
  1538. /* If both playback and capture streams are open, and one of them
  1539. * is setting the hw parameters right now (since we are here), set
  1540. * constraints to the other stream to match the current one. */
  1541. if (twl4030->slave_substream)
  1542. twl4030_constraints(twl4030, substream);
  1543. return 0;
  1544. }
  1545. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1546. int clk_id, unsigned int freq, int dir)
  1547. {
  1548. struct snd_soc_codec *codec = codec_dai->codec;
  1549. struct twl4030_priv *twl4030 = codec->private_data;
  1550. u8 infreq;
  1551. switch (freq) {
  1552. case 19200000:
  1553. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1554. twl4030->sysclk = 19200;
  1555. break;
  1556. case 26000000:
  1557. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1558. twl4030->sysclk = 26000;
  1559. break;
  1560. case 38400000:
  1561. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1562. twl4030->sysclk = 38400;
  1563. break;
  1564. default:
  1565. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1566. freq);
  1567. return -EINVAL;
  1568. }
  1569. infreq |= TWL4030_APLL_EN;
  1570. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1571. return 0;
  1572. }
  1573. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1574. unsigned int fmt)
  1575. {
  1576. struct snd_soc_codec *codec = codec_dai->codec;
  1577. u8 old_format, format;
  1578. /* get format */
  1579. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1580. format = old_format;
  1581. /* set master/slave audio interface */
  1582. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1583. case SND_SOC_DAIFMT_CBM_CFM:
  1584. format &= ~(TWL4030_AIF_SLAVE_EN);
  1585. format &= ~(TWL4030_CLK256FS_EN);
  1586. break;
  1587. case SND_SOC_DAIFMT_CBS_CFS:
  1588. format |= TWL4030_AIF_SLAVE_EN;
  1589. format |= TWL4030_CLK256FS_EN;
  1590. break;
  1591. default:
  1592. return -EINVAL;
  1593. }
  1594. /* interface format */
  1595. format &= ~TWL4030_AIF_FORMAT;
  1596. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1597. case SND_SOC_DAIFMT_I2S:
  1598. format |= TWL4030_AIF_FORMAT_CODEC;
  1599. break;
  1600. case SND_SOC_DAIFMT_DSP_A:
  1601. format |= TWL4030_AIF_FORMAT_TDM;
  1602. break;
  1603. default:
  1604. return -EINVAL;
  1605. }
  1606. if (format != old_format) {
  1607. /* clear CODECPDZ before changing format (codec requirement) */
  1608. twl4030_codec_enable(codec, 0);
  1609. /* change format */
  1610. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1611. /* set CODECPDZ afterwards */
  1612. twl4030_codec_enable(codec, 1);
  1613. }
  1614. return 0;
  1615. }
  1616. static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
  1617. {
  1618. struct snd_soc_codec *codec = dai->codec;
  1619. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1620. if (tristate)
  1621. reg |= TWL4030_AIF_TRI_EN;
  1622. else
  1623. reg &= ~TWL4030_AIF_TRI_EN;
  1624. return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
  1625. }
  1626. /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
  1627. * (VTXL, VTXR) for uplink has to be enabled/disabled. */
  1628. static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
  1629. int enable)
  1630. {
  1631. u8 reg, mask;
  1632. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1633. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1634. mask = TWL4030_ARXL1_VRX_EN;
  1635. else
  1636. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1637. if (enable)
  1638. reg |= mask;
  1639. else
  1640. reg &= ~mask;
  1641. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1642. }
  1643. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1644. struct snd_soc_dai *dai)
  1645. {
  1646. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1647. struct snd_soc_device *socdev = rtd->socdev;
  1648. struct snd_soc_codec *codec = socdev->card->codec;
  1649. u8 infreq;
  1650. u8 mode;
  1651. /* If the system master clock is not 26MHz, the voice PCM interface is
  1652. * not avilable.
  1653. */
  1654. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1655. & TWL4030_APLL_INFREQ;
  1656. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1657. printk(KERN_ERR "TWL4030 voice startup: "
  1658. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1659. return -EINVAL;
  1660. }
  1661. /* If the codec mode is not option2, the voice PCM interface is not
  1662. * avilable.
  1663. */
  1664. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1665. & TWL4030_OPT_MODE;
  1666. if (mode != TWL4030_OPTION_2) {
  1667. printk(KERN_ERR "TWL4030 voice startup: "
  1668. "the codec mode is not option2\n");
  1669. return -EINVAL;
  1670. }
  1671. return 0;
  1672. }
  1673. static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
  1674. struct snd_soc_dai *dai)
  1675. {
  1676. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1677. struct snd_soc_device *socdev = rtd->socdev;
  1678. struct snd_soc_codec *codec = socdev->card->codec;
  1679. /* Enable voice digital filters */
  1680. twl4030_voice_enable(codec, substream->stream, 0);
  1681. }
  1682. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1683. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1684. {
  1685. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1686. struct snd_soc_device *socdev = rtd->socdev;
  1687. struct snd_soc_codec *codec = socdev->card->codec;
  1688. u8 old_mode, mode;
  1689. /* Enable voice digital filters */
  1690. twl4030_voice_enable(codec, substream->stream, 1);
  1691. /* bit rate */
  1692. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1693. & ~(TWL4030_CODECPDZ);
  1694. mode = old_mode;
  1695. switch (params_rate(params)) {
  1696. case 8000:
  1697. mode &= ~(TWL4030_SEL_16K);
  1698. break;
  1699. case 16000:
  1700. mode |= TWL4030_SEL_16K;
  1701. break;
  1702. default:
  1703. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1704. params_rate(params));
  1705. return -EINVAL;
  1706. }
  1707. if (mode != old_mode) {
  1708. /* change rate and set CODECPDZ */
  1709. twl4030_codec_enable(codec, 0);
  1710. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1711. twl4030_codec_enable(codec, 1);
  1712. }
  1713. return 0;
  1714. }
  1715. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1716. int clk_id, unsigned int freq, int dir)
  1717. {
  1718. struct snd_soc_codec *codec = codec_dai->codec;
  1719. u8 infreq;
  1720. switch (freq) {
  1721. case 26000000:
  1722. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1723. break;
  1724. default:
  1725. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1726. freq);
  1727. return -EINVAL;
  1728. }
  1729. infreq |= TWL4030_APLL_EN;
  1730. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1731. return 0;
  1732. }
  1733. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1734. unsigned int fmt)
  1735. {
  1736. struct snd_soc_codec *codec = codec_dai->codec;
  1737. u8 old_format, format;
  1738. /* get format */
  1739. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1740. format = old_format;
  1741. /* set master/slave audio interface */
  1742. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1743. case SND_SOC_DAIFMT_CBM_CFM:
  1744. format &= ~(TWL4030_VIF_SLAVE_EN);
  1745. break;
  1746. case SND_SOC_DAIFMT_CBS_CFS:
  1747. format |= TWL4030_VIF_SLAVE_EN;
  1748. break;
  1749. default:
  1750. return -EINVAL;
  1751. }
  1752. /* clock inversion */
  1753. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1754. case SND_SOC_DAIFMT_IB_NF:
  1755. format &= ~(TWL4030_VIF_FORMAT);
  1756. break;
  1757. case SND_SOC_DAIFMT_NB_IF:
  1758. format |= TWL4030_VIF_FORMAT;
  1759. break;
  1760. default:
  1761. return -EINVAL;
  1762. }
  1763. if (format != old_format) {
  1764. /* change format and set CODECPDZ */
  1765. twl4030_codec_enable(codec, 0);
  1766. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1767. twl4030_codec_enable(codec, 1);
  1768. }
  1769. return 0;
  1770. }
  1771. static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
  1772. {
  1773. struct snd_soc_codec *codec = dai->codec;
  1774. u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1775. if (tristate)
  1776. reg |= TWL4030_VIF_TRI_EN;
  1777. else
  1778. reg &= ~TWL4030_VIF_TRI_EN;
  1779. return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
  1780. }
  1781. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1782. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1783. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1784. .startup = twl4030_startup,
  1785. .shutdown = twl4030_shutdown,
  1786. .hw_params = twl4030_hw_params,
  1787. .set_sysclk = twl4030_set_dai_sysclk,
  1788. .set_fmt = twl4030_set_dai_fmt,
  1789. .set_tristate = twl4030_set_tristate,
  1790. };
  1791. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1792. .startup = twl4030_voice_startup,
  1793. .shutdown = twl4030_voice_shutdown,
  1794. .hw_params = twl4030_voice_hw_params,
  1795. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1796. .set_fmt = twl4030_voice_set_dai_fmt,
  1797. .set_tristate = twl4030_voice_set_tristate,
  1798. };
  1799. struct snd_soc_dai twl4030_dai[] = {
  1800. {
  1801. .name = "twl4030",
  1802. .playback = {
  1803. .stream_name = "HiFi Playback",
  1804. .channels_min = 2,
  1805. .channels_max = 4,
  1806. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1807. .formats = TWL4030_FORMATS,},
  1808. .capture = {
  1809. .stream_name = "Capture",
  1810. .channels_min = 2,
  1811. .channels_max = 4,
  1812. .rates = TWL4030_RATES,
  1813. .formats = TWL4030_FORMATS,},
  1814. .ops = &twl4030_dai_ops,
  1815. },
  1816. {
  1817. .name = "twl4030 Voice",
  1818. .playback = {
  1819. .stream_name = "Voice Playback",
  1820. .channels_min = 1,
  1821. .channels_max = 1,
  1822. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1823. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1824. .capture = {
  1825. .stream_name = "Capture",
  1826. .channels_min = 1,
  1827. .channels_max = 2,
  1828. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1829. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1830. .ops = &twl4030_dai_voice_ops,
  1831. },
  1832. };
  1833. EXPORT_SYMBOL_GPL(twl4030_dai);
  1834. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1835. {
  1836. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1837. struct snd_soc_codec *codec = socdev->card->codec;
  1838. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1839. return 0;
  1840. }
  1841. static int twl4030_resume(struct platform_device *pdev)
  1842. {
  1843. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1844. struct snd_soc_codec *codec = socdev->card->codec;
  1845. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1846. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1847. return 0;
  1848. }
  1849. /*
  1850. * initialize the driver
  1851. * register the mixer and dsp interfaces with the kernel
  1852. */
  1853. static int twl4030_init(struct snd_soc_device *socdev)
  1854. {
  1855. struct snd_soc_codec *codec = socdev->card->codec;
  1856. struct twl4030_setup_data *setup = socdev->codec_data;
  1857. struct twl4030_priv *twl4030 = codec->private_data;
  1858. int ret = 0;
  1859. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1860. codec->name = "twl4030";
  1861. codec->owner = THIS_MODULE;
  1862. codec->read = twl4030_read_reg_cache;
  1863. codec->write = twl4030_write;
  1864. codec->set_bias_level = twl4030_set_bias_level;
  1865. codec->dai = twl4030_dai;
  1866. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1867. codec->reg_cache_size = sizeof(twl4030_reg);
  1868. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1869. GFP_KERNEL);
  1870. if (codec->reg_cache == NULL)
  1871. return -ENOMEM;
  1872. /* Configuration for headset ramp delay from setup data */
  1873. if (setup) {
  1874. unsigned char hs_pop;
  1875. if (setup->sysclk)
  1876. twl4030->sysclk = setup->sysclk;
  1877. else
  1878. twl4030->sysclk = 26000;
  1879. hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  1880. hs_pop &= ~TWL4030_RAMP_DELAY;
  1881. hs_pop |= (setup->ramp_delay_value << 2);
  1882. twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  1883. } else {
  1884. twl4030->sysclk = 26000;
  1885. }
  1886. /* register pcms */
  1887. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1888. if (ret < 0) {
  1889. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1890. goto pcm_err;
  1891. }
  1892. twl4030_init_chip(codec);
  1893. /* power on device */
  1894. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1895. snd_soc_add_controls(codec, twl4030_snd_controls,
  1896. ARRAY_SIZE(twl4030_snd_controls));
  1897. twl4030_add_widgets(codec);
  1898. ret = snd_soc_init_card(socdev);
  1899. if (ret < 0) {
  1900. printk(KERN_ERR "twl4030: failed to register card\n");
  1901. goto card_err;
  1902. }
  1903. return ret;
  1904. card_err:
  1905. snd_soc_free_pcms(socdev);
  1906. snd_soc_dapm_free(socdev);
  1907. pcm_err:
  1908. kfree(codec->reg_cache);
  1909. return ret;
  1910. }
  1911. static struct snd_soc_device *twl4030_socdev;
  1912. static int twl4030_probe(struct platform_device *pdev)
  1913. {
  1914. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1915. struct snd_soc_codec *codec;
  1916. struct twl4030_priv *twl4030;
  1917. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1918. if (codec == NULL)
  1919. return -ENOMEM;
  1920. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1921. if (twl4030 == NULL) {
  1922. kfree(codec);
  1923. return -ENOMEM;
  1924. }
  1925. codec->private_data = twl4030;
  1926. socdev->card->codec = codec;
  1927. mutex_init(&codec->mutex);
  1928. INIT_LIST_HEAD(&codec->dapm_widgets);
  1929. INIT_LIST_HEAD(&codec->dapm_paths);
  1930. twl4030_socdev = socdev;
  1931. twl4030_init(socdev);
  1932. return 0;
  1933. }
  1934. static int twl4030_remove(struct platform_device *pdev)
  1935. {
  1936. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1937. struct snd_soc_codec *codec = socdev->card->codec;
  1938. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1939. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1940. snd_soc_free_pcms(socdev);
  1941. snd_soc_dapm_free(socdev);
  1942. kfree(codec->private_data);
  1943. kfree(codec);
  1944. return 0;
  1945. }
  1946. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1947. .probe = twl4030_probe,
  1948. .remove = twl4030_remove,
  1949. .suspend = twl4030_suspend,
  1950. .resume = twl4030_resume,
  1951. };
  1952. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1953. static int __init twl4030_modinit(void)
  1954. {
  1955. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1956. }
  1957. module_init(twl4030_modinit);
  1958. static void __exit twl4030_exit(void)
  1959. {
  1960. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1961. }
  1962. module_exit(twl4030_exit);
  1963. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1964. MODULE_AUTHOR("Steve Sakoman");
  1965. MODULE_LICENSE("GPL");