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drivers
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ath9k
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phy.h

phy.h 2.0 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2008-2009 Atheros Communications Inc.
    3. 

  3.  *
    4. 

  4.  * Permission to use, copy, modify, and/or distribute this software for any
    5. 

  5.  * purpose with or without fee is hereby granted, provided that the above
    6. 

  6.  * copyright notice and this permission notice appear in all copies.
    7. 

  7.  *
    8. 

  8.  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
    9. 

  9.  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
    10. 

  10.  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
    11. 

  11.  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
    12. 

  12.  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
    13. 

  13.  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
    14. 

  14.  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
    15. 

  15.  */
    16. 

  16. 

  17. #ifndef PHY_H
    18. 

  18. #define PHY_H
    19. 

  19. 

  20. #define AR_PHY_BASE     0x9800
    21. 

  21. #define AR_PHY(_n)      (AR_PHY_BASE + ((_n)<<2))
    22. 

  22. 

  23. #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX   0x0007E000
    24. 

  24. #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
    25. 

  25. #define AR_PHY_TX_GAIN_CLC       0x0000001E
    26. 

  26. #define AR_PHY_TX_GAIN_CLC_S     1
    27. 

  27. #define AR_PHY_TX_GAIN           0x0007F000
    28. 

  28. #define AR_PHY_TX_GAIN_S         12
    29. 

  29. 

  30. #define AR_PHY_CLC_TBL1      0xa35c
    31. 

  31. #define AR_PHY_CLC_I0        0x07ff0000
    32. 

  32. #define AR_PHY_CLC_I0_S      16
    33. 

  33. #define AR_PHY_CLC_Q0        0x0000ffd0
    34. 

  34. #define AR_PHY_CLC_Q0_S      5
    35. 

  35. 

  36. #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
    37. 

  37. 		int r;							\
    38. 

  38. 		for (r = 0; r < ((iniarray)->ia_rows); r++) {		\
    39. 

  39. 			REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
    40. 

  40. 			DO_DELAY(regWr);				\
    41. 

  41. 		}							\
    42. 

  42. 	} while (0)
    43. 

  43. 

  44. #define ATH9K_IS_MIC_ENABLED(ah)					\
    45. 

  45. 	((ah)->sta_id1_defaults & AR_STA_ID1_CRPT_MIC_ENABLE)
    46. 

  46. 

  47. #define ANTSWAP_AB 0x0001
    48. 

  48. #define REDUCE_CHAIN_0 0x00000050
    49. 

  49. #define REDUCE_CHAIN_1 0x00000051
    50. 

  50. #define AR_PHY_CHIP_ID 0x9818
    51. 

  51. 

  52. #define RF_BANK_SETUP(_bank, _iniarray, _col) do {			\
    53. 

  53. 		int i;							\
    54. 

  54. 		for (i = 0; i < (_iniarray)->ia_rows; i++)		\
    55. 

  55. 			(_bank)[i] = INI_RA((_iniarray), i, _col);;	\
    56. 

  56. 	} while (0)
    57. 

  57. 

  58. #endif
    59.