jedec_probe.c 55 KB

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  1. /*
  2. Common Flash Interface probe code.
  3. (C) 2000 Red Hat. GPL'd.
  4. $Id: jedec_probe.c,v 1.66 2005/11/07 11:14:23 gleixner Exp $
  5. See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
  6. for the standard this probe goes back to.
  7. Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
  8. */
  9. #include <linux/module.h>
  10. #include <linux/init.h>
  11. #include <linux/types.h>
  12. #include <linux/kernel.h>
  13. #include <asm/io.h>
  14. #include <asm/byteorder.h>
  15. #include <linux/errno.h>
  16. #include <linux/slab.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/mtd/mtd.h>
  19. #include <linux/mtd/map.h>
  20. #include <linux/mtd/cfi.h>
  21. #include <linux/mtd/gen_probe.h>
  22. /* Manufacturers */
  23. #define MANUFACTURER_AMD 0x0001
  24. #define MANUFACTURER_ATMEL 0x001f
  25. #define MANUFACTURER_FUJITSU 0x0004
  26. #define MANUFACTURER_HYUNDAI 0x00AD
  27. #define MANUFACTURER_INTEL 0x0089
  28. #define MANUFACTURER_MACRONIX 0x00C2
  29. #define MANUFACTURER_NEC 0x0010
  30. #define MANUFACTURER_PMC 0x009D
  31. #define MANUFACTURER_SHARP 0x00b0
  32. #define MANUFACTURER_SST 0x00BF
  33. #define MANUFACTURER_ST 0x0020
  34. #define MANUFACTURER_TOSHIBA 0x0098
  35. #define MANUFACTURER_WINBOND 0x00da
  36. /* AMD */
  37. #define AM29DL800BB 0x22C8
  38. #define AM29DL800BT 0x224A
  39. #define AM29F800BB 0x2258
  40. #define AM29F800BT 0x22D6
  41. #define AM29LV400BB 0x22BA
  42. #define AM29LV400BT 0x22B9
  43. #define AM29LV800BB 0x225B
  44. #define AM29LV800BT 0x22DA
  45. #define AM29LV160DT 0x22C4
  46. #define AM29LV160DB 0x2249
  47. #define AM29F017D 0x003D
  48. #define AM29F016D 0x00AD
  49. #define AM29F080 0x00D5
  50. #define AM29F040 0x00A4
  51. #define AM29LV040B 0x004F
  52. #define AM29F032B 0x0041
  53. #define AM29F002T 0x00B0
  54. #define AM29SL800DB 0x226B
  55. #define AM29SL800DT 0x22EA
  56. /* Atmel */
  57. #define AT49BV512 0x0003
  58. #define AT29LV512 0x003d
  59. #define AT49BV16X 0x00C0
  60. #define AT49BV16XT 0x00C2
  61. #define AT49BV32X 0x00C8
  62. #define AT49BV32XT 0x00C9
  63. /* Fujitsu */
  64. #define MBM29F040C 0x00A4
  65. #define MBM29F800BA 0x2258
  66. #define MBM29LV650UE 0x22D7
  67. #define MBM29LV320TE 0x22F6
  68. #define MBM29LV320BE 0x22F9
  69. #define MBM29LV160TE 0x22C4
  70. #define MBM29LV160BE 0x2249
  71. #define MBM29LV800BA 0x225B
  72. #define MBM29LV800TA 0x22DA
  73. #define MBM29LV400TC 0x22B9
  74. #define MBM29LV400BC 0x22BA
  75. /* Hyundai */
  76. #define HY29F002T 0x00B0
  77. /* Intel */
  78. #define I28F004B3T 0x00d4
  79. #define I28F004B3B 0x00d5
  80. #define I28F400B3T 0x8894
  81. #define I28F400B3B 0x8895
  82. #define I28F008S5 0x00a6
  83. #define I28F016S5 0x00a0
  84. #define I28F008SA 0x00a2
  85. #define I28F008B3T 0x00d2
  86. #define I28F008B3B 0x00d3
  87. #define I28F800B3T 0x8892
  88. #define I28F800B3B 0x8893
  89. #define I28F016S3 0x00aa
  90. #define I28F016B3T 0x00d0
  91. #define I28F016B3B 0x00d1
  92. #define I28F160B3T 0x8890
  93. #define I28F160B3B 0x8891
  94. #define I28F320B3T 0x8896
  95. #define I28F320B3B 0x8897
  96. #define I28F640B3T 0x8898
  97. #define I28F640B3B 0x8899
  98. #define I82802AB 0x00ad
  99. #define I82802AC 0x00ac
  100. /* Macronix */
  101. #define MX29LV040C 0x004F
  102. #define MX29LV160T 0x22C4
  103. #define MX29LV160B 0x2249
  104. #define MX29F040 0x00A4
  105. #define MX29F016 0x00AD
  106. #define MX29F002T 0x00B0
  107. #define MX29F004T 0x0045
  108. #define MX29F004B 0x0046
  109. /* NEC */
  110. #define UPD29F064115 0x221C
  111. /* PMC */
  112. #define PM49FL002 0x006D
  113. #define PM49FL004 0x006E
  114. #define PM49FL008 0x006A
  115. /* Sharp */
  116. #define LH28F640BF 0x00b0
  117. /* ST - www.st.com */
  118. #define M29F800AB 0x0058
  119. #define M29W800DT 0x00D7
  120. #define M29W800DB 0x005B
  121. #define M29W400DT 0x00EE
  122. #define M29W400DB 0x00EF
  123. #define M29W160DT 0x22C4
  124. #define M29W160DB 0x2249
  125. #define M29W040B 0x00E3
  126. #define M50FW040 0x002C
  127. #define M50FW080 0x002D
  128. #define M50FW016 0x002E
  129. #define M50LPW080 0x002F
  130. #define M50FLW080A 0x0080
  131. #define M50FLW080B 0x0081
  132. /* SST */
  133. #define SST29EE020 0x0010
  134. #define SST29LE020 0x0012
  135. #define SST29EE512 0x005d
  136. #define SST29LE512 0x003d
  137. #define SST39LF800 0x2781
  138. #define SST39LF160 0x2782
  139. #define SST39VF1601 0x234b
  140. #define SST39LF512 0x00D4
  141. #define SST39LF010 0x00D5
  142. #define SST39LF020 0x00D6
  143. #define SST39LF040 0x00D7
  144. #define SST39SF010A 0x00B5
  145. #define SST39SF020A 0x00B6
  146. #define SST49LF004B 0x0060
  147. #define SST49LF040B 0x0050
  148. #define SST49LF008A 0x005a
  149. #define SST49LF030A 0x001C
  150. #define SST49LF040A 0x0051
  151. #define SST49LF080A 0x005B
  152. #define SST36VF3203 0x7354
  153. /* Toshiba */
  154. #define TC58FVT160 0x00C2
  155. #define TC58FVB160 0x0043
  156. #define TC58FVT321 0x009A
  157. #define TC58FVB321 0x009C
  158. #define TC58FVT641 0x0093
  159. #define TC58FVB641 0x0095
  160. /* Winbond */
  161. #define W49V002A 0x00b0
  162. /*
  163. * Unlock address sets for AMD command sets.
  164. * Intel command sets use the MTD_UADDR_UNNECESSARY.
  165. * Each identifier, except MTD_UADDR_UNNECESSARY, and
  166. * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
  167. * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
  168. * initialization need not require initializing all of the
  169. * unlock addresses for all bit widths.
  170. */
  171. enum uaddr {
  172. MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
  173. MTD_UADDR_0x0555_0x02AA,
  174. MTD_UADDR_0x0555_0x0AAA,
  175. MTD_UADDR_0x5555_0x2AAA,
  176. MTD_UADDR_0x0AAA_0x0555,
  177. MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
  178. MTD_UADDR_UNNECESSARY, /* Does not require any address */
  179. };
  180. struct unlock_addr {
  181. uint32_t addr1;
  182. uint32_t addr2;
  183. };
  184. /*
  185. * I don't like the fact that the first entry in unlock_addrs[]
  186. * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
  187. * should not be used. The problem is that structures with
  188. * initializers have extra fields initialized to 0. It is _very_
  189. * desireable to have the unlock address entries for unsupported
  190. * data widths automatically initialized - that means that
  191. * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
  192. * must go unused.
  193. */
  194. static const struct unlock_addr unlock_addrs[] = {
  195. [MTD_UADDR_NOT_SUPPORTED] = {
  196. .addr1 = 0xffff,
  197. .addr2 = 0xffff
  198. },
  199. [MTD_UADDR_0x0555_0x02AA] = {
  200. .addr1 = 0x0555,
  201. .addr2 = 0x02aa
  202. },
  203. [MTD_UADDR_0x0555_0x0AAA] = {
  204. .addr1 = 0x0555,
  205. .addr2 = 0x0aaa
  206. },
  207. [MTD_UADDR_0x5555_0x2AAA] = {
  208. .addr1 = 0x5555,
  209. .addr2 = 0x2aaa
  210. },
  211. [MTD_UADDR_0x0AAA_0x0555] = {
  212. .addr1 = 0x0AAA,
  213. .addr2 = 0x0555
  214. },
  215. [MTD_UADDR_DONT_CARE] = {
  216. .addr1 = 0x0000, /* Doesn't matter which address */
  217. .addr2 = 0x0000 /* is used - must be last entry */
  218. },
  219. [MTD_UADDR_UNNECESSARY] = {
  220. .addr1 = 0x0000,
  221. .addr2 = 0x0000
  222. }
  223. };
  224. struct amd_flash_info {
  225. const char *name;
  226. const uint16_t mfr_id;
  227. const uint16_t dev_id;
  228. const uint8_t dev_size;
  229. const uint8_t nr_regions;
  230. const uint16_t cmd_set;
  231. const uint32_t regions[6];
  232. const uint8_t devtypes; /* Bitmask for x8, x16 etc. */
  233. const uint8_t uaddr; /* unlock addrs for 8, 16, 32, 64 */
  234. };
  235. #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
  236. #define SIZE_64KiB 16
  237. #define SIZE_128KiB 17
  238. #define SIZE_256KiB 18
  239. #define SIZE_512KiB 19
  240. #define SIZE_1MiB 20
  241. #define SIZE_2MiB 21
  242. #define SIZE_4MiB 22
  243. #define SIZE_8MiB 23
  244. /*
  245. * Please keep this list ordered by manufacturer!
  246. * Fortunately, the list isn't searched often and so a
  247. * slow, linear search isn't so bad.
  248. */
  249. static const struct amd_flash_info jedec_table[] = {
  250. {
  251. .mfr_id = MANUFACTURER_AMD,
  252. .dev_id = AM29F032B,
  253. .name = "AMD AM29F032B",
  254. .uaddr = MTD_UADDR_0x0555_0x02AA,
  255. .devtypes = CFI_DEVICETYPE_X8,
  256. .dev_size = SIZE_4MiB,
  257. .cmd_set = P_ID_AMD_STD,
  258. .nr_regions = 1,
  259. .regions = {
  260. ERASEINFO(0x10000,64)
  261. }
  262. }, {
  263. .mfr_id = MANUFACTURER_AMD,
  264. .dev_id = AM29LV160DT,
  265. .name = "AMD AM29LV160DT",
  266. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  267. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  268. .dev_size = SIZE_2MiB,
  269. .cmd_set = P_ID_AMD_STD,
  270. .nr_regions = 4,
  271. .regions = {
  272. ERASEINFO(0x10000,31),
  273. ERASEINFO(0x08000,1),
  274. ERASEINFO(0x02000,2),
  275. ERASEINFO(0x04000,1)
  276. }
  277. }, {
  278. .mfr_id = MANUFACTURER_AMD,
  279. .dev_id = AM29LV160DB,
  280. .name = "AMD AM29LV160DB",
  281. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  282. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  283. .dev_size = SIZE_2MiB,
  284. .cmd_set = P_ID_AMD_STD,
  285. .nr_regions = 4,
  286. .regions = {
  287. ERASEINFO(0x04000,1),
  288. ERASEINFO(0x02000,2),
  289. ERASEINFO(0x08000,1),
  290. ERASEINFO(0x10000,31)
  291. }
  292. }, {
  293. .mfr_id = MANUFACTURER_AMD,
  294. .dev_id = AM29LV400BB,
  295. .name = "AMD AM29LV400BB",
  296. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  297. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  298. .dev_size = SIZE_512KiB,
  299. .cmd_set = P_ID_AMD_STD,
  300. .nr_regions = 4,
  301. .regions = {
  302. ERASEINFO(0x04000,1),
  303. ERASEINFO(0x02000,2),
  304. ERASEINFO(0x08000,1),
  305. ERASEINFO(0x10000,7)
  306. }
  307. }, {
  308. .mfr_id = MANUFACTURER_AMD,
  309. .dev_id = AM29LV400BT,
  310. .name = "AMD AM29LV400BT",
  311. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  312. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  313. .dev_size = SIZE_512KiB,
  314. .cmd_set = P_ID_AMD_STD,
  315. .nr_regions = 4,
  316. .regions = {
  317. ERASEINFO(0x10000,7),
  318. ERASEINFO(0x08000,1),
  319. ERASEINFO(0x02000,2),
  320. ERASEINFO(0x04000,1)
  321. }
  322. }, {
  323. .mfr_id = MANUFACTURER_AMD,
  324. .dev_id = AM29LV800BB,
  325. .name = "AMD AM29LV800BB",
  326. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  327. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  328. .dev_size = SIZE_1MiB,
  329. .cmd_set = P_ID_AMD_STD,
  330. .nr_regions = 4,
  331. .regions = {
  332. ERASEINFO(0x04000,1),
  333. ERASEINFO(0x02000,2),
  334. ERASEINFO(0x08000,1),
  335. ERASEINFO(0x10000,15),
  336. }
  337. }, {
  338. /* add DL */
  339. .mfr_id = MANUFACTURER_AMD,
  340. .dev_id = AM29DL800BB,
  341. .name = "AMD AM29DL800BB",
  342. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  343. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  344. .dev_size = SIZE_1MiB,
  345. .cmd_set = P_ID_AMD_STD,
  346. .nr_regions = 6,
  347. .regions = {
  348. ERASEINFO(0x04000,1),
  349. ERASEINFO(0x08000,1),
  350. ERASEINFO(0x02000,4),
  351. ERASEINFO(0x08000,1),
  352. ERASEINFO(0x04000,1),
  353. ERASEINFO(0x10000,14)
  354. }
  355. }, {
  356. .mfr_id = MANUFACTURER_AMD,
  357. .dev_id = AM29DL800BT,
  358. .name = "AMD AM29DL800BT",
  359. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  360. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  361. .dev_size = SIZE_1MiB,
  362. .cmd_set = P_ID_AMD_STD,
  363. .nr_regions = 6,
  364. .regions = {
  365. ERASEINFO(0x10000,14),
  366. ERASEINFO(0x04000,1),
  367. ERASEINFO(0x08000,1),
  368. ERASEINFO(0x02000,4),
  369. ERASEINFO(0x08000,1),
  370. ERASEINFO(0x04000,1)
  371. }
  372. }, {
  373. .mfr_id = MANUFACTURER_AMD,
  374. .dev_id = AM29F800BB,
  375. .name = "AMD AM29F800BB",
  376. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  377. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  378. .dev_size = SIZE_1MiB,
  379. .cmd_set = P_ID_AMD_STD,
  380. .nr_regions = 4,
  381. .regions = {
  382. ERASEINFO(0x04000,1),
  383. ERASEINFO(0x02000,2),
  384. ERASEINFO(0x08000,1),
  385. ERASEINFO(0x10000,15),
  386. }
  387. }, {
  388. .mfr_id = MANUFACTURER_AMD,
  389. .dev_id = AM29LV800BT,
  390. .name = "AMD AM29LV800BT",
  391. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  392. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  393. .dev_size = SIZE_1MiB,
  394. .cmd_set = P_ID_AMD_STD,
  395. .nr_regions = 4,
  396. .regions = {
  397. ERASEINFO(0x10000,15),
  398. ERASEINFO(0x08000,1),
  399. ERASEINFO(0x02000,2),
  400. ERASEINFO(0x04000,1)
  401. }
  402. }, {
  403. .mfr_id = MANUFACTURER_AMD,
  404. .dev_id = AM29F800BT,
  405. .name = "AMD AM29F800BT",
  406. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  407. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  408. .dev_size = SIZE_1MiB,
  409. .cmd_set = P_ID_AMD_STD,
  410. .nr_regions = 4,
  411. .regions = {
  412. ERASEINFO(0x10000,15),
  413. ERASEINFO(0x08000,1),
  414. ERASEINFO(0x02000,2),
  415. ERASEINFO(0x04000,1)
  416. }
  417. }, {
  418. .mfr_id = MANUFACTURER_AMD,
  419. .dev_id = AM29F017D,
  420. .name = "AMD AM29F017D",
  421. .devtypes = CFI_DEVICETYPE_X8,
  422. .uaddr = MTD_UADDR_DONT_CARE,
  423. .dev_size = SIZE_2MiB,
  424. .cmd_set = P_ID_AMD_STD,
  425. .nr_regions = 1,
  426. .regions = {
  427. ERASEINFO(0x10000,32),
  428. }
  429. }, {
  430. .mfr_id = MANUFACTURER_AMD,
  431. .dev_id = AM29F016D,
  432. .name = "AMD AM29F016D",
  433. .devtypes = CFI_DEVICETYPE_X8,
  434. .uaddr = MTD_UADDR_0x0555_0x02AA,
  435. .dev_size = SIZE_2MiB,
  436. .cmd_set = P_ID_AMD_STD,
  437. .nr_regions = 1,
  438. .regions = {
  439. ERASEINFO(0x10000,32),
  440. }
  441. }, {
  442. .mfr_id = MANUFACTURER_AMD,
  443. .dev_id = AM29F080,
  444. .name = "AMD AM29F080",
  445. .devtypes = CFI_DEVICETYPE_X8,
  446. .uaddr = MTD_UADDR_0x0555_0x02AA,
  447. .dev_size = SIZE_1MiB,
  448. .cmd_set = P_ID_AMD_STD,
  449. .nr_regions = 1,
  450. .regions = {
  451. ERASEINFO(0x10000,16),
  452. }
  453. }, {
  454. .mfr_id = MANUFACTURER_AMD,
  455. .dev_id = AM29F040,
  456. .name = "AMD AM29F040",
  457. .devtypes = CFI_DEVICETYPE_X8,
  458. .uaddr = MTD_UADDR_0x0555_0x02AA,
  459. .dev_size = SIZE_512KiB,
  460. .cmd_set = P_ID_AMD_STD,
  461. .nr_regions = 1,
  462. .regions = {
  463. ERASEINFO(0x10000,8),
  464. }
  465. }, {
  466. .mfr_id = MANUFACTURER_AMD,
  467. .dev_id = AM29LV040B,
  468. .name = "AMD AM29LV040B",
  469. .devtypes = CFI_DEVICETYPE_X8,
  470. .uaddr = MTD_UADDR_0x0555_0x02AA,
  471. .dev_size = SIZE_512KiB,
  472. .cmd_set = P_ID_AMD_STD,
  473. .nr_regions = 1,
  474. .regions = {
  475. ERASEINFO(0x10000,8),
  476. }
  477. }, {
  478. .mfr_id = MANUFACTURER_AMD,
  479. .dev_id = AM29F002T,
  480. .name = "AMD AM29F002T",
  481. .devtypes = CFI_DEVICETYPE_X8,
  482. .uaddr = MTD_UADDR_0x0555_0x02AA,
  483. .dev_size = SIZE_256KiB,
  484. .cmd_set = P_ID_AMD_STD,
  485. .nr_regions = 4,
  486. .regions = {
  487. ERASEINFO(0x10000,3),
  488. ERASEINFO(0x08000,1),
  489. ERASEINFO(0x02000,2),
  490. ERASEINFO(0x04000,1),
  491. }
  492. }, {
  493. .mfr_id = MANUFACTURER_AMD,
  494. .dev_id = AM29SL800DT,
  495. .name = "AMD AM29SL800DT",
  496. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  497. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  498. .dev_size = SIZE_1MiB,
  499. .cmd_set = P_ID_AMD_STD,
  500. .nr_regions = 4,
  501. .regions = {
  502. ERASEINFO(0x10000,15),
  503. ERASEINFO(0x08000,1),
  504. ERASEINFO(0x02000,2),
  505. ERASEINFO(0x04000,1),
  506. }
  507. }, {
  508. .mfr_id = MANUFACTURER_AMD,
  509. .dev_id = AM29SL800DB,
  510. .name = "AMD AM29SL800DB",
  511. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  512. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  513. .dev_size = SIZE_1MiB,
  514. .cmd_set = P_ID_AMD_STD,
  515. .nr_regions = 4,
  516. .regions = {
  517. ERASEINFO(0x04000,1),
  518. ERASEINFO(0x02000,2),
  519. ERASEINFO(0x08000,1),
  520. ERASEINFO(0x10000,15),
  521. }
  522. }, {
  523. .mfr_id = MANUFACTURER_ATMEL,
  524. .dev_id = AT49BV512,
  525. .name = "Atmel AT49BV512",
  526. .devtypes = CFI_DEVICETYPE_X8,
  527. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  528. .dev_size = SIZE_64KiB,
  529. .cmd_set = P_ID_AMD_STD,
  530. .nr_regions = 1,
  531. .regions = {
  532. ERASEINFO(0x10000,1)
  533. }
  534. }, {
  535. .mfr_id = MANUFACTURER_ATMEL,
  536. .dev_id = AT29LV512,
  537. .name = "Atmel AT29LV512",
  538. .devtypes = CFI_DEVICETYPE_X8,
  539. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  540. .dev_size = SIZE_64KiB,
  541. .cmd_set = P_ID_AMD_STD,
  542. .nr_regions = 1,
  543. .regions = {
  544. ERASEINFO(0x80,256),
  545. ERASEINFO(0x80,256)
  546. }
  547. }, {
  548. .mfr_id = MANUFACTURER_ATMEL,
  549. .dev_id = AT49BV16X,
  550. .name = "Atmel AT49BV16X",
  551. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  552. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  553. .dev_size = SIZE_2MiB,
  554. .cmd_set = P_ID_AMD_STD,
  555. .nr_regions = 2,
  556. .regions = {
  557. ERASEINFO(0x02000,8),
  558. ERASEINFO(0x10000,31)
  559. }
  560. }, {
  561. .mfr_id = MANUFACTURER_ATMEL,
  562. .dev_id = AT49BV16XT,
  563. .name = "Atmel AT49BV16XT",
  564. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  565. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  566. .dev_size = SIZE_2MiB,
  567. .cmd_set = P_ID_AMD_STD,
  568. .nr_regions = 2,
  569. .regions = {
  570. ERASEINFO(0x10000,31),
  571. ERASEINFO(0x02000,8)
  572. }
  573. }, {
  574. .mfr_id = MANUFACTURER_ATMEL,
  575. .dev_id = AT49BV32X,
  576. .name = "Atmel AT49BV32X",
  577. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  578. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  579. .dev_size = SIZE_4MiB,
  580. .cmd_set = P_ID_AMD_STD,
  581. .nr_regions = 2,
  582. .regions = {
  583. ERASEINFO(0x02000,8),
  584. ERASEINFO(0x10000,63)
  585. }
  586. }, {
  587. .mfr_id = MANUFACTURER_ATMEL,
  588. .dev_id = AT49BV32XT,
  589. .name = "Atmel AT49BV32XT",
  590. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  591. .uaddr = MTD_UADDR_0x0555_0x0AAA, /* ???? */
  592. .dev_size = SIZE_4MiB,
  593. .cmd_set = P_ID_AMD_STD,
  594. .nr_regions = 2,
  595. .regions = {
  596. ERASEINFO(0x10000,63),
  597. ERASEINFO(0x02000,8)
  598. }
  599. }, {
  600. .mfr_id = MANUFACTURER_FUJITSU,
  601. .dev_id = MBM29F040C,
  602. .name = "Fujitsu MBM29F040C",
  603. .devtypes = CFI_DEVICETYPE_X8,
  604. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  605. .dev_size = SIZE_512KiB,
  606. .cmd_set = P_ID_AMD_STD,
  607. .nr_regions = 1,
  608. .regions = {
  609. ERASEINFO(0x10000,8)
  610. }
  611. }, {
  612. .mfr_id = MANUFACTURER_FUJITSU,
  613. .dev_id = MBM29F800BA,
  614. .name = "Fujitsu MBM29F800BA",
  615. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  616. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  617. .dev_size = SIZE_1MiB,
  618. .cmd_set = P_ID_AMD_STD,
  619. .nr_regions = 4,
  620. .regions = {
  621. ERASEINFO(0x04000,1),
  622. ERASEINFO(0x02000,2),
  623. ERASEINFO(0x08000,1),
  624. ERASEINFO(0x10000,15),
  625. }
  626. }, {
  627. .mfr_id = MANUFACTURER_FUJITSU,
  628. .dev_id = MBM29LV650UE,
  629. .name = "Fujitsu MBM29LV650UE",
  630. .devtypes = CFI_DEVICETYPE_X8,
  631. .uaddr = MTD_UADDR_DONT_CARE,
  632. .dev_size = SIZE_8MiB,
  633. .cmd_set = P_ID_AMD_STD,
  634. .nr_regions = 1,
  635. .regions = {
  636. ERASEINFO(0x10000,128)
  637. }
  638. }, {
  639. .mfr_id = MANUFACTURER_FUJITSU,
  640. .dev_id = MBM29LV320TE,
  641. .name = "Fujitsu MBM29LV320TE",
  642. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  643. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  644. .dev_size = SIZE_4MiB,
  645. .cmd_set = P_ID_AMD_STD,
  646. .nr_regions = 2,
  647. .regions = {
  648. ERASEINFO(0x10000,63),
  649. ERASEINFO(0x02000,8)
  650. }
  651. }, {
  652. .mfr_id = MANUFACTURER_FUJITSU,
  653. .dev_id = MBM29LV320BE,
  654. .name = "Fujitsu MBM29LV320BE",
  655. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  656. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  657. .dev_size = SIZE_4MiB,
  658. .cmd_set = P_ID_AMD_STD,
  659. .nr_regions = 2,
  660. .regions = {
  661. ERASEINFO(0x02000,8),
  662. ERASEINFO(0x10000,63)
  663. }
  664. }, {
  665. .mfr_id = MANUFACTURER_FUJITSU,
  666. .dev_id = MBM29LV160TE,
  667. .name = "Fujitsu MBM29LV160TE",
  668. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  669. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  670. .dev_size = SIZE_2MiB,
  671. .cmd_set = P_ID_AMD_STD,
  672. .nr_regions = 4,
  673. .regions = {
  674. ERASEINFO(0x10000,31),
  675. ERASEINFO(0x08000,1),
  676. ERASEINFO(0x02000,2),
  677. ERASEINFO(0x04000,1)
  678. }
  679. }, {
  680. .mfr_id = MANUFACTURER_FUJITSU,
  681. .dev_id = MBM29LV160BE,
  682. .name = "Fujitsu MBM29LV160BE",
  683. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  684. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  685. .dev_size = SIZE_2MiB,
  686. .cmd_set = P_ID_AMD_STD,
  687. .nr_regions = 4,
  688. .regions = {
  689. ERASEINFO(0x04000,1),
  690. ERASEINFO(0x02000,2),
  691. ERASEINFO(0x08000,1),
  692. ERASEINFO(0x10000,31)
  693. }
  694. }, {
  695. .mfr_id = MANUFACTURER_FUJITSU,
  696. .dev_id = MBM29LV800BA,
  697. .name = "Fujitsu MBM29LV800BA",
  698. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  699. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  700. .dev_size = SIZE_1MiB,
  701. .cmd_set = P_ID_AMD_STD,
  702. .nr_regions = 4,
  703. .regions = {
  704. ERASEINFO(0x04000,1),
  705. ERASEINFO(0x02000,2),
  706. ERASEINFO(0x08000,1),
  707. ERASEINFO(0x10000,15)
  708. }
  709. }, {
  710. .mfr_id = MANUFACTURER_FUJITSU,
  711. .dev_id = MBM29LV800TA,
  712. .name = "Fujitsu MBM29LV800TA",
  713. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  714. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  715. .dev_size = SIZE_1MiB,
  716. .cmd_set = P_ID_AMD_STD,
  717. .nr_regions = 4,
  718. .regions = {
  719. ERASEINFO(0x10000,15),
  720. ERASEINFO(0x08000,1),
  721. ERASEINFO(0x02000,2),
  722. ERASEINFO(0x04000,1)
  723. }
  724. }, {
  725. .mfr_id = MANUFACTURER_FUJITSU,
  726. .dev_id = MBM29LV400BC,
  727. .name = "Fujitsu MBM29LV400BC",
  728. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  729. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  730. .dev_size = SIZE_512KiB,
  731. .cmd_set = P_ID_AMD_STD,
  732. .nr_regions = 4,
  733. .regions = {
  734. ERASEINFO(0x04000,1),
  735. ERASEINFO(0x02000,2),
  736. ERASEINFO(0x08000,1),
  737. ERASEINFO(0x10000,7)
  738. }
  739. }, {
  740. .mfr_id = MANUFACTURER_FUJITSU,
  741. .dev_id = MBM29LV400TC,
  742. .name = "Fujitsu MBM29LV400TC",
  743. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  744. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  745. .dev_size = SIZE_512KiB,
  746. .cmd_set = P_ID_AMD_STD,
  747. .nr_regions = 4,
  748. .regions = {
  749. ERASEINFO(0x10000,7),
  750. ERASEINFO(0x08000,1),
  751. ERASEINFO(0x02000,2),
  752. ERASEINFO(0x04000,1)
  753. }
  754. }, {
  755. .mfr_id = MANUFACTURER_HYUNDAI,
  756. .dev_id = HY29F002T,
  757. .name = "Hyundai HY29F002T",
  758. .devtypes = CFI_DEVICETYPE_X8,
  759. .uaddr = MTD_UADDR_0x0555_0x02AA,
  760. .dev_size = SIZE_256KiB,
  761. .cmd_set = P_ID_AMD_STD,
  762. .nr_regions = 4,
  763. .regions = {
  764. ERASEINFO(0x10000,3),
  765. ERASEINFO(0x08000,1),
  766. ERASEINFO(0x02000,2),
  767. ERASEINFO(0x04000,1),
  768. }
  769. }, {
  770. .mfr_id = MANUFACTURER_INTEL,
  771. .dev_id = I28F004B3B,
  772. .name = "Intel 28F004B3B",
  773. .devtypes = CFI_DEVICETYPE_X8,
  774. .uaddr = MTD_UADDR_UNNECESSARY,
  775. .dev_size = SIZE_512KiB,
  776. .cmd_set = P_ID_INTEL_STD,
  777. .nr_regions = 2,
  778. .regions = {
  779. ERASEINFO(0x02000, 8),
  780. ERASEINFO(0x10000, 7),
  781. }
  782. }, {
  783. .mfr_id = MANUFACTURER_INTEL,
  784. .dev_id = I28F004B3T,
  785. .name = "Intel 28F004B3T",
  786. .devtypes = CFI_DEVICETYPE_X8,
  787. .uaddr = MTD_UADDR_UNNECESSARY,
  788. .dev_size = SIZE_512KiB,
  789. .cmd_set = P_ID_INTEL_STD,
  790. .nr_regions = 2,
  791. .regions = {
  792. ERASEINFO(0x10000, 7),
  793. ERASEINFO(0x02000, 8),
  794. }
  795. }, {
  796. .mfr_id = MANUFACTURER_INTEL,
  797. .dev_id = I28F400B3B,
  798. .name = "Intel 28F400B3B",
  799. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  800. .uaddr = MTD_UADDR_UNNECESSARY,
  801. .dev_size = SIZE_512KiB,
  802. .cmd_set = P_ID_INTEL_STD,
  803. .nr_regions = 2,
  804. .regions = {
  805. ERASEINFO(0x02000, 8),
  806. ERASEINFO(0x10000, 7),
  807. }
  808. }, {
  809. .mfr_id = MANUFACTURER_INTEL,
  810. .dev_id = I28F400B3T,
  811. .name = "Intel 28F400B3T",
  812. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  813. .uaddr = MTD_UADDR_UNNECESSARY,
  814. .dev_size = SIZE_512KiB,
  815. .cmd_set = P_ID_INTEL_STD,
  816. .nr_regions = 2,
  817. .regions = {
  818. ERASEINFO(0x10000, 7),
  819. ERASEINFO(0x02000, 8),
  820. }
  821. }, {
  822. .mfr_id = MANUFACTURER_INTEL,
  823. .dev_id = I28F008B3B,
  824. .name = "Intel 28F008B3B",
  825. .devtypes = CFI_DEVICETYPE_X8,
  826. .uaddr = MTD_UADDR_UNNECESSARY,
  827. .dev_size = SIZE_1MiB,
  828. .cmd_set = P_ID_INTEL_STD,
  829. .nr_regions = 2,
  830. .regions = {
  831. ERASEINFO(0x02000, 8),
  832. ERASEINFO(0x10000, 15),
  833. }
  834. }, {
  835. .mfr_id = MANUFACTURER_INTEL,
  836. .dev_id = I28F008B3T,
  837. .name = "Intel 28F008B3T",
  838. .devtypes = CFI_DEVICETYPE_X8,
  839. .uaddr = MTD_UADDR_UNNECESSARY,
  840. .dev_size = SIZE_1MiB,
  841. .cmd_set = P_ID_INTEL_STD,
  842. .nr_regions = 2,
  843. .regions = {
  844. ERASEINFO(0x10000, 15),
  845. ERASEINFO(0x02000, 8),
  846. }
  847. }, {
  848. .mfr_id = MANUFACTURER_INTEL,
  849. .dev_id = I28F008S5,
  850. .name = "Intel 28F008S5",
  851. .devtypes = CFI_DEVICETYPE_X8,
  852. .uaddr = MTD_UADDR_UNNECESSARY,
  853. .dev_size = SIZE_1MiB,
  854. .cmd_set = P_ID_INTEL_EXT,
  855. .nr_regions = 1,
  856. .regions = {
  857. ERASEINFO(0x10000,16),
  858. }
  859. }, {
  860. .mfr_id = MANUFACTURER_INTEL,
  861. .dev_id = I28F016S5,
  862. .name = "Intel 28F016S5",
  863. .devtypes = CFI_DEVICETYPE_X8,
  864. .uaddr = MTD_UADDR_UNNECESSARY,
  865. .dev_size = SIZE_2MiB,
  866. .cmd_set = P_ID_INTEL_EXT,
  867. .nr_regions = 1,
  868. .regions = {
  869. ERASEINFO(0x10000,32),
  870. }
  871. }, {
  872. .mfr_id = MANUFACTURER_INTEL,
  873. .dev_id = I28F008SA,
  874. .name = "Intel 28F008SA",
  875. .devtypes = CFI_DEVICETYPE_X8,
  876. .uaddr = MTD_UADDR_UNNECESSARY,
  877. .dev_size = SIZE_1MiB,
  878. .cmd_set = P_ID_INTEL_STD,
  879. .nr_regions = 1,
  880. .regions = {
  881. ERASEINFO(0x10000, 16),
  882. }
  883. }, {
  884. .mfr_id = MANUFACTURER_INTEL,
  885. .dev_id = I28F800B3B,
  886. .name = "Intel 28F800B3B",
  887. .devtypes = CFI_DEVICETYPE_X16,
  888. .uaddr = MTD_UADDR_UNNECESSARY,
  889. .dev_size = SIZE_1MiB,
  890. .cmd_set = P_ID_INTEL_STD,
  891. .nr_regions = 2,
  892. .regions = {
  893. ERASEINFO(0x02000, 8),
  894. ERASEINFO(0x10000, 15),
  895. }
  896. }, {
  897. .mfr_id = MANUFACTURER_INTEL,
  898. .dev_id = I28F800B3T,
  899. .name = "Intel 28F800B3T",
  900. .devtypes = CFI_DEVICETYPE_X16,
  901. .uaddr = MTD_UADDR_UNNECESSARY,
  902. .dev_size = SIZE_1MiB,
  903. .cmd_set = P_ID_INTEL_STD,
  904. .nr_regions = 2,
  905. .regions = {
  906. ERASEINFO(0x10000, 15),
  907. ERASEINFO(0x02000, 8),
  908. }
  909. }, {
  910. .mfr_id = MANUFACTURER_INTEL,
  911. .dev_id = I28F016B3B,
  912. .name = "Intel 28F016B3B",
  913. .devtypes = CFI_DEVICETYPE_X8,
  914. .uaddr = MTD_UADDR_UNNECESSARY,
  915. .dev_size = SIZE_2MiB,
  916. .cmd_set = P_ID_INTEL_STD,
  917. .nr_regions = 2,
  918. .regions = {
  919. ERASEINFO(0x02000, 8),
  920. ERASEINFO(0x10000, 31),
  921. }
  922. }, {
  923. .mfr_id = MANUFACTURER_INTEL,
  924. .dev_id = I28F016S3,
  925. .name = "Intel I28F016S3",
  926. .devtypes = CFI_DEVICETYPE_X8,
  927. .uaddr = MTD_UADDR_UNNECESSARY,
  928. .dev_size = SIZE_2MiB,
  929. .cmd_set = P_ID_INTEL_STD,
  930. .nr_regions = 1,
  931. .regions = {
  932. ERASEINFO(0x10000, 32),
  933. }
  934. }, {
  935. .mfr_id = MANUFACTURER_INTEL,
  936. .dev_id = I28F016B3T,
  937. .name = "Intel 28F016B3T",
  938. .devtypes = CFI_DEVICETYPE_X8,
  939. .uaddr = MTD_UADDR_UNNECESSARY,
  940. .dev_size = SIZE_2MiB,
  941. .cmd_set = P_ID_INTEL_STD,
  942. .nr_regions = 2,
  943. .regions = {
  944. ERASEINFO(0x10000, 31),
  945. ERASEINFO(0x02000, 8),
  946. }
  947. }, {
  948. .mfr_id = MANUFACTURER_INTEL,
  949. .dev_id = I28F160B3B,
  950. .name = "Intel 28F160B3B",
  951. .devtypes = CFI_DEVICETYPE_X16,
  952. .uaddr = MTD_UADDR_UNNECESSARY,
  953. .dev_size = SIZE_2MiB,
  954. .cmd_set = P_ID_INTEL_STD,
  955. .nr_regions = 2,
  956. .regions = {
  957. ERASEINFO(0x02000, 8),
  958. ERASEINFO(0x10000, 31),
  959. }
  960. }, {
  961. .mfr_id = MANUFACTURER_INTEL,
  962. .dev_id = I28F160B3T,
  963. .name = "Intel 28F160B3T",
  964. .devtypes = CFI_DEVICETYPE_X16,
  965. .uaddr = MTD_UADDR_UNNECESSARY,
  966. .dev_size = SIZE_2MiB,
  967. .cmd_set = P_ID_INTEL_STD,
  968. .nr_regions = 2,
  969. .regions = {
  970. ERASEINFO(0x10000, 31),
  971. ERASEINFO(0x02000, 8),
  972. }
  973. }, {
  974. .mfr_id = MANUFACTURER_INTEL,
  975. .dev_id = I28F320B3B,
  976. .name = "Intel 28F320B3B",
  977. .devtypes = CFI_DEVICETYPE_X16,
  978. .uaddr = MTD_UADDR_UNNECESSARY,
  979. .dev_size = SIZE_4MiB,
  980. .cmd_set = P_ID_INTEL_STD,
  981. .nr_regions = 2,
  982. .regions = {
  983. ERASEINFO(0x02000, 8),
  984. ERASEINFO(0x10000, 63),
  985. }
  986. }, {
  987. .mfr_id = MANUFACTURER_INTEL,
  988. .dev_id = I28F320B3T,
  989. .name = "Intel 28F320B3T",
  990. .devtypes = CFI_DEVICETYPE_X16,
  991. .uaddr = MTD_UADDR_UNNECESSARY,
  992. .dev_size = SIZE_4MiB,
  993. .cmd_set = P_ID_INTEL_STD,
  994. .nr_regions = 2,
  995. .regions = {
  996. ERASEINFO(0x10000, 63),
  997. ERASEINFO(0x02000, 8),
  998. }
  999. }, {
  1000. .mfr_id = MANUFACTURER_INTEL,
  1001. .dev_id = I28F640B3B,
  1002. .name = "Intel 28F640B3B",
  1003. .devtypes = CFI_DEVICETYPE_X16,
  1004. .uaddr = MTD_UADDR_UNNECESSARY,
  1005. .dev_size = SIZE_8MiB,
  1006. .cmd_set = P_ID_INTEL_STD,
  1007. .nr_regions = 2,
  1008. .regions = {
  1009. ERASEINFO(0x02000, 8),
  1010. ERASEINFO(0x10000, 127),
  1011. }
  1012. }, {
  1013. .mfr_id = MANUFACTURER_INTEL,
  1014. .dev_id = I28F640B3T,
  1015. .name = "Intel 28F640B3T",
  1016. .devtypes = CFI_DEVICETYPE_X16,
  1017. .uaddr = MTD_UADDR_UNNECESSARY,
  1018. .dev_size = SIZE_8MiB,
  1019. .cmd_set = P_ID_INTEL_STD,
  1020. .nr_regions = 2,
  1021. .regions = {
  1022. ERASEINFO(0x10000, 127),
  1023. ERASEINFO(0x02000, 8),
  1024. }
  1025. }, {
  1026. .mfr_id = MANUFACTURER_INTEL,
  1027. .dev_id = I82802AB,
  1028. .name = "Intel 82802AB",
  1029. .devtypes = CFI_DEVICETYPE_X8,
  1030. .uaddr = MTD_UADDR_UNNECESSARY,
  1031. .dev_size = SIZE_512KiB,
  1032. .cmd_set = P_ID_INTEL_EXT,
  1033. .nr_regions = 1,
  1034. .regions = {
  1035. ERASEINFO(0x10000,8),
  1036. }
  1037. }, {
  1038. .mfr_id = MANUFACTURER_INTEL,
  1039. .dev_id = I82802AC,
  1040. .name = "Intel 82802AC",
  1041. .devtypes = CFI_DEVICETYPE_X8,
  1042. .uaddr = MTD_UADDR_UNNECESSARY,
  1043. .dev_size = SIZE_1MiB,
  1044. .cmd_set = P_ID_INTEL_EXT,
  1045. .nr_regions = 1,
  1046. .regions = {
  1047. ERASEINFO(0x10000,16),
  1048. }
  1049. }, {
  1050. .mfr_id = MANUFACTURER_MACRONIX,
  1051. .dev_id = MX29LV040C,
  1052. .name = "Macronix MX29LV040C",
  1053. .devtypes = CFI_DEVICETYPE_X8,
  1054. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1055. .dev_size = SIZE_512KiB,
  1056. .cmd_set = P_ID_AMD_STD,
  1057. .nr_regions = 1,
  1058. .regions = {
  1059. ERASEINFO(0x10000,8),
  1060. }
  1061. }, {
  1062. .mfr_id = MANUFACTURER_MACRONIX,
  1063. .dev_id = MX29LV160T,
  1064. .name = "MXIC MX29LV160T",
  1065. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1066. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1067. .dev_size = SIZE_2MiB,
  1068. .cmd_set = P_ID_AMD_STD,
  1069. .nr_regions = 4,
  1070. .regions = {
  1071. ERASEINFO(0x10000,31),
  1072. ERASEINFO(0x08000,1),
  1073. ERASEINFO(0x02000,2),
  1074. ERASEINFO(0x04000,1)
  1075. }
  1076. }, {
  1077. .mfr_id = MANUFACTURER_NEC,
  1078. .dev_id = UPD29F064115,
  1079. .name = "NEC uPD29F064115",
  1080. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1081. .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
  1082. .dev_size = SIZE_8MiB,
  1083. .cmd_set = P_ID_AMD_STD,
  1084. .nr_regions = 3,
  1085. .regions = {
  1086. ERASEINFO(0x2000,8),
  1087. ERASEINFO(0x10000,126),
  1088. ERASEINFO(0x2000,8),
  1089. }
  1090. }, {
  1091. .mfr_id = MANUFACTURER_MACRONIX,
  1092. .dev_id = MX29LV160B,
  1093. .name = "MXIC MX29LV160B",
  1094. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1095. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1096. .dev_size = SIZE_2MiB,
  1097. .cmd_set = P_ID_AMD_STD,
  1098. .nr_regions = 4,
  1099. .regions = {
  1100. ERASEINFO(0x04000,1),
  1101. ERASEINFO(0x02000,2),
  1102. ERASEINFO(0x08000,1),
  1103. ERASEINFO(0x10000,31)
  1104. }
  1105. }, {
  1106. .mfr_id = MANUFACTURER_MACRONIX,
  1107. .dev_id = MX29F040,
  1108. .name = "Macronix MX29F040",
  1109. .devtypes = CFI_DEVICETYPE_X8,
  1110. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1111. .dev_size = SIZE_512KiB,
  1112. .cmd_set = P_ID_AMD_STD,
  1113. .nr_regions = 1,
  1114. .regions = {
  1115. ERASEINFO(0x10000,8),
  1116. }
  1117. }, {
  1118. .mfr_id = MANUFACTURER_MACRONIX,
  1119. .dev_id = MX29F016,
  1120. .name = "Macronix MX29F016",
  1121. .devtypes = CFI_DEVICETYPE_X8,
  1122. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1123. .dev_size = SIZE_2MiB,
  1124. .cmd_set = P_ID_AMD_STD,
  1125. .nr_regions = 1,
  1126. .regions = {
  1127. ERASEINFO(0x10000,32),
  1128. }
  1129. }, {
  1130. .mfr_id = MANUFACTURER_MACRONIX,
  1131. .dev_id = MX29F004T,
  1132. .name = "Macronix MX29F004T",
  1133. .devtypes = CFI_DEVICETYPE_X8,
  1134. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1135. .dev_size = SIZE_512KiB,
  1136. .cmd_set = P_ID_AMD_STD,
  1137. .nr_regions = 4,
  1138. .regions = {
  1139. ERASEINFO(0x10000,7),
  1140. ERASEINFO(0x08000,1),
  1141. ERASEINFO(0x02000,2),
  1142. ERASEINFO(0x04000,1),
  1143. }
  1144. }, {
  1145. .mfr_id = MANUFACTURER_MACRONIX,
  1146. .dev_id = MX29F004B,
  1147. .name = "Macronix MX29F004B",
  1148. .devtypes = CFI_DEVICETYPE_X8,
  1149. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1150. .dev_size = SIZE_512KiB,
  1151. .cmd_set = P_ID_AMD_STD,
  1152. .nr_regions = 4,
  1153. .regions = {
  1154. ERASEINFO(0x04000,1),
  1155. ERASEINFO(0x02000,2),
  1156. ERASEINFO(0x08000,1),
  1157. ERASEINFO(0x10000,7),
  1158. }
  1159. }, {
  1160. .mfr_id = MANUFACTURER_MACRONIX,
  1161. .dev_id = MX29F002T,
  1162. .name = "Macronix MX29F002T",
  1163. .devtypes = CFI_DEVICETYPE_X8,
  1164. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1165. .dev_size = SIZE_256KiB,
  1166. .cmd_set = P_ID_AMD_STD,
  1167. .nr_regions = 4,
  1168. .regions = {
  1169. ERASEINFO(0x10000,3),
  1170. ERASEINFO(0x08000,1),
  1171. ERASEINFO(0x02000,2),
  1172. ERASEINFO(0x04000,1),
  1173. }
  1174. }, {
  1175. .mfr_id = MANUFACTURER_PMC,
  1176. .dev_id = PM49FL002,
  1177. .name = "PMC Pm49FL002",
  1178. .devtypes = CFI_DEVICETYPE_X8,
  1179. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1180. .dev_size = SIZE_256KiB,
  1181. .cmd_set = P_ID_AMD_STD,
  1182. .nr_regions = 1,
  1183. .regions = {
  1184. ERASEINFO( 0x01000, 64 )
  1185. }
  1186. }, {
  1187. .mfr_id = MANUFACTURER_PMC,
  1188. .dev_id = PM49FL004,
  1189. .name = "PMC Pm49FL004",
  1190. .devtypes = CFI_DEVICETYPE_X8,
  1191. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1192. .dev_size = SIZE_512KiB,
  1193. .cmd_set = P_ID_AMD_STD,
  1194. .nr_regions = 1,
  1195. .regions = {
  1196. ERASEINFO( 0x01000, 128 )
  1197. }
  1198. }, {
  1199. .mfr_id = MANUFACTURER_PMC,
  1200. .dev_id = PM49FL008,
  1201. .name = "PMC Pm49FL008",
  1202. .devtypes = CFI_DEVICETYPE_X8,
  1203. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1204. .dev_size = SIZE_1MiB,
  1205. .cmd_set = P_ID_AMD_STD,
  1206. .nr_regions = 1,
  1207. .regions = {
  1208. ERASEINFO( 0x01000, 256 )
  1209. }
  1210. }, {
  1211. .mfr_id = MANUFACTURER_SHARP,
  1212. .dev_id = LH28F640BF,
  1213. .name = "LH28F640BF",
  1214. .devtypes = CFI_DEVICETYPE_X8,
  1215. .uaddr = MTD_UADDR_UNNECESSARY,
  1216. .dev_size = SIZE_4MiB,
  1217. .cmd_set = P_ID_INTEL_STD,
  1218. .nr_regions = 1,
  1219. .regions = {
  1220. ERASEINFO(0x40000,16),
  1221. }
  1222. }, {
  1223. .mfr_id = MANUFACTURER_SST,
  1224. .dev_id = SST39LF512,
  1225. .name = "SST 39LF512",
  1226. .devtypes = CFI_DEVICETYPE_X8,
  1227. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1228. .dev_size = SIZE_64KiB,
  1229. .cmd_set = P_ID_AMD_STD,
  1230. .nr_regions = 1,
  1231. .regions = {
  1232. ERASEINFO(0x01000,16),
  1233. }
  1234. }, {
  1235. .mfr_id = MANUFACTURER_SST,
  1236. .dev_id = SST39LF010,
  1237. .name = "SST 39LF010",
  1238. .devtypes = CFI_DEVICETYPE_X8,
  1239. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1240. .dev_size = SIZE_128KiB,
  1241. .cmd_set = P_ID_AMD_STD,
  1242. .nr_regions = 1,
  1243. .regions = {
  1244. ERASEINFO(0x01000,32),
  1245. }
  1246. }, {
  1247. .mfr_id = MANUFACTURER_SST,
  1248. .dev_id = SST29EE020,
  1249. .name = "SST 29EE020",
  1250. .devtypes = CFI_DEVICETYPE_X8,
  1251. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1252. .dev_size = SIZE_256KiB,
  1253. .cmd_set = P_ID_SST_PAGE,
  1254. .nr_regions = 1,
  1255. .regions = {ERASEINFO(0x01000,64),
  1256. }
  1257. }, {
  1258. .mfr_id = MANUFACTURER_SST,
  1259. .dev_id = SST29LE020,
  1260. .name = "SST 29LE020",
  1261. .devtypes = CFI_DEVICETYPE_X8,
  1262. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1263. .dev_size = SIZE_256KiB,
  1264. .cmd_set = P_ID_SST_PAGE,
  1265. .nr_regions = 1,
  1266. .regions = {ERASEINFO(0x01000,64),
  1267. }
  1268. }, {
  1269. .mfr_id = MANUFACTURER_SST,
  1270. .dev_id = SST39LF020,
  1271. .name = "SST 39LF020",
  1272. .devtypes = CFI_DEVICETYPE_X8,
  1273. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1274. .dev_size = SIZE_256KiB,
  1275. .cmd_set = P_ID_AMD_STD,
  1276. .nr_regions = 1,
  1277. .regions = {
  1278. ERASEINFO(0x01000,64),
  1279. }
  1280. }, {
  1281. .mfr_id = MANUFACTURER_SST,
  1282. .dev_id = SST39LF040,
  1283. .name = "SST 39LF040",
  1284. .devtypes = CFI_DEVICETYPE_X8,
  1285. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1286. .dev_size = SIZE_512KiB,
  1287. .cmd_set = P_ID_AMD_STD,
  1288. .nr_regions = 1,
  1289. .regions = {
  1290. ERASEINFO(0x01000,128),
  1291. }
  1292. }, {
  1293. .mfr_id = MANUFACTURER_SST,
  1294. .dev_id = SST39SF010A,
  1295. .name = "SST 39SF010A",
  1296. .devtypes = CFI_DEVICETYPE_X8,
  1297. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1298. .dev_size = SIZE_128KiB,
  1299. .cmd_set = P_ID_AMD_STD,
  1300. .nr_regions = 1,
  1301. .regions = {
  1302. ERASEINFO(0x01000,32),
  1303. }
  1304. }, {
  1305. .mfr_id = MANUFACTURER_SST,
  1306. .dev_id = SST39SF020A,
  1307. .name = "SST 39SF020A",
  1308. .devtypes = CFI_DEVICETYPE_X8,
  1309. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1310. .dev_size = SIZE_256KiB,
  1311. .cmd_set = P_ID_AMD_STD,
  1312. .nr_regions = 1,
  1313. .regions = {
  1314. ERASEINFO(0x01000,64),
  1315. }
  1316. }, {
  1317. .mfr_id = MANUFACTURER_SST,
  1318. .dev_id = SST49LF040B,
  1319. .name = "SST 49LF040B",
  1320. .devtypes = CFI_DEVICETYPE_X8,
  1321. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1322. .dev_size = SIZE_512KiB,
  1323. .cmd_set = P_ID_AMD_STD,
  1324. .nr_regions = 1,
  1325. .regions = {
  1326. ERASEINFO(0x01000,128),
  1327. }
  1328. }, {
  1329. .mfr_id = MANUFACTURER_SST,
  1330. .dev_id = SST49LF004B,
  1331. .name = "SST 49LF004B",
  1332. .devtypes = CFI_DEVICETYPE_X8,
  1333. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1334. .dev_size = SIZE_512KiB,
  1335. .cmd_set = P_ID_AMD_STD,
  1336. .nr_regions = 1,
  1337. .regions = {
  1338. ERASEINFO(0x01000,128),
  1339. }
  1340. }, {
  1341. .mfr_id = MANUFACTURER_SST,
  1342. .dev_id = SST49LF008A,
  1343. .name = "SST 49LF008A",
  1344. .devtypes = CFI_DEVICETYPE_X8,
  1345. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1346. .dev_size = SIZE_1MiB,
  1347. .cmd_set = P_ID_AMD_STD,
  1348. .nr_regions = 1,
  1349. .regions = {
  1350. ERASEINFO(0x01000,256),
  1351. }
  1352. }, {
  1353. .mfr_id = MANUFACTURER_SST,
  1354. .dev_id = SST49LF030A,
  1355. .name = "SST 49LF030A",
  1356. .devtypes = CFI_DEVICETYPE_X8,
  1357. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1358. .dev_size = SIZE_512KiB,
  1359. .cmd_set = P_ID_AMD_STD,
  1360. .nr_regions = 1,
  1361. .regions = {
  1362. ERASEINFO(0x01000,96),
  1363. }
  1364. }, {
  1365. .mfr_id = MANUFACTURER_SST,
  1366. .dev_id = SST49LF040A,
  1367. .name = "SST 49LF040A",
  1368. .devtypes = CFI_DEVICETYPE_X8,
  1369. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1370. .dev_size = SIZE_512KiB,
  1371. .cmd_set = P_ID_AMD_STD,
  1372. .nr_regions = 1,
  1373. .regions = {
  1374. ERASEINFO(0x01000,128),
  1375. }
  1376. }, {
  1377. .mfr_id = MANUFACTURER_SST,
  1378. .dev_id = SST49LF080A,
  1379. .name = "SST 49LF080A",
  1380. .devtypes = CFI_DEVICETYPE_X8,
  1381. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1382. .dev_size = SIZE_1MiB,
  1383. .cmd_set = P_ID_AMD_STD,
  1384. .nr_regions = 1,
  1385. .regions = {
  1386. ERASEINFO(0x01000,256),
  1387. }
  1388. }, {
  1389. .mfr_id = MANUFACTURER_SST, /* should be CFI */
  1390. .dev_id = SST39LF160,
  1391. .name = "SST 39LF160",
  1392. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1393. .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
  1394. .dev_size = SIZE_2MiB,
  1395. .cmd_set = P_ID_AMD_STD,
  1396. .nr_regions = 2,
  1397. .regions = {
  1398. ERASEINFO(0x1000,256),
  1399. ERASEINFO(0x1000,256)
  1400. }
  1401. }, {
  1402. .mfr_id = MANUFACTURER_SST, /* should be CFI */
  1403. .dev_id = SST39VF1601,
  1404. .name = "SST 39VF1601",
  1405. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1406. .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
  1407. .dev_size = SIZE_2MiB,
  1408. .cmd_set = P_ID_AMD_STD,
  1409. .nr_regions = 2,
  1410. .regions = {
  1411. ERASEINFO(0x1000,256),
  1412. ERASEINFO(0x1000,256)
  1413. }
  1414. }, {
  1415. .mfr_id = MANUFACTURER_SST,
  1416. .dev_id = SST36VF3203,
  1417. .name = "SST 36VF3203",
  1418. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1419. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1420. .dev_size = SIZE_4MiB,
  1421. .cmd_set = P_ID_AMD_STD,
  1422. .nr_regions = 1,
  1423. .regions = {
  1424. ERASEINFO(0x10000,64),
  1425. }
  1426. }, {
  1427. .mfr_id = MANUFACTURER_ST,
  1428. .dev_id = M29F800AB,
  1429. .name = "ST M29F800AB",
  1430. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1431. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1432. .dev_size = SIZE_1MiB,
  1433. .cmd_set = P_ID_AMD_STD,
  1434. .nr_regions = 4,
  1435. .regions = {
  1436. ERASEINFO(0x04000,1),
  1437. ERASEINFO(0x02000,2),
  1438. ERASEINFO(0x08000,1),
  1439. ERASEINFO(0x10000,15),
  1440. }
  1441. }, {
  1442. .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
  1443. .dev_id = M29W800DT,
  1444. .name = "ST M29W800DT",
  1445. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1446. .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
  1447. .dev_size = SIZE_1MiB,
  1448. .cmd_set = P_ID_AMD_STD,
  1449. .nr_regions = 4,
  1450. .regions = {
  1451. ERASEINFO(0x10000,15),
  1452. ERASEINFO(0x08000,1),
  1453. ERASEINFO(0x02000,2),
  1454. ERASEINFO(0x04000,1)
  1455. }
  1456. }, {
  1457. .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
  1458. .dev_id = M29W800DB,
  1459. .name = "ST M29W800DB",
  1460. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1461. .uaddr = MTD_UADDR_0x5555_0x2AAA, /* ???? */
  1462. .dev_size = SIZE_1MiB,
  1463. .cmd_set = P_ID_AMD_STD,
  1464. .nr_regions = 4,
  1465. .regions = {
  1466. ERASEINFO(0x04000,1),
  1467. ERASEINFO(0x02000,2),
  1468. ERASEINFO(0x08000,1),
  1469. ERASEINFO(0x10000,15)
  1470. }
  1471. }, {
  1472. .mfr_id = MANUFACTURER_ST,
  1473. .dev_id = M29W400DT,
  1474. .name = "ST M29W400DT",
  1475. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1476. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1477. .dev_size = SIZE_512KiB,
  1478. .cmd_set = P_ID_AMD_STD,
  1479. .nr_regions = 4,
  1480. .regions = {
  1481. ERASEINFO(0x04000,7),
  1482. ERASEINFO(0x02000,1),
  1483. ERASEINFO(0x08000,2),
  1484. ERASEINFO(0x10000,1)
  1485. }
  1486. }, {
  1487. .mfr_id = MANUFACTURER_ST,
  1488. .dev_id = M29W400DB,
  1489. .name = "ST M29W400DB",
  1490. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1491. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1492. .dev_size = SIZE_512KiB,
  1493. .cmd_set = P_ID_AMD_STD,
  1494. .nr_regions = 4,
  1495. .regions = {
  1496. ERASEINFO(0x04000,1),
  1497. ERASEINFO(0x02000,2),
  1498. ERASEINFO(0x08000,1),
  1499. ERASEINFO(0x10000,7)
  1500. }
  1501. }, {
  1502. .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
  1503. .dev_id = M29W160DT,
  1504. .name = "ST M29W160DT",
  1505. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1506. .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
  1507. .dev_size = SIZE_2MiB,
  1508. .cmd_set = P_ID_AMD_STD,
  1509. .nr_regions = 4,
  1510. .regions = {
  1511. ERASEINFO(0x10000,31),
  1512. ERASEINFO(0x08000,1),
  1513. ERASEINFO(0x02000,2),
  1514. ERASEINFO(0x04000,1)
  1515. }
  1516. }, {
  1517. .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
  1518. .dev_id = M29W160DB,
  1519. .name = "ST M29W160DB",
  1520. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1521. .uaddr = MTD_UADDR_0x0555_0x02AA, /* ???? */
  1522. .dev_size = SIZE_2MiB,
  1523. .cmd_set = P_ID_AMD_STD,
  1524. .nr_regions = 4,
  1525. .regions = {
  1526. ERASEINFO(0x04000,1),
  1527. ERASEINFO(0x02000,2),
  1528. ERASEINFO(0x08000,1),
  1529. ERASEINFO(0x10000,31)
  1530. }
  1531. }, {
  1532. .mfr_id = MANUFACTURER_ST,
  1533. .dev_id = M29W040B,
  1534. .name = "ST M29W040B",
  1535. .devtypes = CFI_DEVICETYPE_X8,
  1536. .uaddr = MTD_UADDR_0x0555_0x02AA,
  1537. .dev_size = SIZE_512KiB,
  1538. .cmd_set = P_ID_AMD_STD,
  1539. .nr_regions = 1,
  1540. .regions = {
  1541. ERASEINFO(0x10000,8),
  1542. }
  1543. }, {
  1544. .mfr_id = MANUFACTURER_ST,
  1545. .dev_id = M50FW040,
  1546. .name = "ST M50FW040",
  1547. .devtypes = CFI_DEVICETYPE_X8,
  1548. .uaddr = MTD_UADDR_UNNECESSARY,
  1549. .dev_size = SIZE_512KiB,
  1550. .cmd_set = P_ID_INTEL_EXT,
  1551. .nr_regions = 1,
  1552. .regions = {
  1553. ERASEINFO(0x10000,8),
  1554. }
  1555. }, {
  1556. .mfr_id = MANUFACTURER_ST,
  1557. .dev_id = M50FW080,
  1558. .name = "ST M50FW080",
  1559. .devtypes = CFI_DEVICETYPE_X8,
  1560. .uaddr = MTD_UADDR_UNNECESSARY,
  1561. .dev_size = SIZE_1MiB,
  1562. .cmd_set = P_ID_INTEL_EXT,
  1563. .nr_regions = 1,
  1564. .regions = {
  1565. ERASEINFO(0x10000,16),
  1566. }
  1567. }, {
  1568. .mfr_id = MANUFACTURER_ST,
  1569. .dev_id = M50FW016,
  1570. .name = "ST M50FW016",
  1571. .devtypes = CFI_DEVICETYPE_X8,
  1572. .uaddr = MTD_UADDR_UNNECESSARY,
  1573. .dev_size = SIZE_2MiB,
  1574. .cmd_set = P_ID_INTEL_EXT,
  1575. .nr_regions = 1,
  1576. .regions = {
  1577. ERASEINFO(0x10000,32),
  1578. }
  1579. }, {
  1580. .mfr_id = MANUFACTURER_ST,
  1581. .dev_id = M50LPW080,
  1582. .name = "ST M50LPW080",
  1583. .devtypes = CFI_DEVICETYPE_X8,
  1584. .uaddr = MTD_UADDR_UNNECESSARY,
  1585. .dev_size = SIZE_1MiB,
  1586. .cmd_set = P_ID_INTEL_EXT,
  1587. .nr_regions = 1,
  1588. .regions = {
  1589. ERASEINFO(0x10000,16),
  1590. },
  1591. }, {
  1592. .mfr_id = MANUFACTURER_ST,
  1593. .dev_id = M50FLW080A,
  1594. .name = "ST M50FLW080A",
  1595. .devtypes = CFI_DEVICETYPE_X8,
  1596. .uaddr = MTD_UADDR_UNNECESSARY,
  1597. .dev_size = SIZE_1MiB,
  1598. .cmd_set = P_ID_INTEL_EXT,
  1599. .nr_regions = 4,
  1600. .regions = {
  1601. ERASEINFO(0x1000,16),
  1602. ERASEINFO(0x10000,13),
  1603. ERASEINFO(0x1000,16),
  1604. ERASEINFO(0x1000,16),
  1605. }
  1606. }, {
  1607. .mfr_id = MANUFACTURER_ST,
  1608. .dev_id = M50FLW080B,
  1609. .name = "ST M50FLW080B",
  1610. .devtypes = CFI_DEVICETYPE_X8,
  1611. .uaddr = MTD_UADDR_UNNECESSARY,
  1612. .dev_size = SIZE_1MiB,
  1613. .cmd_set = P_ID_INTEL_EXT,
  1614. .nr_regions = 4,
  1615. .regions = {
  1616. ERASEINFO(0x1000,16),
  1617. ERASEINFO(0x1000,16),
  1618. ERASEINFO(0x10000,13),
  1619. ERASEINFO(0x1000,16),
  1620. }
  1621. }, {
  1622. .mfr_id = MANUFACTURER_TOSHIBA,
  1623. .dev_id = TC58FVT160,
  1624. .name = "Toshiba TC58FVT160",
  1625. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1626. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1627. .dev_size = SIZE_2MiB,
  1628. .cmd_set = P_ID_AMD_STD,
  1629. .nr_regions = 4,
  1630. .regions = {
  1631. ERASEINFO(0x10000,31),
  1632. ERASEINFO(0x08000,1),
  1633. ERASEINFO(0x02000,2),
  1634. ERASEINFO(0x04000,1)
  1635. }
  1636. }, {
  1637. .mfr_id = MANUFACTURER_TOSHIBA,
  1638. .dev_id = TC58FVB160,
  1639. .name = "Toshiba TC58FVB160",
  1640. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1641. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1642. .dev_size = SIZE_2MiB,
  1643. .cmd_set = P_ID_AMD_STD,
  1644. .nr_regions = 4,
  1645. .regions = {
  1646. ERASEINFO(0x04000,1),
  1647. ERASEINFO(0x02000,2),
  1648. ERASEINFO(0x08000,1),
  1649. ERASEINFO(0x10000,31)
  1650. }
  1651. }, {
  1652. .mfr_id = MANUFACTURER_TOSHIBA,
  1653. .dev_id = TC58FVB321,
  1654. .name = "Toshiba TC58FVB321",
  1655. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1656. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1657. .dev_size = SIZE_4MiB,
  1658. .cmd_set = P_ID_AMD_STD,
  1659. .nr_regions = 2,
  1660. .regions = {
  1661. ERASEINFO(0x02000,8),
  1662. ERASEINFO(0x10000,63)
  1663. }
  1664. }, {
  1665. .mfr_id = MANUFACTURER_TOSHIBA,
  1666. .dev_id = TC58FVT321,
  1667. .name = "Toshiba TC58FVT321",
  1668. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1669. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1670. .dev_size = SIZE_4MiB,
  1671. .cmd_set = P_ID_AMD_STD,
  1672. .nr_regions = 2,
  1673. .regions = {
  1674. ERASEINFO(0x10000,63),
  1675. ERASEINFO(0x02000,8)
  1676. }
  1677. }, {
  1678. .mfr_id = MANUFACTURER_TOSHIBA,
  1679. .dev_id = TC58FVB641,
  1680. .name = "Toshiba TC58FVB641",
  1681. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1682. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1683. .dev_size = SIZE_8MiB,
  1684. .cmd_set = P_ID_AMD_STD,
  1685. .nr_regions = 2,
  1686. .regions = {
  1687. ERASEINFO(0x02000,8),
  1688. ERASEINFO(0x10000,127)
  1689. }
  1690. }, {
  1691. .mfr_id = MANUFACTURER_TOSHIBA,
  1692. .dev_id = TC58FVT641,
  1693. .name = "Toshiba TC58FVT641",
  1694. .devtypes = CFI_DEVICETYPE_X16|CFI_DEVICETYPE_X8,
  1695. .uaddr = MTD_UADDR_0x0AAA_0x0555,
  1696. .dev_size = SIZE_8MiB,
  1697. .cmd_set = P_ID_AMD_STD,
  1698. .nr_regions = 2,
  1699. .regions = {
  1700. ERASEINFO(0x10000,127),
  1701. ERASEINFO(0x02000,8)
  1702. }
  1703. }, {
  1704. .mfr_id = MANUFACTURER_WINBOND,
  1705. .dev_id = W49V002A,
  1706. .name = "Winbond W49V002A",
  1707. .devtypes = CFI_DEVICETYPE_X8,
  1708. .uaddr = MTD_UADDR_0x5555_0x2AAA,
  1709. .dev_size = SIZE_256KiB,
  1710. .cmd_set = P_ID_AMD_STD,
  1711. .nr_regions = 4,
  1712. .regions = {
  1713. ERASEINFO(0x10000, 3),
  1714. ERASEINFO(0x08000, 1),
  1715. ERASEINFO(0x02000, 2),
  1716. ERASEINFO(0x04000, 1),
  1717. }
  1718. }
  1719. };
  1720. static inline u32 jedec_read_mfr(struct map_info *map, uint32_t base,
  1721. struct cfi_private *cfi)
  1722. {
  1723. map_word result;
  1724. unsigned long mask;
  1725. u32 ofs = cfi_build_cmd_addr(0, cfi_interleave(cfi), cfi->device_type);
  1726. mask = (1 << (cfi->device_type * 8)) -1;
  1727. result = map_read(map, base + ofs);
  1728. return result.x[0] & mask;
  1729. }
  1730. static inline u32 jedec_read_id(struct map_info *map, uint32_t base,
  1731. struct cfi_private *cfi)
  1732. {
  1733. map_word result;
  1734. unsigned long mask;
  1735. u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type);
  1736. mask = (1 << (cfi->device_type * 8)) -1;
  1737. result = map_read(map, base + ofs);
  1738. return result.x[0] & mask;
  1739. }
  1740. static void jedec_reset(u32 base, struct map_info *map, struct cfi_private *cfi)
  1741. {
  1742. /* Reset */
  1743. /* after checking the datasheets for SST, MACRONIX and ATMEL
  1744. * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
  1745. * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
  1746. * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
  1747. * as they will ignore the writes and dont care what address
  1748. * the F0 is written to */
  1749. if (cfi->addr_unlock1) {
  1750. DEBUG( MTD_DEBUG_LEVEL3,
  1751. "reset unlock called %x %x \n",
  1752. cfi->addr_unlock1,cfi->addr_unlock2);
  1753. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1754. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  1755. }
  1756. cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1757. /* Some misdesigned Intel chips do not respond for 0xF0 for a reset,
  1758. * so ensure we're in read mode. Send both the Intel and the AMD command
  1759. * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
  1760. * this should be safe.
  1761. */
  1762. cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
  1763. /* FIXME - should have reset delay before continuing */
  1764. }
  1765. static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
  1766. {
  1767. int i,num_erase_regions;
  1768. uint8_t uaddr;
  1769. if (! (jedec_table[index].devtypes & p_cfi->device_type)) {
  1770. DEBUG(MTD_DEBUG_LEVEL1, "Rejecting potential %s with incompatible %d-bit device type\n",
  1771. jedec_table[index].name, 4 * (1<<p_cfi->device_type));
  1772. return 0;
  1773. }
  1774. printk(KERN_INFO "Found: %s\n",jedec_table[index].name);
  1775. num_erase_regions = jedec_table[index].nr_regions;
  1776. p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
  1777. if (!p_cfi->cfiq) {
  1778. //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
  1779. return 0;
  1780. }
  1781. memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
  1782. p_cfi->cfiq->P_ID = jedec_table[index].cmd_set;
  1783. p_cfi->cfiq->NumEraseRegions = jedec_table[index].nr_regions;
  1784. p_cfi->cfiq->DevSize = jedec_table[index].dev_size;
  1785. p_cfi->cfi_mode = CFI_MODE_JEDEC;
  1786. for (i=0; i<num_erase_regions; i++){
  1787. p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
  1788. }
  1789. p_cfi->cmdset_priv = NULL;
  1790. /* This may be redundant for some cases, but it doesn't hurt */
  1791. p_cfi->mfr = jedec_table[index].mfr_id;
  1792. p_cfi->id = jedec_table[index].dev_id;
  1793. uaddr = jedec_table[index].uaddr;
  1794. /* The table has unlock addresses in _bytes_, and we try not to let
  1795. our brains explode when we see the datasheets talking about address
  1796. lines numbered from A-1 to A18. The CFI table has unlock addresses
  1797. in device-words according to the mode the device is connected in */
  1798. p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1 / p_cfi->device_type;
  1799. p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2 / p_cfi->device_type;
  1800. return 1; /* ok */
  1801. }
  1802. /*
  1803. * There is a BIG problem properly ID'ing the JEDEC device and guaranteeing
  1804. * the mapped address, unlock addresses, and proper chip ID. This function
  1805. * attempts to minimize errors. It is doubtfull that this probe will ever
  1806. * be perfect - consequently there should be some module parameters that
  1807. * could be manually specified to force the chip info.
  1808. */
  1809. static inline int jedec_match( uint32_t base,
  1810. struct map_info *map,
  1811. struct cfi_private *cfi,
  1812. const struct amd_flash_info *finfo )
  1813. {
  1814. int rc = 0; /* failure until all tests pass */
  1815. u32 mfr, id;
  1816. uint8_t uaddr;
  1817. /*
  1818. * The IDs must match. For X16 and X32 devices operating in
  1819. * a lower width ( X8 or X16 ), the device ID's are usually just
  1820. * the lower byte(s) of the larger device ID for wider mode. If
  1821. * a part is found that doesn't fit this assumption (device id for
  1822. * smaller width mode is completely unrealated to full-width mode)
  1823. * then the jedec_table[] will have to be augmented with the IDs
  1824. * for different widths.
  1825. */
  1826. switch (cfi->device_type) {
  1827. case CFI_DEVICETYPE_X8:
  1828. mfr = (uint8_t)finfo->mfr_id;
  1829. id = (uint8_t)finfo->dev_id;
  1830. /* bjd: it seems that if we do this, we can end up
  1831. * detecting 16bit flashes as an 8bit device, even though
  1832. * there aren't.
  1833. */
  1834. if (finfo->dev_id > 0xff) {
  1835. DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n",
  1836. __func__);
  1837. goto match_done;
  1838. }
  1839. break;
  1840. case CFI_DEVICETYPE_X16:
  1841. mfr = (uint16_t)finfo->mfr_id;
  1842. id = (uint16_t)finfo->dev_id;
  1843. break;
  1844. case CFI_DEVICETYPE_X32:
  1845. mfr = (uint16_t)finfo->mfr_id;
  1846. id = (uint32_t)finfo->dev_id;
  1847. break;
  1848. default:
  1849. printk(KERN_WARNING
  1850. "MTD %s(): Unsupported device type %d\n",
  1851. __func__, cfi->device_type);
  1852. goto match_done;
  1853. }
  1854. if ( cfi->mfr != mfr || cfi->id != id ) {
  1855. goto match_done;
  1856. }
  1857. /* the part size must fit in the memory window */
  1858. DEBUG( MTD_DEBUG_LEVEL3,
  1859. "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
  1860. __func__, base, 1 << finfo->dev_size, base + (1 << finfo->dev_size) );
  1861. if ( base + cfi_interleave(cfi) * ( 1 << finfo->dev_size ) > map->size ) {
  1862. DEBUG( MTD_DEBUG_LEVEL3,
  1863. "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
  1864. __func__, finfo->mfr_id, finfo->dev_id,
  1865. 1 << finfo->dev_size );
  1866. goto match_done;
  1867. }
  1868. if (! (finfo->devtypes & cfi->device_type))
  1869. goto match_done;
  1870. uaddr = finfo->uaddr;
  1871. DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
  1872. __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
  1873. if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
  1874. && ( unlock_addrs[uaddr].addr1 / cfi->device_type != cfi->addr_unlock1 ||
  1875. unlock_addrs[uaddr].addr2 / cfi->device_type != cfi->addr_unlock2 ) ) {
  1876. DEBUG( MTD_DEBUG_LEVEL3,
  1877. "MTD %s(): 0x%.4x 0x%.4x did not match\n",
  1878. __func__,
  1879. unlock_addrs[uaddr].addr1,
  1880. unlock_addrs[uaddr].addr2);
  1881. goto match_done;
  1882. }
  1883. /*
  1884. * Make sure the ID's dissappear when the device is taken out of
  1885. * ID mode. The only time this should fail when it should succeed
  1886. * is when the ID's are written as data to the same
  1887. * addresses. For this rare and unfortunate case the chip
  1888. * cannot be probed correctly.
  1889. * FIXME - write a driver that takes all of the chip info as
  1890. * module parameters, doesn't probe but forces a load.
  1891. */
  1892. DEBUG( MTD_DEBUG_LEVEL3,
  1893. "MTD %s(): check ID's disappear when not in ID mode\n",
  1894. __func__ );
  1895. jedec_reset( base, map, cfi );
  1896. mfr = jedec_read_mfr( map, base, cfi );
  1897. id = jedec_read_id( map, base, cfi );
  1898. if ( mfr == cfi->mfr && id == cfi->id ) {
  1899. DEBUG( MTD_DEBUG_LEVEL3,
  1900. "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
  1901. "You might need to manually specify JEDEC parameters.\n",
  1902. __func__, cfi->mfr, cfi->id );
  1903. goto match_done;
  1904. }
  1905. /* all tests passed - mark as success */
  1906. rc = 1;
  1907. /*
  1908. * Put the device back in ID mode - only need to do this if we
  1909. * were truly frobbing a real device.
  1910. */
  1911. DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
  1912. if (cfi->addr_unlock1) {
  1913. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1914. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  1915. }
  1916. cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1917. /* FIXME - should have a delay before continuing */
  1918. match_done:
  1919. return rc;
  1920. }
  1921. static int jedec_probe_chip(struct map_info *map, __u32 base,
  1922. unsigned long *chip_map, struct cfi_private *cfi)
  1923. {
  1924. int i;
  1925. enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
  1926. u32 probe_offset1, probe_offset2;
  1927. retry:
  1928. if (!cfi->numchips) {
  1929. uaddr_idx++;
  1930. if (MTD_UADDR_UNNECESSARY == uaddr_idx)
  1931. return 0;
  1932. cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1 / cfi->device_type;
  1933. cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2 / cfi->device_type;
  1934. }
  1935. /* Make certain we aren't probing past the end of map */
  1936. if (base >= map->size) {
  1937. printk(KERN_NOTICE
  1938. "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
  1939. base, map->size -1);
  1940. return 0;
  1941. }
  1942. /* Ensure the unlock addresses we try stay inside the map */
  1943. probe_offset1 = cfi_build_cmd_addr(cfi->addr_unlock1, cfi_interleave(cfi), cfi->device_type);
  1944. probe_offset2 = cfi_build_cmd_addr(cfi->addr_unlock2, cfi_interleave(cfi), cfi->device_type);
  1945. if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
  1946. ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
  1947. goto retry;
  1948. /* Reset */
  1949. jedec_reset(base, map, cfi);
  1950. /* Autoselect Mode */
  1951. if(cfi->addr_unlock1) {
  1952. cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1953. cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
  1954. }
  1955. cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
  1956. /* FIXME - should have a delay before continuing */
  1957. if (!cfi->numchips) {
  1958. /* This is the first time we're called. Set up the CFI
  1959. stuff accordingly and return */
  1960. cfi->mfr = jedec_read_mfr(map, base, cfi);
  1961. cfi->id = jedec_read_id(map, base, cfi);
  1962. DEBUG(MTD_DEBUG_LEVEL3,
  1963. "Search for id:(%02x %02x) interleave(%d) type(%d)\n",
  1964. cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type);
  1965. for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
  1966. if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
  1967. DEBUG( MTD_DEBUG_LEVEL3,
  1968. "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
  1969. __func__, cfi->mfr, cfi->id,
  1970. cfi->addr_unlock1, cfi->addr_unlock2 );
  1971. if (!cfi_jedec_setup(cfi, i))
  1972. return 0;
  1973. goto ok_out;
  1974. }
  1975. }
  1976. goto retry;
  1977. } else {
  1978. uint16_t mfr;
  1979. uint16_t id;
  1980. /* Make sure it is a chip of the same manufacturer and id */
  1981. mfr = jedec_read_mfr(map, base, cfi);
  1982. id = jedec_read_id(map, base, cfi);
  1983. if ((mfr != cfi->mfr) || (id != cfi->id)) {
  1984. printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
  1985. map->name, mfr, id, base);
  1986. jedec_reset(base, map, cfi);
  1987. return 0;
  1988. }
  1989. }
  1990. /* Check each previous chip locations to see if it's an alias */
  1991. for (i=0; i < (base >> cfi->chipshift); i++) {
  1992. unsigned long start;
  1993. if(!test_bit(i, chip_map)) {
  1994. continue; /* Skip location; no valid chip at this address */
  1995. }
  1996. start = i << cfi->chipshift;
  1997. if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
  1998. jedec_read_id(map, start, cfi) == cfi->id) {
  1999. /* Eep. This chip also looks like it's in autoselect mode.
  2000. Is it an alias for the new one? */
  2001. jedec_reset(start, map, cfi);
  2002. /* If the device IDs go away, it's an alias */
  2003. if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
  2004. jedec_read_id(map, base, cfi) != cfi->id) {
  2005. printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
  2006. map->name, base, start);
  2007. return 0;
  2008. }
  2009. /* Yes, it's actually got the device IDs as data. Most
  2010. * unfortunate. Stick the new chip in read mode
  2011. * too and if it's the same, assume it's an alias. */
  2012. /* FIXME: Use other modes to do a proper check */
  2013. jedec_reset(base, map, cfi);
  2014. if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
  2015. jedec_read_id(map, base, cfi) == cfi->id) {
  2016. printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
  2017. map->name, base, start);
  2018. return 0;
  2019. }
  2020. }
  2021. }
  2022. /* OK, if we got to here, then none of the previous chips appear to
  2023. be aliases for the current one. */
  2024. set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
  2025. cfi->numchips++;
  2026. ok_out:
  2027. /* Put it back into Read Mode */
  2028. jedec_reset(base, map, cfi);
  2029. printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
  2030. map->name, cfi_interleave(cfi), cfi->device_type*8, base,
  2031. map->bankwidth*8);
  2032. return 1;
  2033. }
  2034. static struct chip_probe jedec_chip_probe = {
  2035. .name = "JEDEC",
  2036. .probe_chip = jedec_probe_chip
  2037. };
  2038. static struct mtd_info *jedec_probe(struct map_info *map)
  2039. {
  2040. /*
  2041. * Just use the generic probe stuff to call our CFI-specific
  2042. * chip_probe routine in all the possible permutations, etc.
  2043. */
  2044. return mtd_do_chip_probe(map, &jedec_chip_probe);
  2045. }
  2046. static struct mtd_chip_driver jedec_chipdrv = {
  2047. .probe = jedec_probe,
  2048. .name = "jedec_probe",
  2049. .module = THIS_MODULE
  2050. };
  2051. static int __init jedec_probe_init(void)
  2052. {
  2053. register_mtd_chip_driver(&jedec_chipdrv);
  2054. return 0;
  2055. }
  2056. static void __exit jedec_probe_exit(void)
  2057. {
  2058. unregister_mtd_chip_driver(&jedec_chipdrv);
  2059. }
  2060. module_init(jedec_probe_init);
  2061. module_exit(jedec_probe_exit);
  2062. MODULE_LICENSE("GPL");
  2063. MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
  2064. MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");