resource_tracker.c 73 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. };
  72. enum res_qp_states {
  73. RES_QP_BUSY = RES_ANY_BUSY,
  74. /* QP number was allocated */
  75. RES_QP_RESERVED,
  76. /* ICM memory for QP context was mapped */
  77. RES_QP_MAPPED,
  78. /* QP is in hw ownership */
  79. RES_QP_HW
  80. };
  81. struct res_qp {
  82. struct res_common com;
  83. struct res_mtt *mtt;
  84. struct res_cq *rcq;
  85. struct res_cq *scq;
  86. struct res_srq *srq;
  87. struct list_head mcg_list;
  88. spinlock_t mcg_spl;
  89. int local_qpn;
  90. };
  91. enum res_mtt_states {
  92. RES_MTT_BUSY = RES_ANY_BUSY,
  93. RES_MTT_ALLOCATED,
  94. };
  95. static inline const char *mtt_states_str(enum res_mtt_states state)
  96. {
  97. switch (state) {
  98. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  99. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  100. default: return "Unknown";
  101. }
  102. }
  103. struct res_mtt {
  104. struct res_common com;
  105. int order;
  106. atomic_t ref_count;
  107. };
  108. enum res_mpt_states {
  109. RES_MPT_BUSY = RES_ANY_BUSY,
  110. RES_MPT_RESERVED,
  111. RES_MPT_MAPPED,
  112. RES_MPT_HW,
  113. };
  114. struct res_mpt {
  115. struct res_common com;
  116. struct res_mtt *mtt;
  117. int key;
  118. };
  119. enum res_eq_states {
  120. RES_EQ_BUSY = RES_ANY_BUSY,
  121. RES_EQ_RESERVED,
  122. RES_EQ_HW,
  123. };
  124. struct res_eq {
  125. struct res_common com;
  126. struct res_mtt *mtt;
  127. };
  128. enum res_cq_states {
  129. RES_CQ_BUSY = RES_ANY_BUSY,
  130. RES_CQ_ALLOCATED,
  131. RES_CQ_HW,
  132. };
  133. struct res_cq {
  134. struct res_common com;
  135. struct res_mtt *mtt;
  136. atomic_t ref_count;
  137. };
  138. enum res_srq_states {
  139. RES_SRQ_BUSY = RES_ANY_BUSY,
  140. RES_SRQ_ALLOCATED,
  141. RES_SRQ_HW,
  142. };
  143. struct res_srq {
  144. struct res_common com;
  145. struct res_mtt *mtt;
  146. struct res_cq *cq;
  147. atomic_t ref_count;
  148. };
  149. enum res_counter_states {
  150. RES_COUNTER_BUSY = RES_ANY_BUSY,
  151. RES_COUNTER_ALLOCATED,
  152. };
  153. struct res_counter {
  154. struct res_common com;
  155. int port;
  156. };
  157. enum res_xrcdn_states {
  158. RES_XRCD_BUSY = RES_ANY_BUSY,
  159. RES_XRCD_ALLOCATED,
  160. };
  161. struct res_xrcdn {
  162. struct res_common com;
  163. int port;
  164. };
  165. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  166. {
  167. struct rb_node *node = root->rb_node;
  168. while (node) {
  169. struct res_common *res = container_of(node, struct res_common,
  170. node);
  171. if (res_id < res->res_id)
  172. node = node->rb_left;
  173. else if (res_id > res->res_id)
  174. node = node->rb_right;
  175. else
  176. return res;
  177. }
  178. return NULL;
  179. }
  180. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  181. {
  182. struct rb_node **new = &(root->rb_node), *parent = NULL;
  183. /* Figure out where to put new node */
  184. while (*new) {
  185. struct res_common *this = container_of(*new, struct res_common,
  186. node);
  187. parent = *new;
  188. if (res->res_id < this->res_id)
  189. new = &((*new)->rb_left);
  190. else if (res->res_id > this->res_id)
  191. new = &((*new)->rb_right);
  192. else
  193. return -EEXIST;
  194. }
  195. /* Add new node and rebalance tree. */
  196. rb_link_node(&res->node, parent, new);
  197. rb_insert_color(&res->node, root);
  198. return 0;
  199. }
  200. /* For Debug uses */
  201. static const char *ResourceType(enum mlx4_resource rt)
  202. {
  203. switch (rt) {
  204. case RES_QP: return "RES_QP";
  205. case RES_CQ: return "RES_CQ";
  206. case RES_SRQ: return "RES_SRQ";
  207. case RES_MPT: return "RES_MPT";
  208. case RES_MTT: return "RES_MTT";
  209. case RES_MAC: return "RES_MAC";
  210. case RES_EQ: return "RES_EQ";
  211. case RES_COUNTER: return "RES_COUNTER";
  212. case RES_XRCD: return "RES_XRCD";
  213. default: return "Unknown resource type !!!";
  214. };
  215. }
  216. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  217. {
  218. struct mlx4_priv *priv = mlx4_priv(dev);
  219. int i;
  220. int t;
  221. priv->mfunc.master.res_tracker.slave_list =
  222. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  223. GFP_KERNEL);
  224. if (!priv->mfunc.master.res_tracker.slave_list)
  225. return -ENOMEM;
  226. for (i = 0 ; i < dev->num_slaves; i++) {
  227. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  228. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  229. slave_list[i].res_list[t]);
  230. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  231. }
  232. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  233. dev->num_slaves);
  234. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  235. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  236. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  237. return 0 ;
  238. }
  239. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  240. enum mlx4_res_tracker_free_type type)
  241. {
  242. struct mlx4_priv *priv = mlx4_priv(dev);
  243. int i;
  244. if (priv->mfunc.master.res_tracker.slave_list) {
  245. if (type != RES_TR_FREE_STRUCTS_ONLY)
  246. for (i = 0 ; i < dev->num_slaves; i++)
  247. if (type == RES_TR_FREE_ALL ||
  248. dev->caps.function != i)
  249. mlx4_delete_all_resources_for_slave(dev, i);
  250. if (type != RES_TR_FREE_SLAVES_ONLY) {
  251. kfree(priv->mfunc.master.res_tracker.slave_list);
  252. priv->mfunc.master.res_tracker.slave_list = NULL;
  253. }
  254. }
  255. }
  256. static void update_ud_gid(struct mlx4_dev *dev,
  257. struct mlx4_qp_context *qp_ctx, u8 slave)
  258. {
  259. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  260. if (MLX4_QP_ST_UD == ts)
  261. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  262. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  263. slave, qp_ctx->pri_path.mgid_index);
  264. }
  265. static int mpt_mask(struct mlx4_dev *dev)
  266. {
  267. return dev->caps.num_mpts - 1;
  268. }
  269. static void *find_res(struct mlx4_dev *dev, int res_id,
  270. enum mlx4_resource type)
  271. {
  272. struct mlx4_priv *priv = mlx4_priv(dev);
  273. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  274. res_id);
  275. }
  276. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  277. enum mlx4_resource type,
  278. void *res)
  279. {
  280. struct res_common *r;
  281. int err = 0;
  282. spin_lock_irq(mlx4_tlock(dev));
  283. r = find_res(dev, res_id, type);
  284. if (!r) {
  285. err = -ENONET;
  286. goto exit;
  287. }
  288. if (r->state == RES_ANY_BUSY) {
  289. err = -EBUSY;
  290. goto exit;
  291. }
  292. if (r->owner != slave) {
  293. err = -EPERM;
  294. goto exit;
  295. }
  296. r->from_state = r->state;
  297. r->state = RES_ANY_BUSY;
  298. mlx4_dbg(dev, "res %s id 0x%llx to busy\n",
  299. ResourceType(type), r->res_id);
  300. if (res)
  301. *((struct res_common **)res) = r;
  302. exit:
  303. spin_unlock_irq(mlx4_tlock(dev));
  304. return err;
  305. }
  306. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  307. enum mlx4_resource type,
  308. u64 res_id, int *slave)
  309. {
  310. struct res_common *r;
  311. int err = -ENOENT;
  312. int id = res_id;
  313. if (type == RES_QP)
  314. id &= 0x7fffff;
  315. spin_lock(mlx4_tlock(dev));
  316. r = find_res(dev, id, type);
  317. if (r) {
  318. *slave = r->owner;
  319. err = 0;
  320. }
  321. spin_unlock(mlx4_tlock(dev));
  322. return err;
  323. }
  324. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  325. enum mlx4_resource type)
  326. {
  327. struct res_common *r;
  328. spin_lock_irq(mlx4_tlock(dev));
  329. r = find_res(dev, res_id, type);
  330. if (r)
  331. r->state = r->from_state;
  332. spin_unlock_irq(mlx4_tlock(dev));
  333. }
  334. static struct res_common *alloc_qp_tr(int id)
  335. {
  336. struct res_qp *ret;
  337. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  338. if (!ret)
  339. return NULL;
  340. ret->com.res_id = id;
  341. ret->com.state = RES_QP_RESERVED;
  342. ret->local_qpn = id;
  343. INIT_LIST_HEAD(&ret->mcg_list);
  344. spin_lock_init(&ret->mcg_spl);
  345. return &ret->com;
  346. }
  347. static struct res_common *alloc_mtt_tr(int id, int order)
  348. {
  349. struct res_mtt *ret;
  350. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  351. if (!ret)
  352. return NULL;
  353. ret->com.res_id = id;
  354. ret->order = order;
  355. ret->com.state = RES_MTT_ALLOCATED;
  356. atomic_set(&ret->ref_count, 0);
  357. return &ret->com;
  358. }
  359. static struct res_common *alloc_mpt_tr(int id, int key)
  360. {
  361. struct res_mpt *ret;
  362. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  363. if (!ret)
  364. return NULL;
  365. ret->com.res_id = id;
  366. ret->com.state = RES_MPT_RESERVED;
  367. ret->key = key;
  368. return &ret->com;
  369. }
  370. static struct res_common *alloc_eq_tr(int id)
  371. {
  372. struct res_eq *ret;
  373. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  374. if (!ret)
  375. return NULL;
  376. ret->com.res_id = id;
  377. ret->com.state = RES_EQ_RESERVED;
  378. return &ret->com;
  379. }
  380. static struct res_common *alloc_cq_tr(int id)
  381. {
  382. struct res_cq *ret;
  383. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  384. if (!ret)
  385. return NULL;
  386. ret->com.res_id = id;
  387. ret->com.state = RES_CQ_ALLOCATED;
  388. atomic_set(&ret->ref_count, 0);
  389. return &ret->com;
  390. }
  391. static struct res_common *alloc_srq_tr(int id)
  392. {
  393. struct res_srq *ret;
  394. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  395. if (!ret)
  396. return NULL;
  397. ret->com.res_id = id;
  398. ret->com.state = RES_SRQ_ALLOCATED;
  399. atomic_set(&ret->ref_count, 0);
  400. return &ret->com;
  401. }
  402. static struct res_common *alloc_counter_tr(int id)
  403. {
  404. struct res_counter *ret;
  405. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  406. if (!ret)
  407. return NULL;
  408. ret->com.res_id = id;
  409. ret->com.state = RES_COUNTER_ALLOCATED;
  410. return &ret->com;
  411. }
  412. static struct res_common *alloc_xrcdn_tr(int id)
  413. {
  414. struct res_xrcdn *ret;
  415. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  416. if (!ret)
  417. return NULL;
  418. ret->com.res_id = id;
  419. ret->com.state = RES_XRCD_ALLOCATED;
  420. return &ret->com;
  421. }
  422. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  423. int extra)
  424. {
  425. struct res_common *ret;
  426. switch (type) {
  427. case RES_QP:
  428. ret = alloc_qp_tr(id);
  429. break;
  430. case RES_MPT:
  431. ret = alloc_mpt_tr(id, extra);
  432. break;
  433. case RES_MTT:
  434. ret = alloc_mtt_tr(id, extra);
  435. break;
  436. case RES_EQ:
  437. ret = alloc_eq_tr(id);
  438. break;
  439. case RES_CQ:
  440. ret = alloc_cq_tr(id);
  441. break;
  442. case RES_SRQ:
  443. ret = alloc_srq_tr(id);
  444. break;
  445. case RES_MAC:
  446. printk(KERN_ERR "implementation missing\n");
  447. return NULL;
  448. case RES_COUNTER:
  449. ret = alloc_counter_tr(id);
  450. break;
  451. case RES_XRCD:
  452. ret = alloc_xrcdn_tr(id);
  453. break;
  454. default:
  455. return NULL;
  456. }
  457. if (ret)
  458. ret->owner = slave;
  459. return ret;
  460. }
  461. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  462. enum mlx4_resource type, int extra)
  463. {
  464. int i;
  465. int err;
  466. struct mlx4_priv *priv = mlx4_priv(dev);
  467. struct res_common **res_arr;
  468. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  469. struct rb_root *root = &tracker->res_tree[type];
  470. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  471. if (!res_arr)
  472. return -ENOMEM;
  473. for (i = 0; i < count; ++i) {
  474. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  475. if (!res_arr[i]) {
  476. for (--i; i >= 0; --i)
  477. kfree(res_arr[i]);
  478. kfree(res_arr);
  479. return -ENOMEM;
  480. }
  481. }
  482. spin_lock_irq(mlx4_tlock(dev));
  483. for (i = 0; i < count; ++i) {
  484. if (find_res(dev, base + i, type)) {
  485. err = -EEXIST;
  486. goto undo;
  487. }
  488. err = res_tracker_insert(root, res_arr[i]);
  489. if (err)
  490. goto undo;
  491. list_add_tail(&res_arr[i]->list,
  492. &tracker->slave_list[slave].res_list[type]);
  493. }
  494. spin_unlock_irq(mlx4_tlock(dev));
  495. kfree(res_arr);
  496. return 0;
  497. undo:
  498. for (--i; i >= base; --i)
  499. rb_erase(&res_arr[i]->node, root);
  500. spin_unlock_irq(mlx4_tlock(dev));
  501. for (i = 0; i < count; ++i)
  502. kfree(res_arr[i]);
  503. kfree(res_arr);
  504. return err;
  505. }
  506. static int remove_qp_ok(struct res_qp *res)
  507. {
  508. if (res->com.state == RES_QP_BUSY)
  509. return -EBUSY;
  510. else if (res->com.state != RES_QP_RESERVED)
  511. return -EPERM;
  512. return 0;
  513. }
  514. static int remove_mtt_ok(struct res_mtt *res, int order)
  515. {
  516. if (res->com.state == RES_MTT_BUSY ||
  517. atomic_read(&res->ref_count)) {
  518. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  519. __func__, __LINE__,
  520. mtt_states_str(res->com.state),
  521. atomic_read(&res->ref_count));
  522. return -EBUSY;
  523. } else if (res->com.state != RES_MTT_ALLOCATED)
  524. return -EPERM;
  525. else if (res->order != order)
  526. return -EINVAL;
  527. return 0;
  528. }
  529. static int remove_mpt_ok(struct res_mpt *res)
  530. {
  531. if (res->com.state == RES_MPT_BUSY)
  532. return -EBUSY;
  533. else if (res->com.state != RES_MPT_RESERVED)
  534. return -EPERM;
  535. return 0;
  536. }
  537. static int remove_eq_ok(struct res_eq *res)
  538. {
  539. if (res->com.state == RES_MPT_BUSY)
  540. return -EBUSY;
  541. else if (res->com.state != RES_MPT_RESERVED)
  542. return -EPERM;
  543. return 0;
  544. }
  545. static int remove_counter_ok(struct res_counter *res)
  546. {
  547. if (res->com.state == RES_COUNTER_BUSY)
  548. return -EBUSY;
  549. else if (res->com.state != RES_COUNTER_ALLOCATED)
  550. return -EPERM;
  551. return 0;
  552. }
  553. static int remove_xrcdn_ok(struct res_xrcdn *res)
  554. {
  555. if (res->com.state == RES_XRCD_BUSY)
  556. return -EBUSY;
  557. else if (res->com.state != RES_XRCD_ALLOCATED)
  558. return -EPERM;
  559. return 0;
  560. }
  561. static int remove_cq_ok(struct res_cq *res)
  562. {
  563. if (res->com.state == RES_CQ_BUSY)
  564. return -EBUSY;
  565. else if (res->com.state != RES_CQ_ALLOCATED)
  566. return -EPERM;
  567. return 0;
  568. }
  569. static int remove_srq_ok(struct res_srq *res)
  570. {
  571. if (res->com.state == RES_SRQ_BUSY)
  572. return -EBUSY;
  573. else if (res->com.state != RES_SRQ_ALLOCATED)
  574. return -EPERM;
  575. return 0;
  576. }
  577. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  578. {
  579. switch (type) {
  580. case RES_QP:
  581. return remove_qp_ok((struct res_qp *)res);
  582. case RES_CQ:
  583. return remove_cq_ok((struct res_cq *)res);
  584. case RES_SRQ:
  585. return remove_srq_ok((struct res_srq *)res);
  586. case RES_MPT:
  587. return remove_mpt_ok((struct res_mpt *)res);
  588. case RES_MTT:
  589. return remove_mtt_ok((struct res_mtt *)res, extra);
  590. case RES_MAC:
  591. return -ENOSYS;
  592. case RES_EQ:
  593. return remove_eq_ok((struct res_eq *)res);
  594. case RES_COUNTER:
  595. return remove_counter_ok((struct res_counter *)res);
  596. case RES_XRCD:
  597. return remove_xrcdn_ok((struct res_xrcdn *)res);
  598. default:
  599. return -EINVAL;
  600. }
  601. }
  602. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  603. enum mlx4_resource type, int extra)
  604. {
  605. u64 i;
  606. int err;
  607. struct mlx4_priv *priv = mlx4_priv(dev);
  608. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  609. struct res_common *r;
  610. spin_lock_irq(mlx4_tlock(dev));
  611. for (i = base; i < base + count; ++i) {
  612. r = res_tracker_lookup(&tracker->res_tree[type], i);
  613. if (!r) {
  614. err = -ENOENT;
  615. goto out;
  616. }
  617. if (r->owner != slave) {
  618. err = -EPERM;
  619. goto out;
  620. }
  621. err = remove_ok(r, type, extra);
  622. if (err)
  623. goto out;
  624. }
  625. for (i = base; i < base + count; ++i) {
  626. r = res_tracker_lookup(&tracker->res_tree[type], i);
  627. rb_erase(&r->node, &tracker->res_tree[type]);
  628. list_del(&r->list);
  629. kfree(r);
  630. }
  631. err = 0;
  632. out:
  633. spin_unlock_irq(mlx4_tlock(dev));
  634. return err;
  635. }
  636. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  637. enum res_qp_states state, struct res_qp **qp,
  638. int alloc)
  639. {
  640. struct mlx4_priv *priv = mlx4_priv(dev);
  641. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  642. struct res_qp *r;
  643. int err = 0;
  644. spin_lock_irq(mlx4_tlock(dev));
  645. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  646. if (!r)
  647. err = -ENOENT;
  648. else if (r->com.owner != slave)
  649. err = -EPERM;
  650. else {
  651. switch (state) {
  652. case RES_QP_BUSY:
  653. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  654. __func__, r->com.res_id);
  655. err = -EBUSY;
  656. break;
  657. case RES_QP_RESERVED:
  658. if (r->com.state == RES_QP_MAPPED && !alloc)
  659. break;
  660. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  661. err = -EINVAL;
  662. break;
  663. case RES_QP_MAPPED:
  664. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  665. r->com.state == RES_QP_HW)
  666. break;
  667. else {
  668. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  669. r->com.res_id);
  670. err = -EINVAL;
  671. }
  672. break;
  673. case RES_QP_HW:
  674. if (r->com.state != RES_QP_MAPPED)
  675. err = -EINVAL;
  676. break;
  677. default:
  678. err = -EINVAL;
  679. }
  680. if (!err) {
  681. r->com.from_state = r->com.state;
  682. r->com.to_state = state;
  683. r->com.state = RES_QP_BUSY;
  684. if (qp)
  685. *qp = r;
  686. }
  687. }
  688. spin_unlock_irq(mlx4_tlock(dev));
  689. return err;
  690. }
  691. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  692. enum res_mpt_states state, struct res_mpt **mpt)
  693. {
  694. struct mlx4_priv *priv = mlx4_priv(dev);
  695. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  696. struct res_mpt *r;
  697. int err = 0;
  698. spin_lock_irq(mlx4_tlock(dev));
  699. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  700. if (!r)
  701. err = -ENOENT;
  702. else if (r->com.owner != slave)
  703. err = -EPERM;
  704. else {
  705. switch (state) {
  706. case RES_MPT_BUSY:
  707. err = -EINVAL;
  708. break;
  709. case RES_MPT_RESERVED:
  710. if (r->com.state != RES_MPT_MAPPED)
  711. err = -EINVAL;
  712. break;
  713. case RES_MPT_MAPPED:
  714. if (r->com.state != RES_MPT_RESERVED &&
  715. r->com.state != RES_MPT_HW)
  716. err = -EINVAL;
  717. break;
  718. case RES_MPT_HW:
  719. if (r->com.state != RES_MPT_MAPPED)
  720. err = -EINVAL;
  721. break;
  722. default:
  723. err = -EINVAL;
  724. }
  725. if (!err) {
  726. r->com.from_state = r->com.state;
  727. r->com.to_state = state;
  728. r->com.state = RES_MPT_BUSY;
  729. if (mpt)
  730. *mpt = r;
  731. }
  732. }
  733. spin_unlock_irq(mlx4_tlock(dev));
  734. return err;
  735. }
  736. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  737. enum res_eq_states state, struct res_eq **eq)
  738. {
  739. struct mlx4_priv *priv = mlx4_priv(dev);
  740. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  741. struct res_eq *r;
  742. int err = 0;
  743. spin_lock_irq(mlx4_tlock(dev));
  744. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  745. if (!r)
  746. err = -ENOENT;
  747. else if (r->com.owner != slave)
  748. err = -EPERM;
  749. else {
  750. switch (state) {
  751. case RES_EQ_BUSY:
  752. err = -EINVAL;
  753. break;
  754. case RES_EQ_RESERVED:
  755. if (r->com.state != RES_EQ_HW)
  756. err = -EINVAL;
  757. break;
  758. case RES_EQ_HW:
  759. if (r->com.state != RES_EQ_RESERVED)
  760. err = -EINVAL;
  761. break;
  762. default:
  763. err = -EINVAL;
  764. }
  765. if (!err) {
  766. r->com.from_state = r->com.state;
  767. r->com.to_state = state;
  768. r->com.state = RES_EQ_BUSY;
  769. if (eq)
  770. *eq = r;
  771. }
  772. }
  773. spin_unlock_irq(mlx4_tlock(dev));
  774. return err;
  775. }
  776. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  777. enum res_cq_states state, struct res_cq **cq)
  778. {
  779. struct mlx4_priv *priv = mlx4_priv(dev);
  780. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  781. struct res_cq *r;
  782. int err;
  783. spin_lock_irq(mlx4_tlock(dev));
  784. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  785. if (!r)
  786. err = -ENOENT;
  787. else if (r->com.owner != slave)
  788. err = -EPERM;
  789. else {
  790. switch (state) {
  791. case RES_CQ_BUSY:
  792. err = -EBUSY;
  793. break;
  794. case RES_CQ_ALLOCATED:
  795. if (r->com.state != RES_CQ_HW)
  796. err = -EINVAL;
  797. else if (atomic_read(&r->ref_count))
  798. err = -EBUSY;
  799. else
  800. err = 0;
  801. break;
  802. case RES_CQ_HW:
  803. if (r->com.state != RES_CQ_ALLOCATED)
  804. err = -EINVAL;
  805. else
  806. err = 0;
  807. break;
  808. default:
  809. err = -EINVAL;
  810. }
  811. if (!err) {
  812. r->com.from_state = r->com.state;
  813. r->com.to_state = state;
  814. r->com.state = RES_CQ_BUSY;
  815. if (cq)
  816. *cq = r;
  817. }
  818. }
  819. spin_unlock_irq(mlx4_tlock(dev));
  820. return err;
  821. }
  822. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  823. enum res_cq_states state, struct res_srq **srq)
  824. {
  825. struct mlx4_priv *priv = mlx4_priv(dev);
  826. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  827. struct res_srq *r;
  828. int err = 0;
  829. spin_lock_irq(mlx4_tlock(dev));
  830. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  831. if (!r)
  832. err = -ENOENT;
  833. else if (r->com.owner != slave)
  834. err = -EPERM;
  835. else {
  836. switch (state) {
  837. case RES_SRQ_BUSY:
  838. err = -EINVAL;
  839. break;
  840. case RES_SRQ_ALLOCATED:
  841. if (r->com.state != RES_SRQ_HW)
  842. err = -EINVAL;
  843. else if (atomic_read(&r->ref_count))
  844. err = -EBUSY;
  845. break;
  846. case RES_SRQ_HW:
  847. if (r->com.state != RES_SRQ_ALLOCATED)
  848. err = -EINVAL;
  849. break;
  850. default:
  851. err = -EINVAL;
  852. }
  853. if (!err) {
  854. r->com.from_state = r->com.state;
  855. r->com.to_state = state;
  856. r->com.state = RES_SRQ_BUSY;
  857. if (srq)
  858. *srq = r;
  859. }
  860. }
  861. spin_unlock_irq(mlx4_tlock(dev));
  862. return err;
  863. }
  864. static void res_abort_move(struct mlx4_dev *dev, int slave,
  865. enum mlx4_resource type, int id)
  866. {
  867. struct mlx4_priv *priv = mlx4_priv(dev);
  868. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  869. struct res_common *r;
  870. spin_lock_irq(mlx4_tlock(dev));
  871. r = res_tracker_lookup(&tracker->res_tree[type], id);
  872. if (r && (r->owner == slave))
  873. r->state = r->from_state;
  874. spin_unlock_irq(mlx4_tlock(dev));
  875. }
  876. static void res_end_move(struct mlx4_dev *dev, int slave,
  877. enum mlx4_resource type, int id)
  878. {
  879. struct mlx4_priv *priv = mlx4_priv(dev);
  880. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  881. struct res_common *r;
  882. spin_lock_irq(mlx4_tlock(dev));
  883. r = res_tracker_lookup(&tracker->res_tree[type], id);
  884. if (r && (r->owner == slave))
  885. r->state = r->to_state;
  886. spin_unlock_irq(mlx4_tlock(dev));
  887. }
  888. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  889. {
  890. return mlx4_is_qp_reserved(dev, qpn);
  891. }
  892. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  893. u64 in_param, u64 *out_param)
  894. {
  895. int err;
  896. int count;
  897. int align;
  898. int base;
  899. int qpn;
  900. switch (op) {
  901. case RES_OP_RESERVE:
  902. count = get_param_l(&in_param);
  903. align = get_param_h(&in_param);
  904. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  905. if (err)
  906. return err;
  907. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  908. if (err) {
  909. __mlx4_qp_release_range(dev, base, count);
  910. return err;
  911. }
  912. set_param_l(out_param, base);
  913. break;
  914. case RES_OP_MAP_ICM:
  915. qpn = get_param_l(&in_param) & 0x7fffff;
  916. if (valid_reserved(dev, slave, qpn)) {
  917. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  918. if (err)
  919. return err;
  920. }
  921. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  922. NULL, 1);
  923. if (err)
  924. return err;
  925. if (!valid_reserved(dev, slave, qpn)) {
  926. err = __mlx4_qp_alloc_icm(dev, qpn);
  927. if (err) {
  928. res_abort_move(dev, slave, RES_QP, qpn);
  929. return err;
  930. }
  931. }
  932. res_end_move(dev, slave, RES_QP, qpn);
  933. break;
  934. default:
  935. err = -EINVAL;
  936. break;
  937. }
  938. return err;
  939. }
  940. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  941. u64 in_param, u64 *out_param)
  942. {
  943. int err = -EINVAL;
  944. int base;
  945. int order;
  946. if (op != RES_OP_RESERVE_AND_MAP)
  947. return err;
  948. order = get_param_l(&in_param);
  949. base = __mlx4_alloc_mtt_range(dev, order);
  950. if (base == -1)
  951. return -ENOMEM;
  952. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  953. if (err)
  954. __mlx4_free_mtt_range(dev, base, order);
  955. else
  956. set_param_l(out_param, base);
  957. return err;
  958. }
  959. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  960. u64 in_param, u64 *out_param)
  961. {
  962. int err = -EINVAL;
  963. int index;
  964. int id;
  965. struct res_mpt *mpt;
  966. switch (op) {
  967. case RES_OP_RESERVE:
  968. index = __mlx4_mr_reserve(dev);
  969. if (index == -1)
  970. break;
  971. id = index & mpt_mask(dev);
  972. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  973. if (err) {
  974. __mlx4_mr_release(dev, index);
  975. break;
  976. }
  977. set_param_l(out_param, index);
  978. break;
  979. case RES_OP_MAP_ICM:
  980. index = get_param_l(&in_param);
  981. id = index & mpt_mask(dev);
  982. err = mr_res_start_move_to(dev, slave, id,
  983. RES_MPT_MAPPED, &mpt);
  984. if (err)
  985. return err;
  986. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  987. if (err) {
  988. res_abort_move(dev, slave, RES_MPT, id);
  989. return err;
  990. }
  991. res_end_move(dev, slave, RES_MPT, id);
  992. break;
  993. }
  994. return err;
  995. }
  996. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  997. u64 in_param, u64 *out_param)
  998. {
  999. int cqn;
  1000. int err;
  1001. switch (op) {
  1002. case RES_OP_RESERVE_AND_MAP:
  1003. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1004. if (err)
  1005. break;
  1006. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1007. if (err) {
  1008. __mlx4_cq_free_icm(dev, cqn);
  1009. break;
  1010. }
  1011. set_param_l(out_param, cqn);
  1012. break;
  1013. default:
  1014. err = -EINVAL;
  1015. }
  1016. return err;
  1017. }
  1018. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1019. u64 in_param, u64 *out_param)
  1020. {
  1021. int srqn;
  1022. int err;
  1023. switch (op) {
  1024. case RES_OP_RESERVE_AND_MAP:
  1025. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1026. if (err)
  1027. break;
  1028. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1029. if (err) {
  1030. __mlx4_srq_free_icm(dev, srqn);
  1031. break;
  1032. }
  1033. set_param_l(out_param, srqn);
  1034. break;
  1035. default:
  1036. err = -EINVAL;
  1037. }
  1038. return err;
  1039. }
  1040. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1041. {
  1042. struct mlx4_priv *priv = mlx4_priv(dev);
  1043. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1044. struct mac_res *res;
  1045. res = kzalloc(sizeof *res, GFP_KERNEL);
  1046. if (!res)
  1047. return -ENOMEM;
  1048. res->mac = mac;
  1049. res->port = (u8) port;
  1050. list_add_tail(&res->list,
  1051. &tracker->slave_list[slave].res_list[RES_MAC]);
  1052. return 0;
  1053. }
  1054. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1055. int port)
  1056. {
  1057. struct mlx4_priv *priv = mlx4_priv(dev);
  1058. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1059. struct list_head *mac_list =
  1060. &tracker->slave_list[slave].res_list[RES_MAC];
  1061. struct mac_res *res, *tmp;
  1062. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1063. if (res->mac == mac && res->port == (u8) port) {
  1064. list_del(&res->list);
  1065. kfree(res);
  1066. break;
  1067. }
  1068. }
  1069. }
  1070. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1071. {
  1072. struct mlx4_priv *priv = mlx4_priv(dev);
  1073. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1074. struct list_head *mac_list =
  1075. &tracker->slave_list[slave].res_list[RES_MAC];
  1076. struct mac_res *res, *tmp;
  1077. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1078. list_del(&res->list);
  1079. __mlx4_unregister_mac(dev, res->port, res->mac);
  1080. kfree(res);
  1081. }
  1082. }
  1083. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1084. u64 in_param, u64 *out_param)
  1085. {
  1086. int err = -EINVAL;
  1087. int port;
  1088. u64 mac;
  1089. if (op != RES_OP_RESERVE_AND_MAP)
  1090. return err;
  1091. port = get_param_l(out_param);
  1092. mac = in_param;
  1093. err = __mlx4_register_mac(dev, port, mac);
  1094. if (err >= 0) {
  1095. set_param_l(out_param, err);
  1096. err = 0;
  1097. }
  1098. if (!err) {
  1099. err = mac_add_to_slave(dev, slave, mac, port);
  1100. if (err)
  1101. __mlx4_unregister_mac(dev, port, mac);
  1102. }
  1103. return err;
  1104. }
  1105. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1106. u64 in_param, u64 *out_param)
  1107. {
  1108. return 0;
  1109. }
  1110. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1111. u64 in_param, u64 *out_param)
  1112. {
  1113. u32 index;
  1114. int err;
  1115. if (op != RES_OP_RESERVE)
  1116. return -EINVAL;
  1117. err = __mlx4_counter_alloc(dev, &index);
  1118. if (err)
  1119. return err;
  1120. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1121. if (err)
  1122. __mlx4_counter_free(dev, index);
  1123. else
  1124. set_param_l(out_param, index);
  1125. return err;
  1126. }
  1127. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1128. u64 in_param, u64 *out_param)
  1129. {
  1130. u32 xrcdn;
  1131. int err;
  1132. if (op != RES_OP_RESERVE)
  1133. return -EINVAL;
  1134. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1135. if (err)
  1136. return err;
  1137. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1138. if (err)
  1139. __mlx4_xrcd_free(dev, xrcdn);
  1140. else
  1141. set_param_l(out_param, xrcdn);
  1142. return err;
  1143. }
  1144. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1145. struct mlx4_vhcr *vhcr,
  1146. struct mlx4_cmd_mailbox *inbox,
  1147. struct mlx4_cmd_mailbox *outbox,
  1148. struct mlx4_cmd_info *cmd)
  1149. {
  1150. int err;
  1151. int alop = vhcr->op_modifier;
  1152. switch (vhcr->in_modifier) {
  1153. case RES_QP:
  1154. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1155. vhcr->in_param, &vhcr->out_param);
  1156. break;
  1157. case RES_MTT:
  1158. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1159. vhcr->in_param, &vhcr->out_param);
  1160. break;
  1161. case RES_MPT:
  1162. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1163. vhcr->in_param, &vhcr->out_param);
  1164. break;
  1165. case RES_CQ:
  1166. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1167. vhcr->in_param, &vhcr->out_param);
  1168. break;
  1169. case RES_SRQ:
  1170. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1171. vhcr->in_param, &vhcr->out_param);
  1172. break;
  1173. case RES_MAC:
  1174. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1175. vhcr->in_param, &vhcr->out_param);
  1176. break;
  1177. case RES_VLAN:
  1178. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1179. vhcr->in_param, &vhcr->out_param);
  1180. break;
  1181. case RES_COUNTER:
  1182. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1183. vhcr->in_param, &vhcr->out_param);
  1184. break;
  1185. case RES_XRCD:
  1186. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1187. vhcr->in_param, &vhcr->out_param);
  1188. break;
  1189. default:
  1190. err = -EINVAL;
  1191. break;
  1192. }
  1193. return err;
  1194. }
  1195. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1196. u64 in_param)
  1197. {
  1198. int err;
  1199. int count;
  1200. int base;
  1201. int qpn;
  1202. switch (op) {
  1203. case RES_OP_RESERVE:
  1204. base = get_param_l(&in_param) & 0x7fffff;
  1205. count = get_param_h(&in_param);
  1206. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1207. if (err)
  1208. break;
  1209. __mlx4_qp_release_range(dev, base, count);
  1210. break;
  1211. case RES_OP_MAP_ICM:
  1212. qpn = get_param_l(&in_param) & 0x7fffff;
  1213. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1214. NULL, 0);
  1215. if (err)
  1216. return err;
  1217. if (!valid_reserved(dev, slave, qpn))
  1218. __mlx4_qp_free_icm(dev, qpn);
  1219. res_end_move(dev, slave, RES_QP, qpn);
  1220. if (valid_reserved(dev, slave, qpn))
  1221. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1222. break;
  1223. default:
  1224. err = -EINVAL;
  1225. break;
  1226. }
  1227. return err;
  1228. }
  1229. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1230. u64 in_param, u64 *out_param)
  1231. {
  1232. int err = -EINVAL;
  1233. int base;
  1234. int order;
  1235. if (op != RES_OP_RESERVE_AND_MAP)
  1236. return err;
  1237. base = get_param_l(&in_param);
  1238. order = get_param_h(&in_param);
  1239. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1240. if (!err)
  1241. __mlx4_free_mtt_range(dev, base, order);
  1242. return err;
  1243. }
  1244. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1245. u64 in_param)
  1246. {
  1247. int err = -EINVAL;
  1248. int index;
  1249. int id;
  1250. struct res_mpt *mpt;
  1251. switch (op) {
  1252. case RES_OP_RESERVE:
  1253. index = get_param_l(&in_param);
  1254. id = index & mpt_mask(dev);
  1255. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1256. if (err)
  1257. break;
  1258. index = mpt->key;
  1259. put_res(dev, slave, id, RES_MPT);
  1260. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1261. if (err)
  1262. break;
  1263. __mlx4_mr_release(dev, index);
  1264. break;
  1265. case RES_OP_MAP_ICM:
  1266. index = get_param_l(&in_param);
  1267. id = index & mpt_mask(dev);
  1268. err = mr_res_start_move_to(dev, slave, id,
  1269. RES_MPT_RESERVED, &mpt);
  1270. if (err)
  1271. return err;
  1272. __mlx4_mr_free_icm(dev, mpt->key);
  1273. res_end_move(dev, slave, RES_MPT, id);
  1274. return err;
  1275. break;
  1276. default:
  1277. err = -EINVAL;
  1278. break;
  1279. }
  1280. return err;
  1281. }
  1282. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1283. u64 in_param, u64 *out_param)
  1284. {
  1285. int cqn;
  1286. int err;
  1287. switch (op) {
  1288. case RES_OP_RESERVE_AND_MAP:
  1289. cqn = get_param_l(&in_param);
  1290. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1291. if (err)
  1292. break;
  1293. __mlx4_cq_free_icm(dev, cqn);
  1294. break;
  1295. default:
  1296. err = -EINVAL;
  1297. break;
  1298. }
  1299. return err;
  1300. }
  1301. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1302. u64 in_param, u64 *out_param)
  1303. {
  1304. int srqn;
  1305. int err;
  1306. switch (op) {
  1307. case RES_OP_RESERVE_AND_MAP:
  1308. srqn = get_param_l(&in_param);
  1309. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1310. if (err)
  1311. break;
  1312. __mlx4_srq_free_icm(dev, srqn);
  1313. break;
  1314. default:
  1315. err = -EINVAL;
  1316. break;
  1317. }
  1318. return err;
  1319. }
  1320. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1321. u64 in_param, u64 *out_param)
  1322. {
  1323. int port;
  1324. int err = 0;
  1325. switch (op) {
  1326. case RES_OP_RESERVE_AND_MAP:
  1327. port = get_param_l(out_param);
  1328. mac_del_from_slave(dev, slave, in_param, port);
  1329. __mlx4_unregister_mac(dev, port, in_param);
  1330. break;
  1331. default:
  1332. err = -EINVAL;
  1333. break;
  1334. }
  1335. return err;
  1336. }
  1337. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1338. u64 in_param, u64 *out_param)
  1339. {
  1340. return 0;
  1341. }
  1342. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1343. u64 in_param, u64 *out_param)
  1344. {
  1345. int index;
  1346. int err;
  1347. if (op != RES_OP_RESERVE)
  1348. return -EINVAL;
  1349. index = get_param_l(&in_param);
  1350. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1351. if (err)
  1352. return err;
  1353. __mlx4_counter_free(dev, index);
  1354. return err;
  1355. }
  1356. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1357. u64 in_param, u64 *out_param)
  1358. {
  1359. int xrcdn;
  1360. int err;
  1361. if (op != RES_OP_RESERVE)
  1362. return -EINVAL;
  1363. xrcdn = get_param_l(&in_param);
  1364. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1365. if (err)
  1366. return err;
  1367. __mlx4_xrcd_free(dev, xrcdn);
  1368. return err;
  1369. }
  1370. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1371. struct mlx4_vhcr *vhcr,
  1372. struct mlx4_cmd_mailbox *inbox,
  1373. struct mlx4_cmd_mailbox *outbox,
  1374. struct mlx4_cmd_info *cmd)
  1375. {
  1376. int err = -EINVAL;
  1377. int alop = vhcr->op_modifier;
  1378. switch (vhcr->in_modifier) {
  1379. case RES_QP:
  1380. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1381. vhcr->in_param);
  1382. break;
  1383. case RES_MTT:
  1384. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1385. vhcr->in_param, &vhcr->out_param);
  1386. break;
  1387. case RES_MPT:
  1388. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1389. vhcr->in_param);
  1390. break;
  1391. case RES_CQ:
  1392. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1393. vhcr->in_param, &vhcr->out_param);
  1394. break;
  1395. case RES_SRQ:
  1396. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1397. vhcr->in_param, &vhcr->out_param);
  1398. break;
  1399. case RES_MAC:
  1400. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1401. vhcr->in_param, &vhcr->out_param);
  1402. break;
  1403. case RES_VLAN:
  1404. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1405. vhcr->in_param, &vhcr->out_param);
  1406. break;
  1407. case RES_COUNTER:
  1408. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1409. vhcr->in_param, &vhcr->out_param);
  1410. break;
  1411. case RES_XRCD:
  1412. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1413. vhcr->in_param, &vhcr->out_param);
  1414. default:
  1415. break;
  1416. }
  1417. return err;
  1418. }
  1419. /* ugly but other choices are uglier */
  1420. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1421. {
  1422. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1423. }
  1424. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1425. {
  1426. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1427. }
  1428. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1429. {
  1430. return be32_to_cpu(mpt->mtt_sz);
  1431. }
  1432. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1433. {
  1434. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1435. }
  1436. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1437. {
  1438. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1439. }
  1440. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1441. {
  1442. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1443. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1444. int log_sq_sride = qpc->sq_size_stride & 7;
  1445. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1446. int log_rq_stride = qpc->rq_size_stride & 7;
  1447. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1448. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1449. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1450. int sq_size;
  1451. int rq_size;
  1452. int total_pages;
  1453. int total_mem;
  1454. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1455. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1456. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1457. total_mem = sq_size + rq_size;
  1458. total_pages =
  1459. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1460. page_shift);
  1461. return total_pages;
  1462. }
  1463. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1464. int size, struct res_mtt *mtt)
  1465. {
  1466. int res_start = mtt->com.res_id;
  1467. int res_size = (1 << mtt->order);
  1468. if (start < res_start || start + size > res_start + res_size)
  1469. return -EPERM;
  1470. return 0;
  1471. }
  1472. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1473. struct mlx4_vhcr *vhcr,
  1474. struct mlx4_cmd_mailbox *inbox,
  1475. struct mlx4_cmd_mailbox *outbox,
  1476. struct mlx4_cmd_info *cmd)
  1477. {
  1478. int err;
  1479. int index = vhcr->in_modifier;
  1480. struct res_mtt *mtt;
  1481. struct res_mpt *mpt;
  1482. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1483. int phys;
  1484. int id;
  1485. id = index & mpt_mask(dev);
  1486. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1487. if (err)
  1488. return err;
  1489. phys = mr_phys_mpt(inbox->buf);
  1490. if (!phys) {
  1491. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1492. if (err)
  1493. goto ex_abort;
  1494. err = check_mtt_range(dev, slave, mtt_base,
  1495. mr_get_mtt_size(inbox->buf), mtt);
  1496. if (err)
  1497. goto ex_put;
  1498. mpt->mtt = mtt;
  1499. }
  1500. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1501. if (err)
  1502. goto ex_put;
  1503. if (!phys) {
  1504. atomic_inc(&mtt->ref_count);
  1505. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1506. }
  1507. res_end_move(dev, slave, RES_MPT, id);
  1508. return 0;
  1509. ex_put:
  1510. if (!phys)
  1511. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1512. ex_abort:
  1513. res_abort_move(dev, slave, RES_MPT, id);
  1514. return err;
  1515. }
  1516. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1517. struct mlx4_vhcr *vhcr,
  1518. struct mlx4_cmd_mailbox *inbox,
  1519. struct mlx4_cmd_mailbox *outbox,
  1520. struct mlx4_cmd_info *cmd)
  1521. {
  1522. int err;
  1523. int index = vhcr->in_modifier;
  1524. struct res_mpt *mpt;
  1525. int id;
  1526. id = index & mpt_mask(dev);
  1527. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1528. if (err)
  1529. return err;
  1530. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1531. if (err)
  1532. goto ex_abort;
  1533. if (mpt->mtt)
  1534. atomic_dec(&mpt->mtt->ref_count);
  1535. res_end_move(dev, slave, RES_MPT, id);
  1536. return 0;
  1537. ex_abort:
  1538. res_abort_move(dev, slave, RES_MPT, id);
  1539. return err;
  1540. }
  1541. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1542. struct mlx4_vhcr *vhcr,
  1543. struct mlx4_cmd_mailbox *inbox,
  1544. struct mlx4_cmd_mailbox *outbox,
  1545. struct mlx4_cmd_info *cmd)
  1546. {
  1547. int err;
  1548. int index = vhcr->in_modifier;
  1549. struct res_mpt *mpt;
  1550. int id;
  1551. id = index & mpt_mask(dev);
  1552. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1553. if (err)
  1554. return err;
  1555. if (mpt->com.from_state != RES_MPT_HW) {
  1556. err = -EBUSY;
  1557. goto out;
  1558. }
  1559. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1560. out:
  1561. put_res(dev, slave, id, RES_MPT);
  1562. return err;
  1563. }
  1564. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1565. {
  1566. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1567. }
  1568. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1569. {
  1570. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1571. }
  1572. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1573. {
  1574. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1575. }
  1576. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1577. struct mlx4_vhcr *vhcr,
  1578. struct mlx4_cmd_mailbox *inbox,
  1579. struct mlx4_cmd_mailbox *outbox,
  1580. struct mlx4_cmd_info *cmd)
  1581. {
  1582. int err;
  1583. int qpn = vhcr->in_modifier & 0x7fffff;
  1584. struct res_mtt *mtt;
  1585. struct res_qp *qp;
  1586. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1587. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1588. int mtt_size = qp_get_mtt_size(qpc);
  1589. struct res_cq *rcq;
  1590. struct res_cq *scq;
  1591. int rcqn = qp_get_rcqn(qpc);
  1592. int scqn = qp_get_scqn(qpc);
  1593. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1594. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1595. struct res_srq *srq;
  1596. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1597. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1598. if (err)
  1599. return err;
  1600. qp->local_qpn = local_qpn;
  1601. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1602. if (err)
  1603. goto ex_abort;
  1604. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1605. if (err)
  1606. goto ex_put_mtt;
  1607. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1608. if (err)
  1609. goto ex_put_mtt;
  1610. if (scqn != rcqn) {
  1611. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1612. if (err)
  1613. goto ex_put_rcq;
  1614. } else
  1615. scq = rcq;
  1616. if (use_srq) {
  1617. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1618. if (err)
  1619. goto ex_put_scq;
  1620. }
  1621. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1622. if (err)
  1623. goto ex_put_srq;
  1624. atomic_inc(&mtt->ref_count);
  1625. qp->mtt = mtt;
  1626. atomic_inc(&rcq->ref_count);
  1627. qp->rcq = rcq;
  1628. atomic_inc(&scq->ref_count);
  1629. qp->scq = scq;
  1630. if (scqn != rcqn)
  1631. put_res(dev, slave, scqn, RES_CQ);
  1632. if (use_srq) {
  1633. atomic_inc(&srq->ref_count);
  1634. put_res(dev, slave, srqn, RES_SRQ);
  1635. qp->srq = srq;
  1636. }
  1637. put_res(dev, slave, rcqn, RES_CQ);
  1638. put_res(dev, slave, mtt_base, RES_MTT);
  1639. res_end_move(dev, slave, RES_QP, qpn);
  1640. return 0;
  1641. ex_put_srq:
  1642. if (use_srq)
  1643. put_res(dev, slave, srqn, RES_SRQ);
  1644. ex_put_scq:
  1645. if (scqn != rcqn)
  1646. put_res(dev, slave, scqn, RES_CQ);
  1647. ex_put_rcq:
  1648. put_res(dev, slave, rcqn, RES_CQ);
  1649. ex_put_mtt:
  1650. put_res(dev, slave, mtt_base, RES_MTT);
  1651. ex_abort:
  1652. res_abort_move(dev, slave, RES_QP, qpn);
  1653. return err;
  1654. }
  1655. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1656. {
  1657. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1658. }
  1659. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1660. {
  1661. int log_eq_size = eqc->log_eq_size & 0x1f;
  1662. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1663. if (log_eq_size + 5 < page_shift)
  1664. return 1;
  1665. return 1 << (log_eq_size + 5 - page_shift);
  1666. }
  1667. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1668. {
  1669. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1670. }
  1671. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1672. {
  1673. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1674. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1675. if (log_cq_size + 5 < page_shift)
  1676. return 1;
  1677. return 1 << (log_cq_size + 5 - page_shift);
  1678. }
  1679. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1680. struct mlx4_vhcr *vhcr,
  1681. struct mlx4_cmd_mailbox *inbox,
  1682. struct mlx4_cmd_mailbox *outbox,
  1683. struct mlx4_cmd_info *cmd)
  1684. {
  1685. int err;
  1686. int eqn = vhcr->in_modifier;
  1687. int res_id = (slave << 8) | eqn;
  1688. struct mlx4_eq_context *eqc = inbox->buf;
  1689. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1690. int mtt_size = eq_get_mtt_size(eqc);
  1691. struct res_eq *eq;
  1692. struct res_mtt *mtt;
  1693. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1694. if (err)
  1695. return err;
  1696. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1697. if (err)
  1698. goto out_add;
  1699. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1700. if (err)
  1701. goto out_move;
  1702. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1703. if (err)
  1704. goto out_put;
  1705. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1706. if (err)
  1707. goto out_put;
  1708. atomic_inc(&mtt->ref_count);
  1709. eq->mtt = mtt;
  1710. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1711. res_end_move(dev, slave, RES_EQ, res_id);
  1712. return 0;
  1713. out_put:
  1714. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1715. out_move:
  1716. res_abort_move(dev, slave, RES_EQ, res_id);
  1717. out_add:
  1718. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1719. return err;
  1720. }
  1721. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1722. int len, struct res_mtt **res)
  1723. {
  1724. struct mlx4_priv *priv = mlx4_priv(dev);
  1725. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1726. struct res_mtt *mtt;
  1727. int err = -EINVAL;
  1728. spin_lock_irq(mlx4_tlock(dev));
  1729. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1730. com.list) {
  1731. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1732. *res = mtt;
  1733. mtt->com.from_state = mtt->com.state;
  1734. mtt->com.state = RES_MTT_BUSY;
  1735. err = 0;
  1736. break;
  1737. }
  1738. }
  1739. spin_unlock_irq(mlx4_tlock(dev));
  1740. return err;
  1741. }
  1742. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1743. struct mlx4_vhcr *vhcr,
  1744. struct mlx4_cmd_mailbox *inbox,
  1745. struct mlx4_cmd_mailbox *outbox,
  1746. struct mlx4_cmd_info *cmd)
  1747. {
  1748. struct mlx4_mtt mtt;
  1749. __be64 *page_list = inbox->buf;
  1750. u64 *pg_list = (u64 *)page_list;
  1751. int i;
  1752. struct res_mtt *rmtt = NULL;
  1753. int start = be64_to_cpu(page_list[0]);
  1754. int npages = vhcr->in_modifier;
  1755. int err;
  1756. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1757. if (err)
  1758. return err;
  1759. /* Call the SW implementation of write_mtt:
  1760. * - Prepare a dummy mtt struct
  1761. * - Translate inbox contents to simple addresses in host endianess */
  1762. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1763. we don't really use it */
  1764. mtt.order = 0;
  1765. mtt.page_shift = 0;
  1766. for (i = 0; i < npages; ++i)
  1767. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1768. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1769. ((u64 *)page_list + 2));
  1770. if (rmtt)
  1771. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1772. return err;
  1773. }
  1774. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1775. struct mlx4_vhcr *vhcr,
  1776. struct mlx4_cmd_mailbox *inbox,
  1777. struct mlx4_cmd_mailbox *outbox,
  1778. struct mlx4_cmd_info *cmd)
  1779. {
  1780. int eqn = vhcr->in_modifier;
  1781. int res_id = eqn | (slave << 8);
  1782. struct res_eq *eq;
  1783. int err;
  1784. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1785. if (err)
  1786. return err;
  1787. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1788. if (err)
  1789. goto ex_abort;
  1790. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1791. if (err)
  1792. goto ex_put;
  1793. atomic_dec(&eq->mtt->ref_count);
  1794. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1795. res_end_move(dev, slave, RES_EQ, res_id);
  1796. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1797. return 0;
  1798. ex_put:
  1799. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1800. ex_abort:
  1801. res_abort_move(dev, slave, RES_EQ, res_id);
  1802. return err;
  1803. }
  1804. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1805. {
  1806. struct mlx4_priv *priv = mlx4_priv(dev);
  1807. struct mlx4_slave_event_eq_info *event_eq;
  1808. struct mlx4_cmd_mailbox *mailbox;
  1809. u32 in_modifier = 0;
  1810. int err;
  1811. int res_id;
  1812. struct res_eq *req;
  1813. if (!priv->mfunc.master.slave_state)
  1814. return -EINVAL;
  1815. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1816. /* Create the event only if the slave is registered */
  1817. if (event_eq->eqn < 0)
  1818. return 0;
  1819. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1820. res_id = (slave << 8) | event_eq->eqn;
  1821. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1822. if (err)
  1823. goto unlock;
  1824. if (req->com.from_state != RES_EQ_HW) {
  1825. err = -EINVAL;
  1826. goto put;
  1827. }
  1828. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1829. if (IS_ERR(mailbox)) {
  1830. err = PTR_ERR(mailbox);
  1831. goto put;
  1832. }
  1833. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1834. ++event_eq->token;
  1835. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1836. }
  1837. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1838. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1839. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1840. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1841. MLX4_CMD_NATIVE);
  1842. put_res(dev, slave, res_id, RES_EQ);
  1843. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1844. mlx4_free_cmd_mailbox(dev, mailbox);
  1845. return err;
  1846. put:
  1847. put_res(dev, slave, res_id, RES_EQ);
  1848. unlock:
  1849. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1850. return err;
  1851. }
  1852. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1853. struct mlx4_vhcr *vhcr,
  1854. struct mlx4_cmd_mailbox *inbox,
  1855. struct mlx4_cmd_mailbox *outbox,
  1856. struct mlx4_cmd_info *cmd)
  1857. {
  1858. int eqn = vhcr->in_modifier;
  1859. int res_id = eqn | (slave << 8);
  1860. struct res_eq *eq;
  1861. int err;
  1862. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1863. if (err)
  1864. return err;
  1865. if (eq->com.from_state != RES_EQ_HW) {
  1866. err = -EINVAL;
  1867. goto ex_put;
  1868. }
  1869. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1870. ex_put:
  1871. put_res(dev, slave, res_id, RES_EQ);
  1872. return err;
  1873. }
  1874. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1875. struct mlx4_vhcr *vhcr,
  1876. struct mlx4_cmd_mailbox *inbox,
  1877. struct mlx4_cmd_mailbox *outbox,
  1878. struct mlx4_cmd_info *cmd)
  1879. {
  1880. int err;
  1881. int cqn = vhcr->in_modifier;
  1882. struct mlx4_cq_context *cqc = inbox->buf;
  1883. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1884. struct res_cq *cq;
  1885. struct res_mtt *mtt;
  1886. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1887. if (err)
  1888. return err;
  1889. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1890. if (err)
  1891. goto out_move;
  1892. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1893. if (err)
  1894. goto out_put;
  1895. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1896. if (err)
  1897. goto out_put;
  1898. atomic_inc(&mtt->ref_count);
  1899. cq->mtt = mtt;
  1900. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1901. res_end_move(dev, slave, RES_CQ, cqn);
  1902. return 0;
  1903. out_put:
  1904. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1905. out_move:
  1906. res_abort_move(dev, slave, RES_CQ, cqn);
  1907. return err;
  1908. }
  1909. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1910. struct mlx4_vhcr *vhcr,
  1911. struct mlx4_cmd_mailbox *inbox,
  1912. struct mlx4_cmd_mailbox *outbox,
  1913. struct mlx4_cmd_info *cmd)
  1914. {
  1915. int err;
  1916. int cqn = vhcr->in_modifier;
  1917. struct res_cq *cq;
  1918. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1919. if (err)
  1920. return err;
  1921. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1922. if (err)
  1923. goto out_move;
  1924. atomic_dec(&cq->mtt->ref_count);
  1925. res_end_move(dev, slave, RES_CQ, cqn);
  1926. return 0;
  1927. out_move:
  1928. res_abort_move(dev, slave, RES_CQ, cqn);
  1929. return err;
  1930. }
  1931. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1932. struct mlx4_vhcr *vhcr,
  1933. struct mlx4_cmd_mailbox *inbox,
  1934. struct mlx4_cmd_mailbox *outbox,
  1935. struct mlx4_cmd_info *cmd)
  1936. {
  1937. int cqn = vhcr->in_modifier;
  1938. struct res_cq *cq;
  1939. int err;
  1940. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1941. if (err)
  1942. return err;
  1943. if (cq->com.from_state != RES_CQ_HW)
  1944. goto ex_put;
  1945. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1946. ex_put:
  1947. put_res(dev, slave, cqn, RES_CQ);
  1948. return err;
  1949. }
  1950. static int handle_resize(struct mlx4_dev *dev, int slave,
  1951. struct mlx4_vhcr *vhcr,
  1952. struct mlx4_cmd_mailbox *inbox,
  1953. struct mlx4_cmd_mailbox *outbox,
  1954. struct mlx4_cmd_info *cmd,
  1955. struct res_cq *cq)
  1956. {
  1957. int err;
  1958. struct res_mtt *orig_mtt;
  1959. struct res_mtt *mtt;
  1960. struct mlx4_cq_context *cqc = inbox->buf;
  1961. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1962. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1963. if (err)
  1964. return err;
  1965. if (orig_mtt != cq->mtt) {
  1966. err = -EINVAL;
  1967. goto ex_put;
  1968. }
  1969. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1970. if (err)
  1971. goto ex_put;
  1972. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1973. if (err)
  1974. goto ex_put1;
  1975. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1976. if (err)
  1977. goto ex_put1;
  1978. atomic_dec(&orig_mtt->ref_count);
  1979. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1980. atomic_inc(&mtt->ref_count);
  1981. cq->mtt = mtt;
  1982. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1983. return 0;
  1984. ex_put1:
  1985. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1986. ex_put:
  1987. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1988. return err;
  1989. }
  1990. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1991. struct mlx4_vhcr *vhcr,
  1992. struct mlx4_cmd_mailbox *inbox,
  1993. struct mlx4_cmd_mailbox *outbox,
  1994. struct mlx4_cmd_info *cmd)
  1995. {
  1996. int cqn = vhcr->in_modifier;
  1997. struct res_cq *cq;
  1998. int err;
  1999. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2000. if (err)
  2001. return err;
  2002. if (cq->com.from_state != RES_CQ_HW)
  2003. goto ex_put;
  2004. if (vhcr->op_modifier == 0) {
  2005. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2006. goto ex_put;
  2007. }
  2008. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2009. ex_put:
  2010. put_res(dev, slave, cqn, RES_CQ);
  2011. return err;
  2012. }
  2013. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2014. {
  2015. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2016. int log_rq_stride = srqc->logstride & 7;
  2017. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2018. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2019. return 1;
  2020. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2021. }
  2022. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2023. struct mlx4_vhcr *vhcr,
  2024. struct mlx4_cmd_mailbox *inbox,
  2025. struct mlx4_cmd_mailbox *outbox,
  2026. struct mlx4_cmd_info *cmd)
  2027. {
  2028. int err;
  2029. int srqn = vhcr->in_modifier;
  2030. struct res_mtt *mtt;
  2031. struct res_srq *srq;
  2032. struct mlx4_srq_context *srqc = inbox->buf;
  2033. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2034. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2035. return -EINVAL;
  2036. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2037. if (err)
  2038. return err;
  2039. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2040. if (err)
  2041. goto ex_abort;
  2042. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2043. mtt);
  2044. if (err)
  2045. goto ex_put_mtt;
  2046. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2047. if (err)
  2048. goto ex_put_mtt;
  2049. atomic_inc(&mtt->ref_count);
  2050. srq->mtt = mtt;
  2051. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2052. res_end_move(dev, slave, RES_SRQ, srqn);
  2053. return 0;
  2054. ex_put_mtt:
  2055. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2056. ex_abort:
  2057. res_abort_move(dev, slave, RES_SRQ, srqn);
  2058. return err;
  2059. }
  2060. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2061. struct mlx4_vhcr *vhcr,
  2062. struct mlx4_cmd_mailbox *inbox,
  2063. struct mlx4_cmd_mailbox *outbox,
  2064. struct mlx4_cmd_info *cmd)
  2065. {
  2066. int err;
  2067. int srqn = vhcr->in_modifier;
  2068. struct res_srq *srq;
  2069. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2070. if (err)
  2071. return err;
  2072. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2073. if (err)
  2074. goto ex_abort;
  2075. atomic_dec(&srq->mtt->ref_count);
  2076. if (srq->cq)
  2077. atomic_dec(&srq->cq->ref_count);
  2078. res_end_move(dev, slave, RES_SRQ, srqn);
  2079. return 0;
  2080. ex_abort:
  2081. res_abort_move(dev, slave, RES_SRQ, srqn);
  2082. return err;
  2083. }
  2084. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2085. struct mlx4_vhcr *vhcr,
  2086. struct mlx4_cmd_mailbox *inbox,
  2087. struct mlx4_cmd_mailbox *outbox,
  2088. struct mlx4_cmd_info *cmd)
  2089. {
  2090. int err;
  2091. int srqn = vhcr->in_modifier;
  2092. struct res_srq *srq;
  2093. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2094. if (err)
  2095. return err;
  2096. if (srq->com.from_state != RES_SRQ_HW) {
  2097. err = -EBUSY;
  2098. goto out;
  2099. }
  2100. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2101. out:
  2102. put_res(dev, slave, srqn, RES_SRQ);
  2103. return err;
  2104. }
  2105. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2106. struct mlx4_vhcr *vhcr,
  2107. struct mlx4_cmd_mailbox *inbox,
  2108. struct mlx4_cmd_mailbox *outbox,
  2109. struct mlx4_cmd_info *cmd)
  2110. {
  2111. int err;
  2112. int srqn = vhcr->in_modifier;
  2113. struct res_srq *srq;
  2114. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2115. if (err)
  2116. return err;
  2117. if (srq->com.from_state != RES_SRQ_HW) {
  2118. err = -EBUSY;
  2119. goto out;
  2120. }
  2121. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2122. out:
  2123. put_res(dev, slave, srqn, RES_SRQ);
  2124. return err;
  2125. }
  2126. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2127. struct mlx4_vhcr *vhcr,
  2128. struct mlx4_cmd_mailbox *inbox,
  2129. struct mlx4_cmd_mailbox *outbox,
  2130. struct mlx4_cmd_info *cmd)
  2131. {
  2132. int err;
  2133. int qpn = vhcr->in_modifier & 0x7fffff;
  2134. struct res_qp *qp;
  2135. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2136. if (err)
  2137. return err;
  2138. if (qp->com.from_state != RES_QP_HW) {
  2139. err = -EBUSY;
  2140. goto out;
  2141. }
  2142. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2143. out:
  2144. put_res(dev, slave, qpn, RES_QP);
  2145. return err;
  2146. }
  2147. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2148. struct mlx4_vhcr *vhcr,
  2149. struct mlx4_cmd_mailbox *inbox,
  2150. struct mlx4_cmd_mailbox *outbox,
  2151. struct mlx4_cmd_info *cmd)
  2152. {
  2153. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2154. update_ud_gid(dev, qpc, (u8)slave);
  2155. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2156. }
  2157. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2158. struct mlx4_vhcr *vhcr,
  2159. struct mlx4_cmd_mailbox *inbox,
  2160. struct mlx4_cmd_mailbox *outbox,
  2161. struct mlx4_cmd_info *cmd)
  2162. {
  2163. int err;
  2164. int qpn = vhcr->in_modifier & 0x7fffff;
  2165. struct res_qp *qp;
  2166. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2167. if (err)
  2168. return err;
  2169. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2170. if (err)
  2171. goto ex_abort;
  2172. atomic_dec(&qp->mtt->ref_count);
  2173. atomic_dec(&qp->rcq->ref_count);
  2174. atomic_dec(&qp->scq->ref_count);
  2175. if (qp->srq)
  2176. atomic_dec(&qp->srq->ref_count);
  2177. res_end_move(dev, slave, RES_QP, qpn);
  2178. return 0;
  2179. ex_abort:
  2180. res_abort_move(dev, slave, RES_QP, qpn);
  2181. return err;
  2182. }
  2183. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2184. struct res_qp *rqp, u8 *gid)
  2185. {
  2186. struct res_gid *res;
  2187. list_for_each_entry(res, &rqp->mcg_list, list) {
  2188. if (!memcmp(res->gid, gid, 16))
  2189. return res;
  2190. }
  2191. return NULL;
  2192. }
  2193. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2194. u8 *gid, enum mlx4_protocol prot,
  2195. enum mlx4_steer_type steer)
  2196. {
  2197. struct res_gid *res;
  2198. int err;
  2199. res = kzalloc(sizeof *res, GFP_KERNEL);
  2200. if (!res)
  2201. return -ENOMEM;
  2202. spin_lock_irq(&rqp->mcg_spl);
  2203. if (find_gid(dev, slave, rqp, gid)) {
  2204. kfree(res);
  2205. err = -EEXIST;
  2206. } else {
  2207. memcpy(res->gid, gid, 16);
  2208. res->prot = prot;
  2209. res->steer = steer;
  2210. list_add_tail(&res->list, &rqp->mcg_list);
  2211. err = 0;
  2212. }
  2213. spin_unlock_irq(&rqp->mcg_spl);
  2214. return err;
  2215. }
  2216. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2217. u8 *gid, enum mlx4_protocol prot,
  2218. enum mlx4_steer_type steer)
  2219. {
  2220. struct res_gid *res;
  2221. int err;
  2222. spin_lock_irq(&rqp->mcg_spl);
  2223. res = find_gid(dev, slave, rqp, gid);
  2224. if (!res || res->prot != prot || res->steer != steer)
  2225. err = -EINVAL;
  2226. else {
  2227. list_del(&res->list);
  2228. kfree(res);
  2229. err = 0;
  2230. }
  2231. spin_unlock_irq(&rqp->mcg_spl);
  2232. return err;
  2233. }
  2234. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2235. struct mlx4_vhcr *vhcr,
  2236. struct mlx4_cmd_mailbox *inbox,
  2237. struct mlx4_cmd_mailbox *outbox,
  2238. struct mlx4_cmd_info *cmd)
  2239. {
  2240. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2241. u8 *gid = inbox->buf;
  2242. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2243. int err;
  2244. int qpn;
  2245. struct res_qp *rqp;
  2246. int attach = vhcr->op_modifier;
  2247. int block_loopback = vhcr->in_modifier >> 31;
  2248. u8 steer_type_mask = 2;
  2249. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2250. qpn = vhcr->in_modifier & 0xffffff;
  2251. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2252. if (err)
  2253. return err;
  2254. qp.qpn = qpn;
  2255. if (attach) {
  2256. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2257. if (err)
  2258. goto ex_put;
  2259. err = mlx4_qp_attach_common(dev, &qp, gid,
  2260. block_loopback, prot, type);
  2261. if (err)
  2262. goto ex_rem;
  2263. } else {
  2264. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2265. if (err)
  2266. goto ex_put;
  2267. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2268. }
  2269. put_res(dev, slave, qpn, RES_QP);
  2270. return 0;
  2271. ex_rem:
  2272. /* ignore error return below, already in error */
  2273. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2274. ex_put:
  2275. put_res(dev, slave, qpn, RES_QP);
  2276. return err;
  2277. }
  2278. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2279. struct mlx4_vhcr *vhcr,
  2280. struct mlx4_cmd_mailbox *inbox,
  2281. struct mlx4_cmd_mailbox *outbox,
  2282. struct mlx4_cmd_info *cmd)
  2283. {
  2284. return mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2285. vhcr->in_modifier, 0,
  2286. MLX4_QP_FLOW_STEERING_ATTACH,
  2287. MLX4_CMD_TIME_CLASS_A,
  2288. MLX4_CMD_NATIVE);
  2289. }
  2290. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2291. struct mlx4_vhcr *vhcr,
  2292. struct mlx4_cmd_mailbox *inbox,
  2293. struct mlx4_cmd_mailbox *outbox,
  2294. struct mlx4_cmd_info *cmd)
  2295. {
  2296. return mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2297. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2298. MLX4_CMD_NATIVE);
  2299. }
  2300. enum {
  2301. BUSY_MAX_RETRIES = 10
  2302. };
  2303. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2304. struct mlx4_vhcr *vhcr,
  2305. struct mlx4_cmd_mailbox *inbox,
  2306. struct mlx4_cmd_mailbox *outbox,
  2307. struct mlx4_cmd_info *cmd)
  2308. {
  2309. int err;
  2310. int index = vhcr->in_modifier & 0xffff;
  2311. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2312. if (err)
  2313. return err;
  2314. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2315. put_res(dev, slave, index, RES_COUNTER);
  2316. return err;
  2317. }
  2318. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2319. {
  2320. struct res_gid *rgid;
  2321. struct res_gid *tmp;
  2322. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2323. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2324. qp.qpn = rqp->local_qpn;
  2325. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2326. rgid->steer);
  2327. list_del(&rgid->list);
  2328. kfree(rgid);
  2329. }
  2330. }
  2331. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2332. enum mlx4_resource type, int print)
  2333. {
  2334. struct mlx4_priv *priv = mlx4_priv(dev);
  2335. struct mlx4_resource_tracker *tracker =
  2336. &priv->mfunc.master.res_tracker;
  2337. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2338. struct res_common *r;
  2339. struct res_common *tmp;
  2340. int busy;
  2341. busy = 0;
  2342. spin_lock_irq(mlx4_tlock(dev));
  2343. list_for_each_entry_safe(r, tmp, rlist, list) {
  2344. if (r->owner == slave) {
  2345. if (!r->removing) {
  2346. if (r->state == RES_ANY_BUSY) {
  2347. if (print)
  2348. mlx4_dbg(dev,
  2349. "%s id 0x%llx is busy\n",
  2350. ResourceType(type),
  2351. r->res_id);
  2352. ++busy;
  2353. } else {
  2354. r->from_state = r->state;
  2355. r->state = RES_ANY_BUSY;
  2356. r->removing = 1;
  2357. }
  2358. }
  2359. }
  2360. }
  2361. spin_unlock_irq(mlx4_tlock(dev));
  2362. return busy;
  2363. }
  2364. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2365. enum mlx4_resource type)
  2366. {
  2367. unsigned long begin;
  2368. int busy;
  2369. begin = jiffies;
  2370. do {
  2371. busy = _move_all_busy(dev, slave, type, 0);
  2372. if (time_after(jiffies, begin + 5 * HZ))
  2373. break;
  2374. if (busy)
  2375. cond_resched();
  2376. } while (busy);
  2377. if (busy)
  2378. busy = _move_all_busy(dev, slave, type, 1);
  2379. return busy;
  2380. }
  2381. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2382. {
  2383. struct mlx4_priv *priv = mlx4_priv(dev);
  2384. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2385. struct list_head *qp_list =
  2386. &tracker->slave_list[slave].res_list[RES_QP];
  2387. struct res_qp *qp;
  2388. struct res_qp *tmp;
  2389. int state;
  2390. u64 in_param;
  2391. int qpn;
  2392. int err;
  2393. err = move_all_busy(dev, slave, RES_QP);
  2394. if (err)
  2395. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2396. "for slave %d\n", slave);
  2397. spin_lock_irq(mlx4_tlock(dev));
  2398. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2399. spin_unlock_irq(mlx4_tlock(dev));
  2400. if (qp->com.owner == slave) {
  2401. qpn = qp->com.res_id;
  2402. detach_qp(dev, slave, qp);
  2403. state = qp->com.from_state;
  2404. while (state != 0) {
  2405. switch (state) {
  2406. case RES_QP_RESERVED:
  2407. spin_lock_irq(mlx4_tlock(dev));
  2408. rb_erase(&qp->com.node,
  2409. &tracker->res_tree[RES_QP]);
  2410. list_del(&qp->com.list);
  2411. spin_unlock_irq(mlx4_tlock(dev));
  2412. kfree(qp);
  2413. state = 0;
  2414. break;
  2415. case RES_QP_MAPPED:
  2416. if (!valid_reserved(dev, slave, qpn))
  2417. __mlx4_qp_free_icm(dev, qpn);
  2418. state = RES_QP_RESERVED;
  2419. break;
  2420. case RES_QP_HW:
  2421. in_param = slave;
  2422. err = mlx4_cmd(dev, in_param,
  2423. qp->local_qpn, 2,
  2424. MLX4_CMD_2RST_QP,
  2425. MLX4_CMD_TIME_CLASS_A,
  2426. MLX4_CMD_NATIVE);
  2427. if (err)
  2428. mlx4_dbg(dev, "rem_slave_qps: failed"
  2429. " to move slave %d qpn %d to"
  2430. " reset\n", slave,
  2431. qp->local_qpn);
  2432. atomic_dec(&qp->rcq->ref_count);
  2433. atomic_dec(&qp->scq->ref_count);
  2434. atomic_dec(&qp->mtt->ref_count);
  2435. if (qp->srq)
  2436. atomic_dec(&qp->srq->ref_count);
  2437. state = RES_QP_MAPPED;
  2438. break;
  2439. default:
  2440. state = 0;
  2441. }
  2442. }
  2443. }
  2444. spin_lock_irq(mlx4_tlock(dev));
  2445. }
  2446. spin_unlock_irq(mlx4_tlock(dev));
  2447. }
  2448. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2449. {
  2450. struct mlx4_priv *priv = mlx4_priv(dev);
  2451. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2452. struct list_head *srq_list =
  2453. &tracker->slave_list[slave].res_list[RES_SRQ];
  2454. struct res_srq *srq;
  2455. struct res_srq *tmp;
  2456. int state;
  2457. u64 in_param;
  2458. LIST_HEAD(tlist);
  2459. int srqn;
  2460. int err;
  2461. err = move_all_busy(dev, slave, RES_SRQ);
  2462. if (err)
  2463. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2464. "busy for slave %d\n", slave);
  2465. spin_lock_irq(mlx4_tlock(dev));
  2466. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2467. spin_unlock_irq(mlx4_tlock(dev));
  2468. if (srq->com.owner == slave) {
  2469. srqn = srq->com.res_id;
  2470. state = srq->com.from_state;
  2471. while (state != 0) {
  2472. switch (state) {
  2473. case RES_SRQ_ALLOCATED:
  2474. __mlx4_srq_free_icm(dev, srqn);
  2475. spin_lock_irq(mlx4_tlock(dev));
  2476. rb_erase(&srq->com.node,
  2477. &tracker->res_tree[RES_SRQ]);
  2478. list_del(&srq->com.list);
  2479. spin_unlock_irq(mlx4_tlock(dev));
  2480. kfree(srq);
  2481. state = 0;
  2482. break;
  2483. case RES_SRQ_HW:
  2484. in_param = slave;
  2485. err = mlx4_cmd(dev, in_param, srqn, 1,
  2486. MLX4_CMD_HW2SW_SRQ,
  2487. MLX4_CMD_TIME_CLASS_A,
  2488. MLX4_CMD_NATIVE);
  2489. if (err)
  2490. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2491. " to move slave %d srq %d to"
  2492. " SW ownership\n",
  2493. slave, srqn);
  2494. atomic_dec(&srq->mtt->ref_count);
  2495. if (srq->cq)
  2496. atomic_dec(&srq->cq->ref_count);
  2497. state = RES_SRQ_ALLOCATED;
  2498. break;
  2499. default:
  2500. state = 0;
  2501. }
  2502. }
  2503. }
  2504. spin_lock_irq(mlx4_tlock(dev));
  2505. }
  2506. spin_unlock_irq(mlx4_tlock(dev));
  2507. }
  2508. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2509. {
  2510. struct mlx4_priv *priv = mlx4_priv(dev);
  2511. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2512. struct list_head *cq_list =
  2513. &tracker->slave_list[slave].res_list[RES_CQ];
  2514. struct res_cq *cq;
  2515. struct res_cq *tmp;
  2516. int state;
  2517. u64 in_param;
  2518. LIST_HEAD(tlist);
  2519. int cqn;
  2520. int err;
  2521. err = move_all_busy(dev, slave, RES_CQ);
  2522. if (err)
  2523. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2524. "busy for slave %d\n", slave);
  2525. spin_lock_irq(mlx4_tlock(dev));
  2526. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2527. spin_unlock_irq(mlx4_tlock(dev));
  2528. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2529. cqn = cq->com.res_id;
  2530. state = cq->com.from_state;
  2531. while (state != 0) {
  2532. switch (state) {
  2533. case RES_CQ_ALLOCATED:
  2534. __mlx4_cq_free_icm(dev, cqn);
  2535. spin_lock_irq(mlx4_tlock(dev));
  2536. rb_erase(&cq->com.node,
  2537. &tracker->res_tree[RES_CQ]);
  2538. list_del(&cq->com.list);
  2539. spin_unlock_irq(mlx4_tlock(dev));
  2540. kfree(cq);
  2541. state = 0;
  2542. break;
  2543. case RES_CQ_HW:
  2544. in_param = slave;
  2545. err = mlx4_cmd(dev, in_param, cqn, 1,
  2546. MLX4_CMD_HW2SW_CQ,
  2547. MLX4_CMD_TIME_CLASS_A,
  2548. MLX4_CMD_NATIVE);
  2549. if (err)
  2550. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2551. " to move slave %d cq %d to"
  2552. " SW ownership\n",
  2553. slave, cqn);
  2554. atomic_dec(&cq->mtt->ref_count);
  2555. state = RES_CQ_ALLOCATED;
  2556. break;
  2557. default:
  2558. state = 0;
  2559. }
  2560. }
  2561. }
  2562. spin_lock_irq(mlx4_tlock(dev));
  2563. }
  2564. spin_unlock_irq(mlx4_tlock(dev));
  2565. }
  2566. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2567. {
  2568. struct mlx4_priv *priv = mlx4_priv(dev);
  2569. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2570. struct list_head *mpt_list =
  2571. &tracker->slave_list[slave].res_list[RES_MPT];
  2572. struct res_mpt *mpt;
  2573. struct res_mpt *tmp;
  2574. int state;
  2575. u64 in_param;
  2576. LIST_HEAD(tlist);
  2577. int mptn;
  2578. int err;
  2579. err = move_all_busy(dev, slave, RES_MPT);
  2580. if (err)
  2581. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2582. "busy for slave %d\n", slave);
  2583. spin_lock_irq(mlx4_tlock(dev));
  2584. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2585. spin_unlock_irq(mlx4_tlock(dev));
  2586. if (mpt->com.owner == slave) {
  2587. mptn = mpt->com.res_id;
  2588. state = mpt->com.from_state;
  2589. while (state != 0) {
  2590. switch (state) {
  2591. case RES_MPT_RESERVED:
  2592. __mlx4_mr_release(dev, mpt->key);
  2593. spin_lock_irq(mlx4_tlock(dev));
  2594. rb_erase(&mpt->com.node,
  2595. &tracker->res_tree[RES_MPT]);
  2596. list_del(&mpt->com.list);
  2597. spin_unlock_irq(mlx4_tlock(dev));
  2598. kfree(mpt);
  2599. state = 0;
  2600. break;
  2601. case RES_MPT_MAPPED:
  2602. __mlx4_mr_free_icm(dev, mpt->key);
  2603. state = RES_MPT_RESERVED;
  2604. break;
  2605. case RES_MPT_HW:
  2606. in_param = slave;
  2607. err = mlx4_cmd(dev, in_param, mptn, 0,
  2608. MLX4_CMD_HW2SW_MPT,
  2609. MLX4_CMD_TIME_CLASS_A,
  2610. MLX4_CMD_NATIVE);
  2611. if (err)
  2612. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2613. " to move slave %d mpt %d to"
  2614. " SW ownership\n",
  2615. slave, mptn);
  2616. if (mpt->mtt)
  2617. atomic_dec(&mpt->mtt->ref_count);
  2618. state = RES_MPT_MAPPED;
  2619. break;
  2620. default:
  2621. state = 0;
  2622. }
  2623. }
  2624. }
  2625. spin_lock_irq(mlx4_tlock(dev));
  2626. }
  2627. spin_unlock_irq(mlx4_tlock(dev));
  2628. }
  2629. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2630. {
  2631. struct mlx4_priv *priv = mlx4_priv(dev);
  2632. struct mlx4_resource_tracker *tracker =
  2633. &priv->mfunc.master.res_tracker;
  2634. struct list_head *mtt_list =
  2635. &tracker->slave_list[slave].res_list[RES_MTT];
  2636. struct res_mtt *mtt;
  2637. struct res_mtt *tmp;
  2638. int state;
  2639. LIST_HEAD(tlist);
  2640. int base;
  2641. int err;
  2642. err = move_all_busy(dev, slave, RES_MTT);
  2643. if (err)
  2644. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2645. "busy for slave %d\n", slave);
  2646. spin_lock_irq(mlx4_tlock(dev));
  2647. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2648. spin_unlock_irq(mlx4_tlock(dev));
  2649. if (mtt->com.owner == slave) {
  2650. base = mtt->com.res_id;
  2651. state = mtt->com.from_state;
  2652. while (state != 0) {
  2653. switch (state) {
  2654. case RES_MTT_ALLOCATED:
  2655. __mlx4_free_mtt_range(dev, base,
  2656. mtt->order);
  2657. spin_lock_irq(mlx4_tlock(dev));
  2658. rb_erase(&mtt->com.node,
  2659. &tracker->res_tree[RES_MTT]);
  2660. list_del(&mtt->com.list);
  2661. spin_unlock_irq(mlx4_tlock(dev));
  2662. kfree(mtt);
  2663. state = 0;
  2664. break;
  2665. default:
  2666. state = 0;
  2667. }
  2668. }
  2669. }
  2670. spin_lock_irq(mlx4_tlock(dev));
  2671. }
  2672. spin_unlock_irq(mlx4_tlock(dev));
  2673. }
  2674. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2675. {
  2676. struct mlx4_priv *priv = mlx4_priv(dev);
  2677. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2678. struct list_head *eq_list =
  2679. &tracker->slave_list[slave].res_list[RES_EQ];
  2680. struct res_eq *eq;
  2681. struct res_eq *tmp;
  2682. int err;
  2683. int state;
  2684. LIST_HEAD(tlist);
  2685. int eqn;
  2686. struct mlx4_cmd_mailbox *mailbox;
  2687. err = move_all_busy(dev, slave, RES_EQ);
  2688. if (err)
  2689. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2690. "busy for slave %d\n", slave);
  2691. spin_lock_irq(mlx4_tlock(dev));
  2692. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2693. spin_unlock_irq(mlx4_tlock(dev));
  2694. if (eq->com.owner == slave) {
  2695. eqn = eq->com.res_id;
  2696. state = eq->com.from_state;
  2697. while (state != 0) {
  2698. switch (state) {
  2699. case RES_EQ_RESERVED:
  2700. spin_lock_irq(mlx4_tlock(dev));
  2701. rb_erase(&eq->com.node,
  2702. &tracker->res_tree[RES_EQ]);
  2703. list_del(&eq->com.list);
  2704. spin_unlock_irq(mlx4_tlock(dev));
  2705. kfree(eq);
  2706. state = 0;
  2707. break;
  2708. case RES_EQ_HW:
  2709. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2710. if (IS_ERR(mailbox)) {
  2711. cond_resched();
  2712. continue;
  2713. }
  2714. err = mlx4_cmd_box(dev, slave, 0,
  2715. eqn & 0xff, 0,
  2716. MLX4_CMD_HW2SW_EQ,
  2717. MLX4_CMD_TIME_CLASS_A,
  2718. MLX4_CMD_NATIVE);
  2719. if (err)
  2720. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2721. " to move slave %d eqs %d to"
  2722. " SW ownership\n", slave, eqn);
  2723. mlx4_free_cmd_mailbox(dev, mailbox);
  2724. atomic_dec(&eq->mtt->ref_count);
  2725. state = RES_EQ_RESERVED;
  2726. break;
  2727. default:
  2728. state = 0;
  2729. }
  2730. }
  2731. }
  2732. spin_lock_irq(mlx4_tlock(dev));
  2733. }
  2734. spin_unlock_irq(mlx4_tlock(dev));
  2735. }
  2736. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  2737. {
  2738. struct mlx4_priv *priv = mlx4_priv(dev);
  2739. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2740. struct list_head *counter_list =
  2741. &tracker->slave_list[slave].res_list[RES_COUNTER];
  2742. struct res_counter *counter;
  2743. struct res_counter *tmp;
  2744. int err;
  2745. int index;
  2746. err = move_all_busy(dev, slave, RES_COUNTER);
  2747. if (err)
  2748. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  2749. "busy for slave %d\n", slave);
  2750. spin_lock_irq(mlx4_tlock(dev));
  2751. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  2752. if (counter->com.owner == slave) {
  2753. index = counter->com.res_id;
  2754. rb_erase(&counter->com.node,
  2755. &tracker->res_tree[RES_COUNTER]);
  2756. list_del(&counter->com.list);
  2757. kfree(counter);
  2758. __mlx4_counter_free(dev, index);
  2759. }
  2760. }
  2761. spin_unlock_irq(mlx4_tlock(dev));
  2762. }
  2763. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  2764. {
  2765. struct mlx4_priv *priv = mlx4_priv(dev);
  2766. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2767. struct list_head *xrcdn_list =
  2768. &tracker->slave_list[slave].res_list[RES_XRCD];
  2769. struct res_xrcdn *xrcd;
  2770. struct res_xrcdn *tmp;
  2771. int err;
  2772. int xrcdn;
  2773. err = move_all_busy(dev, slave, RES_XRCD);
  2774. if (err)
  2775. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  2776. "busy for slave %d\n", slave);
  2777. spin_lock_irq(mlx4_tlock(dev));
  2778. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  2779. if (xrcd->com.owner == slave) {
  2780. xrcdn = xrcd->com.res_id;
  2781. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  2782. list_del(&xrcd->com.list);
  2783. kfree(xrcd);
  2784. __mlx4_xrcd_free(dev, xrcdn);
  2785. }
  2786. }
  2787. spin_unlock_irq(mlx4_tlock(dev));
  2788. }
  2789. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2790. {
  2791. struct mlx4_priv *priv = mlx4_priv(dev);
  2792. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2793. /*VLAN*/
  2794. rem_slave_macs(dev, slave);
  2795. rem_slave_qps(dev, slave);
  2796. rem_slave_srqs(dev, slave);
  2797. rem_slave_cqs(dev, slave);
  2798. rem_slave_mrs(dev, slave);
  2799. rem_slave_eqs(dev, slave);
  2800. rem_slave_mtts(dev, slave);
  2801. rem_slave_counters(dev, slave);
  2802. rem_slave_xrcdns(dev, slave);
  2803. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2804. }