imx28.dtsi 17 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. serial0 = &auart0;
  23. serial1 = &auart1;
  24. serial2 = &auart2;
  25. serial3 = &auart3;
  26. serial4 = &auart4;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. apb@80000000 {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. reg = <0x80000000 0x80000>;
  38. ranges;
  39. apbh@80000000 {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. reg = <0x80000000 0x3c900>;
  44. ranges;
  45. icoll: interrupt-controller@80000000 {
  46. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. reg = <0x80000000 0x2000>;
  50. };
  51. hsadc@80002000 {
  52. reg = <0x80002000 2000>;
  53. interrupts = <13 87>;
  54. status = "disabled";
  55. };
  56. dma-apbh@80004000 {
  57. compatible = "fsl,imx28-dma-apbh";
  58. reg = <0x80004000 2000>;
  59. };
  60. perfmon@80006000 {
  61. reg = <0x80006000 800>;
  62. interrupts = <27>;
  63. status = "disabled";
  64. };
  65. gpmi-nand@8000c000 {
  66. compatible = "fsl,imx28-gpmi-nand";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. reg = <0x8000c000 2000>, <0x8000a000 2000>;
  70. reg-names = "gpmi-nand", "bch";
  71. interrupts = <88>, <41>;
  72. interrupt-names = "gpmi-dma", "bch";
  73. fsl,gpmi-dma-channel = <4>;
  74. status = "disabled";
  75. };
  76. ssp0: ssp@80010000 {
  77. reg = <0x80010000 2000>;
  78. interrupts = <96 82>;
  79. fsl,ssp-dma-channel = <0>;
  80. status = "disabled";
  81. };
  82. ssp1: ssp@80012000 {
  83. reg = <0x80012000 2000>;
  84. interrupts = <97 83>;
  85. fsl,ssp-dma-channel = <1>;
  86. status = "disabled";
  87. };
  88. ssp2: ssp@80014000 {
  89. reg = <0x80014000 2000>;
  90. interrupts = <98 84>;
  91. fsl,ssp-dma-channel = <2>;
  92. status = "disabled";
  93. };
  94. ssp3: ssp@80016000 {
  95. reg = <0x80016000 2000>;
  96. interrupts = <99 85>;
  97. fsl,ssp-dma-channel = <3>;
  98. status = "disabled";
  99. };
  100. pinctrl@80018000 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. compatible = "fsl,imx28-pinctrl", "simple-bus";
  104. reg = <0x80018000 2000>;
  105. gpio0: gpio@0 {
  106. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  107. interrupts = <127>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. interrupt-controller;
  111. #interrupt-cells = <2>;
  112. };
  113. gpio1: gpio@1 {
  114. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  115. interrupts = <126>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. interrupt-controller;
  119. #interrupt-cells = <2>;
  120. };
  121. gpio2: gpio@2 {
  122. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  123. interrupts = <125>;
  124. gpio-controller;
  125. #gpio-cells = <2>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. };
  129. gpio3: gpio@3 {
  130. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  131. interrupts = <124>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio4: gpio@4 {
  138. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  139. interrupts = <123>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. duart_pins_a: duart@0 {
  146. reg = <0>;
  147. fsl,pinmux-ids = <
  148. 0x3102 /* MX28_PAD_PWM0__DUART_RX */
  149. 0x3112 /* MX28_PAD_PWM1__DUART_TX */
  150. >;
  151. fsl,drive-strength = <0>;
  152. fsl,voltage = <1>;
  153. fsl,pull-up = <0>;
  154. };
  155. duart_pins_b: duart@1 {
  156. reg = <1>;
  157. fsl,pinmux-ids = <
  158. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  159. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  160. >;
  161. fsl,drive-strength = <0>;
  162. fsl,voltage = <1>;
  163. fsl,pull-up = <0>;
  164. };
  165. gpmi_pins_a: gpmi-nand@0 {
  166. reg = <0>;
  167. fsl,pinmux-ids = <
  168. 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
  169. 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
  170. 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
  171. 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
  172. 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
  173. 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
  174. 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
  175. 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
  176. 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
  177. 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
  178. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  179. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  180. 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
  181. 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
  182. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  183. >;
  184. fsl,drive-strength = <0>;
  185. fsl,voltage = <1>;
  186. fsl,pull-up = <0>;
  187. };
  188. gpmi_status_cfg: gpmi-status-cfg {
  189. fsl,pinmux-ids = <
  190. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  191. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  192. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  193. >;
  194. fsl,drive-strength = <2>;
  195. };
  196. auart0_pins_a: auart0@0 {
  197. reg = <0>;
  198. fsl,pinmux-ids = <
  199. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  200. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  201. 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
  202. 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
  203. >;
  204. fsl,drive-strength = <0>;
  205. fsl,voltage = <1>;
  206. fsl,pull-up = <0>;
  207. };
  208. auart0_2pins_a: auart0-2pins@0 {
  209. reg = <0>;
  210. fsl,pinmux-ids = <
  211. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  212. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  213. >;
  214. fsl,drive-strength = <0>;
  215. fsl,voltage = <1>;
  216. fsl,pull-up = <0>;
  217. };
  218. auart3_pins_a: auart3@0 {
  219. reg = <0>;
  220. fsl,pinmux-ids = <
  221. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  222. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  223. 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
  224. 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
  225. >;
  226. fsl,drive-strength = <0>;
  227. fsl,voltage = <1>;
  228. fsl,pull-up = <0>;
  229. };
  230. mac0_pins_a: mac0@0 {
  231. reg = <0>;
  232. fsl,pinmux-ids = <
  233. 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
  234. 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
  235. 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
  236. 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
  237. 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
  238. 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
  239. 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
  240. 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
  241. 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
  242. >;
  243. fsl,drive-strength = <1>;
  244. fsl,voltage = <1>;
  245. fsl,pull-up = <1>;
  246. };
  247. mac1_pins_a: mac1@0 {
  248. reg = <0>;
  249. fsl,pinmux-ids = <
  250. 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
  251. 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
  252. 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
  253. 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
  254. 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
  255. 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
  256. >;
  257. fsl,drive-strength = <1>;
  258. fsl,voltage = <1>;
  259. fsl,pull-up = <1>;
  260. };
  261. mmc0_8bit_pins_a: mmc0-8bit@0 {
  262. reg = <0>;
  263. fsl,pinmux-ids = <
  264. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  265. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  266. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  267. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  268. 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
  269. 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
  270. 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
  271. 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
  272. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  273. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  274. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  275. >;
  276. fsl,drive-strength = <1>;
  277. fsl,voltage = <1>;
  278. fsl,pull-up = <1>;
  279. };
  280. mmc0_4bit_pins_a: mmc0-4bit@0 {
  281. reg = <0>;
  282. fsl,pinmux-ids = <
  283. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  284. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  285. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  286. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  287. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  288. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  289. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  290. >;
  291. fsl,drive-strength = <1>;
  292. fsl,voltage = <1>;
  293. fsl,pull-up = <1>;
  294. };
  295. mmc0_cd_cfg: mmc0-cd-cfg {
  296. fsl,pinmux-ids = <
  297. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  298. >;
  299. fsl,pull-up = <0>;
  300. };
  301. mmc0_sck_cfg: mmc0-sck-cfg {
  302. fsl,pinmux-ids = <
  303. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  304. >;
  305. fsl,drive-strength = <2>;
  306. fsl,pull-up = <0>;
  307. };
  308. i2c0_pins_a: i2c0@0 {
  309. reg = <0>;
  310. fsl,pinmux-ids = <
  311. 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
  312. 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
  313. >;
  314. fsl,drive-strength = <1>;
  315. fsl,voltage = <1>;
  316. fsl,pull-up = <1>;
  317. };
  318. saif0_pins_a: saif0@0 {
  319. reg = <0>;
  320. fsl,pinmux-ids = <
  321. 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
  322. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  323. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  324. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  325. >;
  326. fsl,drive-strength = <2>;
  327. fsl,voltage = <1>;
  328. fsl,pull-up = <1>;
  329. };
  330. saif1_pins_a: saif1@0 {
  331. reg = <0>;
  332. fsl,pinmux-ids = <
  333. 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
  334. >;
  335. fsl,drive-strength = <2>;
  336. fsl,voltage = <1>;
  337. fsl,pull-up = <1>;
  338. };
  339. pwm2_pins_a: pwm2@0 {
  340. reg = <0>;
  341. fsl,pinmux-ids = <
  342. 0x3120 /* MX28_PAD_PWM2__PWM_2 */
  343. >;
  344. fsl,drive-strength = <0>;
  345. fsl,voltage = <1>;
  346. fsl,pull-up = <0>;
  347. };
  348. lcdif_24bit_pins_a: lcdif-24bit@0 {
  349. reg = <0>;
  350. fsl,pinmux-ids = <
  351. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  352. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  353. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  354. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  355. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  356. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  357. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  358. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  359. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  360. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  361. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  362. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  363. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  364. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  365. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  366. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  367. 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
  368. 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
  369. 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
  370. 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
  371. 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
  372. 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
  373. 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
  374. 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
  375. >;
  376. fsl,drive-strength = <0>;
  377. fsl,voltage = <1>;
  378. fsl,pull-up = <0>;
  379. };
  380. can0_pins_a: can0@0 {
  381. reg = <0>;
  382. fsl,pinmux-ids = <
  383. 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
  384. 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
  385. >;
  386. fsl,drive-strength = <0>;
  387. fsl,voltage = <1>;
  388. fsl,pull-up = <0>;
  389. };
  390. can1_pins_a: can1@0 {
  391. reg = <0>;
  392. fsl,pinmux-ids = <
  393. 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
  394. 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
  395. >;
  396. fsl,drive-strength = <0>;
  397. fsl,voltage = <1>;
  398. fsl,pull-up = <0>;
  399. };
  400. };
  401. digctl@8001c000 {
  402. reg = <0x8001c000 2000>;
  403. interrupts = <89>;
  404. status = "disabled";
  405. };
  406. etm@80022000 {
  407. reg = <0x80022000 2000>;
  408. status = "disabled";
  409. };
  410. dma-apbx@80024000 {
  411. compatible = "fsl,imx28-dma-apbx";
  412. reg = <0x80024000 2000>;
  413. };
  414. dcp@80028000 {
  415. reg = <0x80028000 2000>;
  416. interrupts = <52 53 54>;
  417. status = "disabled";
  418. };
  419. pxp@8002a000 {
  420. reg = <0x8002a000 2000>;
  421. interrupts = <39>;
  422. status = "disabled";
  423. };
  424. ocotp@8002c000 {
  425. reg = <0x8002c000 2000>;
  426. status = "disabled";
  427. };
  428. axi-ahb@8002e000 {
  429. reg = <0x8002e000 2000>;
  430. status = "disabled";
  431. };
  432. lcdif@80030000 {
  433. compatible = "fsl,imx28-lcdif";
  434. reg = <0x80030000 2000>;
  435. interrupts = <38 86>;
  436. status = "disabled";
  437. };
  438. can0: can@80032000 {
  439. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  440. reg = <0x80032000 2000>;
  441. interrupts = <8>;
  442. status = "disabled";
  443. };
  444. can1: can@80034000 {
  445. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  446. reg = <0x80034000 2000>;
  447. interrupts = <9>;
  448. status = "disabled";
  449. };
  450. simdbg@8003c000 {
  451. reg = <0x8003c000 200>;
  452. status = "disabled";
  453. };
  454. simgpmisel@8003c200 {
  455. reg = <0x8003c200 100>;
  456. status = "disabled";
  457. };
  458. simsspsel@8003c300 {
  459. reg = <0x8003c300 100>;
  460. status = "disabled";
  461. };
  462. simmemsel@8003c400 {
  463. reg = <0x8003c400 100>;
  464. status = "disabled";
  465. };
  466. gpiomon@8003c500 {
  467. reg = <0x8003c500 100>;
  468. status = "disabled";
  469. };
  470. simenet@8003c700 {
  471. reg = <0x8003c700 100>;
  472. status = "disabled";
  473. };
  474. armjtag@8003c800 {
  475. reg = <0x8003c800 100>;
  476. status = "disabled";
  477. };
  478. };
  479. apbx@80040000 {
  480. compatible = "simple-bus";
  481. #address-cells = <1>;
  482. #size-cells = <1>;
  483. reg = <0x80040000 0x40000>;
  484. ranges;
  485. clkctl@80040000 {
  486. reg = <0x80040000 2000>;
  487. status = "disabled";
  488. };
  489. saif0: saif@80042000 {
  490. compatible = "fsl,imx28-saif";
  491. reg = <0x80042000 2000>;
  492. interrupts = <59 80>;
  493. fsl,saif-dma-channel = <4>;
  494. status = "disabled";
  495. };
  496. power@80044000 {
  497. reg = <0x80044000 2000>;
  498. status = "disabled";
  499. };
  500. saif1: saif@80046000 {
  501. compatible = "fsl,imx28-saif";
  502. reg = <0x80046000 2000>;
  503. interrupts = <58 81>;
  504. fsl,saif-dma-channel = <5>;
  505. status = "disabled";
  506. };
  507. lradc@80050000 {
  508. reg = <0x80050000 2000>;
  509. status = "disabled";
  510. };
  511. spdif@80054000 {
  512. reg = <0x80054000 2000>;
  513. interrupts = <45 66>;
  514. status = "disabled";
  515. };
  516. rtc@80056000 {
  517. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  518. reg = <0x80056000 2000>;
  519. interrupts = <29>;
  520. };
  521. i2c0: i2c@80058000 {
  522. #address-cells = <1>;
  523. #size-cells = <0>;
  524. compatible = "fsl,imx28-i2c";
  525. reg = <0x80058000 2000>;
  526. interrupts = <111 68>;
  527. status = "disabled";
  528. };
  529. i2c1: i2c@8005a000 {
  530. #address-cells = <1>;
  531. #size-cells = <0>;
  532. compatible = "fsl,imx28-i2c";
  533. reg = <0x8005a000 2000>;
  534. interrupts = <110 69>;
  535. status = "disabled";
  536. };
  537. pwm: pwm@80064000 {
  538. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  539. reg = <0x80064000 2000>;
  540. #pwm-cells = <2>;
  541. fsl,pwm-number = <8>;
  542. status = "disabled";
  543. };
  544. timrot@80068000 {
  545. reg = <0x80068000 2000>;
  546. status = "disabled";
  547. };
  548. auart0: serial@8006a000 {
  549. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  550. reg = <0x8006a000 0x2000>;
  551. interrupts = <112 70 71>;
  552. status = "disabled";
  553. };
  554. auart1: serial@8006c000 {
  555. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  556. reg = <0x8006c000 0x2000>;
  557. interrupts = <113 72 73>;
  558. status = "disabled";
  559. };
  560. auart2: serial@8006e000 {
  561. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  562. reg = <0x8006e000 0x2000>;
  563. interrupts = <114 74 75>;
  564. status = "disabled";
  565. };
  566. auart3: serial@80070000 {
  567. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  568. reg = <0x80070000 0x2000>;
  569. interrupts = <115 76 77>;
  570. status = "disabled";
  571. };
  572. auart4: serial@80072000 {
  573. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  574. reg = <0x80072000 0x2000>;
  575. interrupts = <116 78 79>;
  576. status = "disabled";
  577. };
  578. duart: serial@80074000 {
  579. compatible = "arm,pl011", "arm,primecell";
  580. reg = <0x80074000 0x1000>;
  581. interrupts = <47>;
  582. status = "disabled";
  583. };
  584. usbphy0: usbphy@8007c000 {
  585. reg = <0x8007c000 0x2000>;
  586. status = "disabled";
  587. };
  588. usbphy1: usbphy@8007e000 {
  589. reg = <0x8007e000 0x2000>;
  590. status = "disabled";
  591. };
  592. };
  593. };
  594. ahb@80080000 {
  595. compatible = "simple-bus";
  596. #address-cells = <1>;
  597. #size-cells = <1>;
  598. reg = <0x80080000 0x80000>;
  599. ranges;
  600. usbctrl0: usbctrl@80080000 {
  601. reg = <0x80080000 0x10000>;
  602. status = "disabled";
  603. };
  604. usbctrl1: usbctrl@80090000 {
  605. reg = <0x80090000 0x10000>;
  606. status = "disabled";
  607. };
  608. dflpt@800c0000 {
  609. reg = <0x800c0000 0x10000>;
  610. status = "disabled";
  611. };
  612. mac0: ethernet@800f0000 {
  613. compatible = "fsl,imx28-fec";
  614. reg = <0x800f0000 0x4000>;
  615. interrupts = <101>;
  616. status = "disabled";
  617. };
  618. mac1: ethernet@800f4000 {
  619. compatible = "fsl,imx28-fec";
  620. reg = <0x800f4000 0x4000>;
  621. interrupts = <102>;
  622. status = "disabled";
  623. };
  624. switch@800f8000 {
  625. reg = <0x800f8000 0x8000>;
  626. status = "disabled";
  627. };
  628. };
  629. };