langwell_otg.h 4.7 KB

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  1. /*
  2. * Intel Langwell USB OTG transceiver driver
  3. * Copyright (C) 2008, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. #ifndef __LANGWELL_OTG_H__
  20. #define __LANGWELL_OTG_H__
  21. /* notify transceiver driver about OTG events */
  22. extern void langwell_update_transceiver(void);
  23. /* HCD register bus driver */
  24. extern int langwell_register_host(struct pci_driver *host_driver);
  25. /* HCD unregister bus driver */
  26. extern void langwell_unregister_host(struct pci_driver *host_driver);
  27. /* DCD register bus driver */
  28. extern int langwell_register_peripheral(struct pci_driver *client_driver);
  29. /* DCD unregister bus driver */
  30. extern void langwell_unregister_peripheral(struct pci_driver *client_driver);
  31. /* No silent failure, output warning message */
  32. extern void langwell_otg_nsf_msg(unsigned long message);
  33. #define CI_USBCMD 0x30
  34. # define USBCMD_RST BIT(1)
  35. # define USBCMD_RS BIT(0)
  36. #define CI_USBSTS 0x34
  37. # define USBSTS_SLI BIT(8)
  38. # define USBSTS_URI BIT(6)
  39. # define USBSTS_PCI BIT(2)
  40. #define CI_PORTSC1 0x74
  41. # define PORTSC_PP BIT(12)
  42. # define PORTSC_LS (BIT(11) | BIT(10))
  43. # define PORTSC_SUSP BIT(7)
  44. # define PORTSC_CCS BIT(0)
  45. #define CI_HOSTPC1 0xb4
  46. # define HOSTPC1_PHCD BIT(22)
  47. #define CI_OTGSC 0xf4
  48. # define OTGSC_DPIE BIT(30)
  49. # define OTGSC_1MSE BIT(29)
  50. # define OTGSC_BSEIE BIT(28)
  51. # define OTGSC_BSVIE BIT(27)
  52. # define OTGSC_ASVIE BIT(26)
  53. # define OTGSC_AVVIE BIT(25)
  54. # define OTGSC_IDIE BIT(24)
  55. # define OTGSC_DPIS BIT(22)
  56. # define OTGSC_1MSS BIT(21)
  57. # define OTGSC_BSEIS BIT(20)
  58. # define OTGSC_BSVIS BIT(19)
  59. # define OTGSC_ASVIS BIT(18)
  60. # define OTGSC_AVVIS BIT(17)
  61. # define OTGSC_IDIS BIT(16)
  62. # define OTGSC_DPS BIT(14)
  63. # define OTGSC_1MST BIT(13)
  64. # define OTGSC_BSE BIT(12)
  65. # define OTGSC_BSV BIT(11)
  66. # define OTGSC_ASV BIT(10)
  67. # define OTGSC_AVV BIT(9)
  68. # define OTGSC_ID BIT(8)
  69. # define OTGSC_HABA BIT(7)
  70. # define OTGSC_HADP BIT(6)
  71. # define OTGSC_IDPU BIT(5)
  72. # define OTGSC_DP BIT(4)
  73. # define OTGSC_OT BIT(3)
  74. # define OTGSC_HAAR BIT(2)
  75. # define OTGSC_VC BIT(1)
  76. # define OTGSC_VD BIT(0)
  77. # define OTGSC_INTEN_MASK (0x7f << 24)
  78. # define OTGSC_INTSTS_MASK (0x7f << 16)
  79. #define CI_USBMODE 0xf8
  80. # define USBMODE_CM (BIT(1) | BIT(0))
  81. # define USBMODE_IDLE 0
  82. # define USBMODE_DEVICE 0x2
  83. # define USBMODE_HOST 0x3
  84. #define INTR_DUMMY_MASK (USBSTS_SLI | USBSTS_URI | USBSTS_PCI)
  85. struct otg_hsm {
  86. /* Input */
  87. int a_bus_resume;
  88. int a_bus_suspend;
  89. int a_conn;
  90. int a_sess_vld;
  91. int a_srp_det;
  92. int a_vbus_vld;
  93. int b_bus_resume;
  94. int b_bus_suspend;
  95. int b_conn;
  96. int b_se0_srp;
  97. int b_sess_end;
  98. int b_sess_vld;
  99. int id;
  100. /* Internal variables */
  101. int a_set_b_hnp_en;
  102. int b_srp_done;
  103. int b_hnp_enable;
  104. /* Timeout indicator for timers */
  105. int a_wait_vrise_tmout;
  106. int a_wait_bcon_tmout;
  107. int a_aidl_bdis_tmout;
  108. int b_ase0_brst_tmout;
  109. int b_bus_suspend_tmout;
  110. int b_srp_res_tmout;
  111. /* Informative variables */
  112. int a_bus_drop;
  113. int a_bus_req;
  114. int a_clr_err;
  115. int a_suspend_req;
  116. int b_bus_req;
  117. /* Output */
  118. int drv_vbus;
  119. int loc_conn;
  120. int loc_sof;
  121. /* Others */
  122. int b_bus_suspend_vld;
  123. };
  124. #define TA_WAIT_VRISE 100
  125. #define TA_WAIT_BCON 30000
  126. #define TA_AIDL_BDIS 15000
  127. #define TB_ASE0_BRST 5000
  128. #define TB_SE0_SRP 2
  129. #define TB_SRP_RES 100
  130. #define TB_BUS_SUSPEND 500
  131. struct langwell_otg_timer {
  132. unsigned long expires; /* Number of count increase to timeout */
  133. unsigned long count; /* Tick counter */
  134. void (*function)(unsigned long); /* Timeout function */
  135. unsigned long data; /* Data passed to function */
  136. struct list_head list;
  137. };
  138. struct langwell_otg {
  139. struct otg_transceiver otg;
  140. struct otg_hsm hsm;
  141. void __iomem *regs;
  142. unsigned region;
  143. struct pci_driver *host_ops;
  144. struct pci_driver *client_ops;
  145. struct pci_dev *pdev;
  146. struct work_struct work;
  147. struct workqueue_struct *qwork;
  148. spinlock_t lock;
  149. spinlock_t wq_lock;
  150. };
  151. static inline struct langwell_otg *otg_to_langwell(struct otg_transceiver *otg)
  152. {
  153. return container_of(otg, struct langwell_otg, otg);
  154. }
  155. #ifdef DEBUG
  156. #define otg_dbg(fmt, args...) \
  157. printk(KERN_DEBUG fmt , ## args)
  158. #else
  159. #define otg_dbg(fmt, args...) \
  160. do { } while (0)
  161. #endif /* DEBUG */
  162. #endif /* __LANGWELL_OTG_H__ */